1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* 3 * Copyright (C) 2005-2014, 2018-2019, 2021 Intel Corporation 4 */ 5 #include <linux/types.h> 6 #include <linux/slab.h> 7 #include <linux/export.h> 8 #if defined(__FreeBSD__) 9 #include <linux/delay.h> 10 #endif 11 12 #include "iwl-drv.h" 13 #include "iwl-debug.h" 14 #include "iwl-eeprom-read.h" 15 #include "iwl-io.h" 16 #include "iwl-prph.h" 17 #include "iwl-csr.h" 18 19 /* 20 * EEPROM access time values: 21 * 22 * Driver initiates EEPROM read by writing byte address << 1 to CSR_EEPROM_REG. 23 * Driver then polls CSR_EEPROM_REG for CSR_EEPROM_REG_READ_VALID_MSK (0x1). 24 * When polling, wait 10 uSec between polling loops, up to a maximum 5000 uSec. 25 * Driver reads 16-bit value from bits 31-16 of CSR_EEPROM_REG. 26 */ 27 #define IWL_EEPROM_ACCESS_TIMEOUT 5000 /* uSec */ 28 29 /* 30 * The device's EEPROM semaphore prevents conflicts between driver and uCode 31 * when accessing the EEPROM; each access is a series of pulses to/from the 32 * EEPROM chip, not a single event, so even reads could conflict if they 33 * weren't arbitrated by the semaphore. 34 */ 35 #define IWL_EEPROM_SEM_TIMEOUT 10 /* microseconds */ 36 #define IWL_EEPROM_SEM_RETRY_LIMIT 1000 /* number of attempts (not time) */ 37 38 39 static int iwl_eeprom_acquire_semaphore(struct iwl_trans *trans) 40 { 41 u16 count; 42 int ret; 43 44 for (count = 0; count < IWL_EEPROM_SEM_RETRY_LIMIT; count++) { 45 /* Request semaphore */ 46 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 47 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM); 48 49 /* See if we got it */ 50 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG, 51 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM, 52 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM, 53 IWL_EEPROM_SEM_TIMEOUT); 54 if (ret >= 0) { 55 IWL_DEBUG_EEPROM(trans->dev, 56 "Acquired semaphore after %d tries.\n", 57 count+1); 58 return ret; 59 } 60 } 61 62 return ret; 63 } 64 65 static void iwl_eeprom_release_semaphore(struct iwl_trans *trans) 66 { 67 iwl_clear_bit(trans, CSR_HW_IF_CONFIG_REG, 68 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM); 69 } 70 71 static int iwl_eeprom_verify_signature(struct iwl_trans *trans, bool nvm_is_otp) 72 { 73 u32 gp = iwl_read32(trans, CSR_EEPROM_GP) & CSR_EEPROM_GP_VALID_MSK; 74 75 IWL_DEBUG_EEPROM(trans->dev, "EEPROM signature=0x%08x\n", gp); 76 77 switch (gp) { 78 case CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP: 79 if (!nvm_is_otp) { 80 IWL_ERR(trans, "EEPROM with bad signature: 0x%08x\n", 81 gp); 82 return -ENOENT; 83 } 84 return 0; 85 case CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K: 86 case CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K: 87 if (nvm_is_otp) { 88 IWL_ERR(trans, "OTP with bad signature: 0x%08x\n", gp); 89 return -ENOENT; 90 } 91 return 0; 92 case CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP: 93 default: 94 IWL_ERR(trans, 95 "bad EEPROM/OTP signature, type=%s, EEPROM_GP=0x%08x\n", 96 nvm_is_otp ? "OTP" : "EEPROM", gp); 97 return -ENOENT; 98 } 99 } 100 101 /****************************************************************************** 102 * 103 * OTP related functions 104 * 105 ******************************************************************************/ 106 107 static void iwl_set_otp_access_absolute(struct iwl_trans *trans) 108 { 109 iwl_read32(trans, CSR_OTP_GP_REG); 110 111 iwl_clear_bit(trans, CSR_OTP_GP_REG, 112 CSR_OTP_GP_REG_OTP_ACCESS_MODE); 113 } 114 115 static int iwl_nvm_is_otp(struct iwl_trans *trans) 116 { 117 u32 otpgp; 118 119 /* OTP only valid for CP/PP and after */ 120 switch (trans->hw_rev & CSR_HW_REV_TYPE_MSK) { 121 case CSR_HW_REV_TYPE_NONE: 122 IWL_ERR(trans, "Unknown hardware type\n"); 123 return -EIO; 124 case CSR_HW_REV_TYPE_5300: 125 case CSR_HW_REV_TYPE_5350: 126 case CSR_HW_REV_TYPE_5100: 127 case CSR_HW_REV_TYPE_5150: 128 return 0; 129 default: 130 otpgp = iwl_read32(trans, CSR_OTP_GP_REG); 131 if (otpgp & CSR_OTP_GP_REG_DEVICE_SELECT) 132 return 1; 133 return 0; 134 } 135 } 136 137 static int iwl_init_otp_access(struct iwl_trans *trans) 138 { 139 int ret; 140 141 ret = iwl_finish_nic_init(trans); 142 if (ret) 143 return ret; 144 145 iwl_set_bits_prph(trans, APMG_PS_CTRL_REG, 146 APMG_PS_CTRL_VAL_RESET_REQ); 147 udelay(5); 148 iwl_clear_bits_prph(trans, APMG_PS_CTRL_REG, 149 APMG_PS_CTRL_VAL_RESET_REQ); 150 151 /* 152 * CSR auto clock gate disable bit - 153 * this is only applicable for HW with OTP shadow RAM 154 */ 155 if (trans->trans_cfg->base_params->shadow_ram_support) 156 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 157 CSR_RESET_LINK_PWR_MGMT_DISABLED); 158 159 return 0; 160 } 161 162 static int iwl_read_otp_word(struct iwl_trans *trans, u16 addr, 163 __le16 *eeprom_data) 164 { 165 int ret = 0; 166 u32 r; 167 u32 otpgp; 168 169 iwl_write32(trans, CSR_EEPROM_REG, 170 CSR_EEPROM_REG_MSK_ADDR & (addr << 1)); 171 ret = iwl_poll_bit(trans, CSR_EEPROM_REG, 172 CSR_EEPROM_REG_READ_VALID_MSK, 173 CSR_EEPROM_REG_READ_VALID_MSK, 174 IWL_EEPROM_ACCESS_TIMEOUT); 175 if (ret < 0) { 176 IWL_ERR(trans, "Time out reading OTP[%d]\n", addr); 177 return ret; 178 } 179 r = iwl_read32(trans, CSR_EEPROM_REG); 180 /* check for ECC errors: */ 181 otpgp = iwl_read32(trans, CSR_OTP_GP_REG); 182 if (otpgp & CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK) { 183 /* stop in this case */ 184 /* set the uncorrectable OTP ECC bit for acknowledgment */ 185 iwl_set_bit(trans, CSR_OTP_GP_REG, 186 CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK); 187 IWL_ERR(trans, "Uncorrectable OTP ECC error, abort OTP read\n"); 188 return -EINVAL; 189 } 190 if (otpgp & CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK) { 191 /* continue in this case */ 192 /* set the correctable OTP ECC bit for acknowledgment */ 193 iwl_set_bit(trans, CSR_OTP_GP_REG, 194 CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK); 195 IWL_ERR(trans, "Correctable OTP ECC error, continue read\n"); 196 } 197 *eeprom_data = cpu_to_le16(r >> 16); 198 return 0; 199 } 200 201 /* 202 * iwl_is_otp_empty: check for empty OTP 203 */ 204 static bool iwl_is_otp_empty(struct iwl_trans *trans) 205 { 206 u16 next_link_addr = 0; 207 __le16 link_value; 208 bool is_empty = false; 209 210 /* locate the beginning of OTP link list */ 211 if (!iwl_read_otp_word(trans, next_link_addr, &link_value)) { 212 if (!link_value) { 213 IWL_ERR(trans, "OTP is empty\n"); 214 is_empty = true; 215 } 216 } else { 217 IWL_ERR(trans, "Unable to read first block of OTP list.\n"); 218 is_empty = true; 219 } 220 221 return is_empty; 222 } 223 224 225 /* 226 * iwl_find_otp_image: find EEPROM image in OTP 227 * finding the OTP block that contains the EEPROM image. 228 * the last valid block on the link list (the block _before_ the last block) 229 * is the block we should read and used to configure the device. 230 * If all the available OTP blocks are full, the last block will be the block 231 * we should read and used to configure the device. 232 * only perform this operation if shadow RAM is disabled 233 */ 234 static int iwl_find_otp_image(struct iwl_trans *trans, 235 u16 *validblockaddr) 236 { 237 u16 next_link_addr = 0, valid_addr; 238 __le16 link_value = 0; 239 int usedblocks = 0; 240 241 /* set addressing mode to absolute to traverse the link list */ 242 iwl_set_otp_access_absolute(trans); 243 244 /* checking for empty OTP or error */ 245 if (iwl_is_otp_empty(trans)) 246 return -EINVAL; 247 248 /* 249 * start traverse link list 250 * until reach the max number of OTP blocks 251 * different devices have different number of OTP blocks 252 */ 253 do { 254 /* save current valid block address 255 * check for more block on the link list 256 */ 257 valid_addr = next_link_addr; 258 next_link_addr = le16_to_cpu(link_value) * sizeof(u16); 259 IWL_DEBUG_EEPROM(trans->dev, "OTP blocks %d addr 0x%x\n", 260 usedblocks, next_link_addr); 261 if (iwl_read_otp_word(trans, next_link_addr, &link_value)) 262 return -EINVAL; 263 if (!link_value) { 264 /* 265 * reach the end of link list, return success and 266 * set address point to the starting address 267 * of the image 268 */ 269 *validblockaddr = valid_addr; 270 /* skip first 2 bytes (link list pointer) */ 271 *validblockaddr += 2; 272 return 0; 273 } 274 /* more in the link list, continue */ 275 usedblocks++; 276 } while (usedblocks <= trans->trans_cfg->base_params->max_ll_items); 277 278 /* OTP has no valid blocks */ 279 IWL_DEBUG_EEPROM(trans->dev, "OTP has no valid blocks\n"); 280 return -EINVAL; 281 } 282 283 /* 284 * iwl_read_eeprom - read EEPROM contents 285 * 286 * Load the EEPROM contents from adapter and return it 287 * and its size. 288 * 289 * NOTE: This routine uses the non-debug IO access functions. 290 */ 291 int iwl_read_eeprom(struct iwl_trans *trans, u8 **eeprom, size_t *eeprom_size) 292 { 293 __le16 *e; 294 u32 gp = iwl_read32(trans, CSR_EEPROM_GP); 295 int sz; 296 int ret; 297 u16 addr; 298 u16 validblockaddr = 0; 299 u16 cache_addr = 0; 300 int nvm_is_otp; 301 302 if (!eeprom || !eeprom_size) 303 return -EINVAL; 304 305 nvm_is_otp = iwl_nvm_is_otp(trans); 306 if (nvm_is_otp < 0) 307 return nvm_is_otp; 308 309 sz = trans->trans_cfg->base_params->eeprom_size; 310 IWL_DEBUG_EEPROM(trans->dev, "NVM size = %d\n", sz); 311 312 e = kmalloc(sz, GFP_KERNEL); 313 if (!e) 314 return -ENOMEM; 315 316 ret = iwl_eeprom_verify_signature(trans, nvm_is_otp); 317 if (ret < 0) { 318 IWL_ERR(trans, "EEPROM not found, EEPROM_GP=0x%08x\n", gp); 319 goto err_free; 320 } 321 322 /* Make sure driver (instead of uCode) is allowed to read EEPROM */ 323 ret = iwl_eeprom_acquire_semaphore(trans); 324 if (ret < 0) { 325 IWL_ERR(trans, "Failed to acquire EEPROM semaphore.\n"); 326 goto err_free; 327 } 328 329 if (nvm_is_otp) { 330 ret = iwl_init_otp_access(trans); 331 if (ret) { 332 IWL_ERR(trans, "Failed to initialize OTP access.\n"); 333 goto err_unlock; 334 } 335 336 iwl_write32(trans, CSR_EEPROM_GP, 337 iwl_read32(trans, CSR_EEPROM_GP) & 338 ~CSR_EEPROM_GP_IF_OWNER_MSK); 339 340 iwl_set_bit(trans, CSR_OTP_GP_REG, 341 CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK | 342 CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK); 343 /* traversing the linked list if no shadow ram supported */ 344 if (!trans->trans_cfg->base_params->shadow_ram_support) { 345 ret = iwl_find_otp_image(trans, &validblockaddr); 346 if (ret) 347 goto err_unlock; 348 } 349 for (addr = validblockaddr; addr < validblockaddr + sz; 350 addr += sizeof(u16)) { 351 __le16 eeprom_data; 352 353 ret = iwl_read_otp_word(trans, addr, &eeprom_data); 354 if (ret) 355 goto err_unlock; 356 e[cache_addr / 2] = eeprom_data; 357 cache_addr += sizeof(u16); 358 } 359 } else { 360 /* eeprom is an array of 16bit values */ 361 for (addr = 0; addr < sz; addr += sizeof(u16)) { 362 u32 r; 363 364 iwl_write32(trans, CSR_EEPROM_REG, 365 CSR_EEPROM_REG_MSK_ADDR & (addr << 1)); 366 367 ret = iwl_poll_bit(trans, CSR_EEPROM_REG, 368 CSR_EEPROM_REG_READ_VALID_MSK, 369 CSR_EEPROM_REG_READ_VALID_MSK, 370 IWL_EEPROM_ACCESS_TIMEOUT); 371 if (ret < 0) { 372 IWL_ERR(trans, 373 "Time out reading EEPROM[%d]\n", addr); 374 goto err_unlock; 375 } 376 r = iwl_read32(trans, CSR_EEPROM_REG); 377 e[addr / 2] = cpu_to_le16(r >> 16); 378 } 379 } 380 381 IWL_DEBUG_EEPROM(trans->dev, "NVM Type: %s\n", 382 nvm_is_otp ? "OTP" : "EEPROM"); 383 384 iwl_eeprom_release_semaphore(trans); 385 386 *eeprom_size = sz; 387 *eeprom = (u8 *)e; 388 return 0; 389 390 err_unlock: 391 iwl_eeprom_release_semaphore(trans); 392 err_free: 393 kfree(e); 394 395 return ret; 396 } 397 IWL_EXPORT_SYMBOL(iwl_read_eeprom); 398