1bfcc09ddSBjoern A. Zeeb /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2bfcc09ddSBjoern A. Zeeb /* 3bfcc09ddSBjoern A. Zeeb * Copyright (C) 2003-2015, 2018-2021 Intel Corporation 4bfcc09ddSBjoern A. Zeeb * Copyright (C) 2013-2015 Intel Mobile Communications GmbH 5bfcc09ddSBjoern A. Zeeb * Copyright (C) 2016-2017 Intel Deutschland GmbH 6bfcc09ddSBjoern A. Zeeb */ 7bfcc09ddSBjoern A. Zeeb #ifndef __iwl_trans_int_pcie_h__ 8bfcc09ddSBjoern A. Zeeb #define __iwl_trans_int_pcie_h__ 9bfcc09ddSBjoern A. Zeeb 10bfcc09ddSBjoern A. Zeeb #include <linux/spinlock.h> 11bfcc09ddSBjoern A. Zeeb #include <linux/interrupt.h> 12bfcc09ddSBjoern A. Zeeb #include <linux/skbuff.h> 13bfcc09ddSBjoern A. Zeeb #include <linux/wait.h> 14bfcc09ddSBjoern A. Zeeb #include <linux/pci.h> 15bfcc09ddSBjoern A. Zeeb #include <linux/timer.h> 16bfcc09ddSBjoern A. Zeeb #include <linux/cpu.h> 17bfcc09ddSBjoern A. Zeeb 18bfcc09ddSBjoern A. Zeeb #include "iwl-fh.h" 19bfcc09ddSBjoern A. Zeeb #include "iwl-csr.h" 20bfcc09ddSBjoern A. Zeeb #include "iwl-trans.h" 21bfcc09ddSBjoern A. Zeeb #include "iwl-debug.h" 22bfcc09ddSBjoern A. Zeeb #include "iwl-io.h" 23bfcc09ddSBjoern A. Zeeb #include "iwl-op-mode.h" 24bfcc09ddSBjoern A. Zeeb #include "iwl-drv.h" 25bfcc09ddSBjoern A. Zeeb #include "queue/tx.h" 26bfcc09ddSBjoern A. Zeeb 27bfcc09ddSBjoern A. Zeeb /* 28bfcc09ddSBjoern A. Zeeb * RX related structures and functions 29bfcc09ddSBjoern A. Zeeb */ 30bfcc09ddSBjoern A. Zeeb #define RX_NUM_QUEUES 1 31bfcc09ddSBjoern A. Zeeb #define RX_POST_REQ_ALLOC 2 32bfcc09ddSBjoern A. Zeeb #define RX_CLAIM_REQ_ALLOC 8 33bfcc09ddSBjoern A. Zeeb #define RX_PENDING_WATERMARK 16 34bfcc09ddSBjoern A. Zeeb #define FIRST_RX_QUEUE 512 35bfcc09ddSBjoern A. Zeeb 36bfcc09ddSBjoern A. Zeeb struct iwl_host_cmd; 37bfcc09ddSBjoern A. Zeeb 38bfcc09ddSBjoern A. Zeeb /*This file includes the declaration that are internal to the 39bfcc09ddSBjoern A. Zeeb * trans_pcie layer */ 40bfcc09ddSBjoern A. Zeeb 41bfcc09ddSBjoern A. Zeeb /** 42bfcc09ddSBjoern A. Zeeb * struct iwl_rx_mem_buffer 43bfcc09ddSBjoern A. Zeeb * @page_dma: bus address of rxb page 44bfcc09ddSBjoern A. Zeeb * @page: driver's pointer to the rxb page 45bfcc09ddSBjoern A. Zeeb * @list: list entry for the membuffer 46bfcc09ddSBjoern A. Zeeb * @invalid: rxb is in driver ownership - not owned by HW 47bfcc09ddSBjoern A. Zeeb * @vid: index of this rxb in the global table 48bfcc09ddSBjoern A. Zeeb * @offset: indicates which offset of the page (in bytes) 49bfcc09ddSBjoern A. Zeeb * this buffer uses (if multiple RBs fit into one page) 50bfcc09ddSBjoern A. Zeeb */ 51bfcc09ddSBjoern A. Zeeb struct iwl_rx_mem_buffer { 52bfcc09ddSBjoern A. Zeeb dma_addr_t page_dma; 53bfcc09ddSBjoern A. Zeeb struct page *page; 54bfcc09ddSBjoern A. Zeeb struct list_head list; 55bfcc09ddSBjoern A. Zeeb u32 offset; 56bfcc09ddSBjoern A. Zeeb u16 vid; 57bfcc09ddSBjoern A. Zeeb bool invalid; 58bfcc09ddSBjoern A. Zeeb }; 59bfcc09ddSBjoern A. Zeeb 60bfcc09ddSBjoern A. Zeeb /** 61bfcc09ddSBjoern A. Zeeb * struct isr_statistics - interrupt statistics 62bfcc09ddSBjoern A. Zeeb * 63bfcc09ddSBjoern A. Zeeb */ 64bfcc09ddSBjoern A. Zeeb struct isr_statistics { 65bfcc09ddSBjoern A. Zeeb u32 hw; 66bfcc09ddSBjoern A. Zeeb u32 sw; 67bfcc09ddSBjoern A. Zeeb u32 err_code; 68bfcc09ddSBjoern A. Zeeb u32 sch; 69bfcc09ddSBjoern A. Zeeb u32 alive; 70bfcc09ddSBjoern A. Zeeb u32 rfkill; 71bfcc09ddSBjoern A. Zeeb u32 ctkill; 72bfcc09ddSBjoern A. Zeeb u32 wakeup; 73bfcc09ddSBjoern A. Zeeb u32 rx; 74bfcc09ddSBjoern A. Zeeb u32 tx; 75bfcc09ddSBjoern A. Zeeb u32 unhandled; 76bfcc09ddSBjoern A. Zeeb }; 77bfcc09ddSBjoern A. Zeeb 78bfcc09ddSBjoern A. Zeeb /** 79bfcc09ddSBjoern A. Zeeb * struct iwl_rx_transfer_desc - transfer descriptor 80bfcc09ddSBjoern A. Zeeb * @addr: ptr to free buffer start address 81bfcc09ddSBjoern A. Zeeb * @rbid: unique tag of the buffer 82bfcc09ddSBjoern A. Zeeb * @reserved: reserved 83bfcc09ddSBjoern A. Zeeb */ 84bfcc09ddSBjoern A. Zeeb struct iwl_rx_transfer_desc { 85bfcc09ddSBjoern A. Zeeb __le16 rbid; 86bfcc09ddSBjoern A. Zeeb __le16 reserved[3]; 87bfcc09ddSBjoern A. Zeeb __le64 addr; 88bfcc09ddSBjoern A. Zeeb } __packed; 89bfcc09ddSBjoern A. Zeeb 90bfcc09ddSBjoern A. Zeeb #define IWL_RX_CD_FLAGS_FRAGMENTED BIT(0) 91bfcc09ddSBjoern A. Zeeb 92bfcc09ddSBjoern A. Zeeb /** 93bfcc09ddSBjoern A. Zeeb * struct iwl_rx_completion_desc - completion descriptor 94bfcc09ddSBjoern A. Zeeb * @reserved1: reserved 95bfcc09ddSBjoern A. Zeeb * @rbid: unique tag of the received buffer 96bfcc09ddSBjoern A. Zeeb * @flags: flags (0: fragmented, all others: reserved) 97bfcc09ddSBjoern A. Zeeb * @reserved2: reserved 98bfcc09ddSBjoern A. Zeeb */ 99bfcc09ddSBjoern A. Zeeb struct iwl_rx_completion_desc { 100bfcc09ddSBjoern A. Zeeb __le32 reserved1; 101bfcc09ddSBjoern A. Zeeb __le16 rbid; 102bfcc09ddSBjoern A. Zeeb u8 flags; 103bfcc09ddSBjoern A. Zeeb u8 reserved2[25]; 104bfcc09ddSBjoern A. Zeeb } __packed; 105bfcc09ddSBjoern A. Zeeb 106bfcc09ddSBjoern A. Zeeb /** 107bfcc09ddSBjoern A. Zeeb * struct iwl_rxq - Rx queue 108bfcc09ddSBjoern A. Zeeb * @id: queue index 109bfcc09ddSBjoern A. Zeeb * @bd: driver's pointer to buffer of receive buffer descriptors (rbd). 110bfcc09ddSBjoern A. Zeeb * Address size is 32 bit in pre-9000 devices and 64 bit in 9000 devices. 111bfcc09ddSBjoern A. Zeeb * In AX210 devices it is a pointer to a list of iwl_rx_transfer_desc's 112bfcc09ddSBjoern A. Zeeb * @bd_dma: bus address of buffer of receive buffer descriptors (rbd) 113bfcc09ddSBjoern A. Zeeb * @used_bd: driver's pointer to buffer of used receive buffer descriptors (rbd) 114bfcc09ddSBjoern A. Zeeb * @used_bd_dma: physical address of buffer of used receive buffer descriptors (rbd) 115bfcc09ddSBjoern A. Zeeb * @read: Shared index to newest available Rx buffer 116bfcc09ddSBjoern A. Zeeb * @write: Shared index to oldest written Rx packet 117bfcc09ddSBjoern A. Zeeb * @free_count: Number of pre-allocated buffers in rx_free 118bfcc09ddSBjoern A. Zeeb * @used_count: Number of RBDs handled to allocator to use for allocation 119bfcc09ddSBjoern A. Zeeb * @write_actual: 120bfcc09ddSBjoern A. Zeeb * @rx_free: list of RBDs with allocated RB ready for use 121bfcc09ddSBjoern A. Zeeb * @rx_used: list of RBDs with no RB attached 122bfcc09ddSBjoern A. Zeeb * @need_update: flag to indicate we need to update read/write index 123bfcc09ddSBjoern A. Zeeb * @rb_stts: driver's pointer to receive buffer status 124bfcc09ddSBjoern A. Zeeb * @rb_stts_dma: bus address of receive buffer status 125bfcc09ddSBjoern A. Zeeb * @lock: 126bfcc09ddSBjoern A. Zeeb * @queue: actual rx queue. Not used for multi-rx queue. 127bfcc09ddSBjoern A. Zeeb * @next_rb_is_fragment: indicates that the previous RB that we handled set 128bfcc09ddSBjoern A. Zeeb * the fragmented flag, so the next one is still another fragment 129bfcc09ddSBjoern A. Zeeb * 130bfcc09ddSBjoern A. Zeeb * NOTE: rx_free and rx_used are used as a FIFO for iwl_rx_mem_buffers 131bfcc09ddSBjoern A. Zeeb */ 132bfcc09ddSBjoern A. Zeeb struct iwl_rxq { 133bfcc09ddSBjoern A. Zeeb int id; 134bfcc09ddSBjoern A. Zeeb void *bd; 135bfcc09ddSBjoern A. Zeeb dma_addr_t bd_dma; 136bfcc09ddSBjoern A. Zeeb union { 137bfcc09ddSBjoern A. Zeeb void *used_bd; 138bfcc09ddSBjoern A. Zeeb __le32 *bd_32; 139bfcc09ddSBjoern A. Zeeb struct iwl_rx_completion_desc *cd; 140bfcc09ddSBjoern A. Zeeb }; 141bfcc09ddSBjoern A. Zeeb dma_addr_t used_bd_dma; 142bfcc09ddSBjoern A. Zeeb u32 read; 143bfcc09ddSBjoern A. Zeeb u32 write; 144bfcc09ddSBjoern A. Zeeb u32 free_count; 145bfcc09ddSBjoern A. Zeeb u32 used_count; 146bfcc09ddSBjoern A. Zeeb u32 write_actual; 147bfcc09ddSBjoern A. Zeeb u32 queue_size; 148bfcc09ddSBjoern A. Zeeb struct list_head rx_free; 149bfcc09ddSBjoern A. Zeeb struct list_head rx_used; 150bfcc09ddSBjoern A. Zeeb bool need_update, next_rb_is_fragment; 151bfcc09ddSBjoern A. Zeeb void *rb_stts; 152bfcc09ddSBjoern A. Zeeb dma_addr_t rb_stts_dma; 153bfcc09ddSBjoern A. Zeeb spinlock_t lock; 154bfcc09ddSBjoern A. Zeeb struct napi_struct napi; 155bfcc09ddSBjoern A. Zeeb struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE]; 156bfcc09ddSBjoern A. Zeeb }; 157bfcc09ddSBjoern A. Zeeb 158bfcc09ddSBjoern A. Zeeb /** 159bfcc09ddSBjoern A. Zeeb * struct iwl_rb_allocator - Rx allocator 160bfcc09ddSBjoern A. Zeeb * @req_pending: number of requests the allcator had not processed yet 161bfcc09ddSBjoern A. Zeeb * @req_ready: number of requests honored and ready for claiming 162bfcc09ddSBjoern A. Zeeb * @rbd_allocated: RBDs with pages allocated and ready to be handled to 163bfcc09ddSBjoern A. Zeeb * the queue. This is a list of &struct iwl_rx_mem_buffer 164bfcc09ddSBjoern A. Zeeb * @rbd_empty: RBDs with no page attached for allocator use. This is a list 165bfcc09ddSBjoern A. Zeeb * of &struct iwl_rx_mem_buffer 166bfcc09ddSBjoern A. Zeeb * @lock: protects the rbd_allocated and rbd_empty lists 167bfcc09ddSBjoern A. Zeeb * @alloc_wq: work queue for background calls 168bfcc09ddSBjoern A. Zeeb * @rx_alloc: work struct for background calls 169bfcc09ddSBjoern A. Zeeb */ 170bfcc09ddSBjoern A. Zeeb struct iwl_rb_allocator { 171bfcc09ddSBjoern A. Zeeb atomic_t req_pending; 172bfcc09ddSBjoern A. Zeeb atomic_t req_ready; 173bfcc09ddSBjoern A. Zeeb struct list_head rbd_allocated; 174bfcc09ddSBjoern A. Zeeb struct list_head rbd_empty; 175bfcc09ddSBjoern A. Zeeb spinlock_t lock; 176bfcc09ddSBjoern A. Zeeb struct workqueue_struct *alloc_wq; 177bfcc09ddSBjoern A. Zeeb struct work_struct rx_alloc; 178bfcc09ddSBjoern A. Zeeb }; 179bfcc09ddSBjoern A. Zeeb 180bfcc09ddSBjoern A. Zeeb /** 181bfcc09ddSBjoern A. Zeeb * iwl_get_closed_rb_stts - get closed rb stts from different structs 182bfcc09ddSBjoern A. Zeeb * @rxq - the rxq to get the rb stts from 183bfcc09ddSBjoern A. Zeeb */ 184bfcc09ddSBjoern A. Zeeb static inline __le16 iwl_get_closed_rb_stts(struct iwl_trans *trans, 185bfcc09ddSBjoern A. Zeeb struct iwl_rxq *rxq) 186bfcc09ddSBjoern A. Zeeb { 187bfcc09ddSBjoern A. Zeeb if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 188bfcc09ddSBjoern A. Zeeb __le16 *rb_stts = rxq->rb_stts; 189bfcc09ddSBjoern A. Zeeb 190bfcc09ddSBjoern A. Zeeb return READ_ONCE(*rb_stts); 191bfcc09ddSBjoern A. Zeeb } else { 192bfcc09ddSBjoern A. Zeeb struct iwl_rb_status *rb_stts = rxq->rb_stts; 193bfcc09ddSBjoern A. Zeeb 194bfcc09ddSBjoern A. Zeeb return READ_ONCE(rb_stts->closed_rb_num); 195bfcc09ddSBjoern A. Zeeb } 196bfcc09ddSBjoern A. Zeeb } 197bfcc09ddSBjoern A. Zeeb 198bfcc09ddSBjoern A. Zeeb #ifdef CONFIG_IWLWIFI_DEBUGFS 199bfcc09ddSBjoern A. Zeeb /** 200bfcc09ddSBjoern A. Zeeb * enum iwl_fw_mon_dbgfs_state - the different states of the monitor_data 201bfcc09ddSBjoern A. Zeeb * debugfs file 202bfcc09ddSBjoern A. Zeeb * 203bfcc09ddSBjoern A. Zeeb * @IWL_FW_MON_DBGFS_STATE_CLOSED: the file is closed. 204bfcc09ddSBjoern A. Zeeb * @IWL_FW_MON_DBGFS_STATE_OPEN: the file is open. 205bfcc09ddSBjoern A. Zeeb * @IWL_FW_MON_DBGFS_STATE_DISABLED: the file is disabled, once this state is 206bfcc09ddSBjoern A. Zeeb * set the file can no longer be used. 207bfcc09ddSBjoern A. Zeeb */ 208bfcc09ddSBjoern A. Zeeb enum iwl_fw_mon_dbgfs_state { 209bfcc09ddSBjoern A. Zeeb IWL_FW_MON_DBGFS_STATE_CLOSED, 210bfcc09ddSBjoern A. Zeeb IWL_FW_MON_DBGFS_STATE_OPEN, 211bfcc09ddSBjoern A. Zeeb IWL_FW_MON_DBGFS_STATE_DISABLED, 212bfcc09ddSBjoern A. Zeeb }; 213bfcc09ddSBjoern A. Zeeb #endif 214bfcc09ddSBjoern A. Zeeb 215bfcc09ddSBjoern A. Zeeb /** 216bfcc09ddSBjoern A. Zeeb * enum iwl_shared_irq_flags - level of sharing for irq 217bfcc09ddSBjoern A. Zeeb * @IWL_SHARED_IRQ_NON_RX: interrupt vector serves non rx causes. 218bfcc09ddSBjoern A. Zeeb * @IWL_SHARED_IRQ_FIRST_RSS: interrupt vector serves first RSS queue. 219bfcc09ddSBjoern A. Zeeb */ 220bfcc09ddSBjoern A. Zeeb enum iwl_shared_irq_flags { 221bfcc09ddSBjoern A. Zeeb IWL_SHARED_IRQ_NON_RX = BIT(0), 222bfcc09ddSBjoern A. Zeeb IWL_SHARED_IRQ_FIRST_RSS = BIT(1), 223bfcc09ddSBjoern A. Zeeb }; 224bfcc09ddSBjoern A. Zeeb 225bfcc09ddSBjoern A. Zeeb /** 226bfcc09ddSBjoern A. Zeeb * enum iwl_image_response_code - image response values 227bfcc09ddSBjoern A. Zeeb * @IWL_IMAGE_RESP_DEF: the default value of the register 228bfcc09ddSBjoern A. Zeeb * @IWL_IMAGE_RESP_SUCCESS: iml was read successfully 229bfcc09ddSBjoern A. Zeeb * @IWL_IMAGE_RESP_FAIL: iml reading failed 230bfcc09ddSBjoern A. Zeeb */ 231bfcc09ddSBjoern A. Zeeb enum iwl_image_response_code { 232bfcc09ddSBjoern A. Zeeb IWL_IMAGE_RESP_DEF = 0, 233bfcc09ddSBjoern A. Zeeb IWL_IMAGE_RESP_SUCCESS = 1, 234bfcc09ddSBjoern A. Zeeb IWL_IMAGE_RESP_FAIL = 2, 235bfcc09ddSBjoern A. Zeeb }; 236bfcc09ddSBjoern A. Zeeb 237bfcc09ddSBjoern A. Zeeb /** 238bfcc09ddSBjoern A. Zeeb * struct cont_rec: continuous recording data structure 239bfcc09ddSBjoern A. Zeeb * @prev_wr_ptr: the last address that was read in monitor_data 240bfcc09ddSBjoern A. Zeeb * debugfs file 241bfcc09ddSBjoern A. Zeeb * @prev_wrap_cnt: the wrap count that was used during the last read in 242bfcc09ddSBjoern A. Zeeb * monitor_data debugfs file 243bfcc09ddSBjoern A. Zeeb * @state: the state of monitor_data debugfs file as described 244bfcc09ddSBjoern A. Zeeb * in &iwl_fw_mon_dbgfs_state enum 245bfcc09ddSBjoern A. Zeeb * @mutex: locked while reading from monitor_data debugfs file 246bfcc09ddSBjoern A. Zeeb */ 247bfcc09ddSBjoern A. Zeeb #ifdef CONFIG_IWLWIFI_DEBUGFS 248bfcc09ddSBjoern A. Zeeb struct cont_rec { 249bfcc09ddSBjoern A. Zeeb u32 prev_wr_ptr; 250bfcc09ddSBjoern A. Zeeb u32 prev_wrap_cnt; 251bfcc09ddSBjoern A. Zeeb u8 state; 252bfcc09ddSBjoern A. Zeeb /* Used to sync monitor_data debugfs file with driver unload flow */ 253bfcc09ddSBjoern A. Zeeb struct mutex mutex; 254bfcc09ddSBjoern A. Zeeb }; 255bfcc09ddSBjoern A. Zeeb #endif 256bfcc09ddSBjoern A. Zeeb 257bfcc09ddSBjoern A. Zeeb enum iwl_pcie_fw_reset_state { 258bfcc09ddSBjoern A. Zeeb FW_RESET_IDLE, 259bfcc09ddSBjoern A. Zeeb FW_RESET_REQUESTED, 260bfcc09ddSBjoern A. Zeeb FW_RESET_OK, 261bfcc09ddSBjoern A. Zeeb FW_RESET_ERROR, 262bfcc09ddSBjoern A. Zeeb }; 263bfcc09ddSBjoern A. Zeeb 264bfcc09ddSBjoern A. Zeeb /** 265bfcc09ddSBjoern A. Zeeb * struct iwl_trans_pcie - PCIe transport specific data 266bfcc09ddSBjoern A. Zeeb * @rxq: all the RX queue data 267bfcc09ddSBjoern A. Zeeb * @rx_pool: initial pool of iwl_rx_mem_buffer for all the queues 268bfcc09ddSBjoern A. Zeeb * @global_table: table mapping received VID from hw to rxb 269bfcc09ddSBjoern A. Zeeb * @rba: allocator for RX replenishing 270bfcc09ddSBjoern A. Zeeb * @ctxt_info: context information for FW self init 271bfcc09ddSBjoern A. Zeeb * @ctxt_info_gen3: context information for gen3 devices 272bfcc09ddSBjoern A. Zeeb * @prph_info: prph info for self init 273bfcc09ddSBjoern A. Zeeb * @prph_scratch: prph scratch for self init 274bfcc09ddSBjoern A. Zeeb * @ctxt_info_dma_addr: dma addr of context information 275bfcc09ddSBjoern A. Zeeb * @prph_info_dma_addr: dma addr of prph info 276bfcc09ddSBjoern A. Zeeb * @prph_scratch_dma_addr: dma addr of prph scratch 277bfcc09ddSBjoern A. Zeeb * @ctxt_info_dma_addr: dma addr of context information 278bfcc09ddSBjoern A. Zeeb * @init_dram: DRAM data of firmware image (including paging). 279bfcc09ddSBjoern A. Zeeb * Context information addresses will be taken from here. 280bfcc09ddSBjoern A. Zeeb * This is driver's local copy for keeping track of size and 281bfcc09ddSBjoern A. Zeeb * count for allocating and freeing the memory. 282bfcc09ddSBjoern A. Zeeb * @iml: image loader image virtual address 283bfcc09ddSBjoern A. Zeeb * @iml_dma_addr: image loader image DMA address 284bfcc09ddSBjoern A. Zeeb * @trans: pointer to the generic transport area 285bfcc09ddSBjoern A. Zeeb * @scd_base_addr: scheduler sram base address in SRAM 286bfcc09ddSBjoern A. Zeeb * @kw: keep warm address 287bfcc09ddSBjoern A. Zeeb * @pnvm_dram: DRAM area that contains the PNVM data 288bfcc09ddSBjoern A. Zeeb * @pci_dev: basic pci-network driver stuff 289bfcc09ddSBjoern A. Zeeb * @hw_base: pci hardware address support 290bfcc09ddSBjoern A. Zeeb * @ucode_write_complete: indicates that the ucode has been copied. 291bfcc09ddSBjoern A. Zeeb * @ucode_write_waitq: wait queue for uCode load 292bfcc09ddSBjoern A. Zeeb * @cmd_queue - command queue number 293bfcc09ddSBjoern A. Zeeb * @def_rx_queue - default rx queue number 294bfcc09ddSBjoern A. Zeeb * @rx_buf_size: Rx buffer size 295bfcc09ddSBjoern A. Zeeb * @scd_set_active: should the transport configure the SCD for HCMD queue 296bfcc09ddSBjoern A. Zeeb * @rx_page_order: page order for receive buffer size 297bfcc09ddSBjoern A. Zeeb * @rx_buf_bytes: RX buffer (RB) size in bytes 298bfcc09ddSBjoern A. Zeeb * @reg_lock: protect hw register access 299bfcc09ddSBjoern A. Zeeb * @mutex: to protect stop_device / start_fw / start_hw 300bfcc09ddSBjoern A. Zeeb * @cmd_in_flight: true when we have a host command in flight 301bfcc09ddSBjoern A. Zeeb #ifdef CONFIG_IWLWIFI_DEBUGFS 302bfcc09ddSBjoern A. Zeeb * @fw_mon_data: fw continuous recording data 303bfcc09ddSBjoern A. Zeeb #endif 304bfcc09ddSBjoern A. Zeeb * @msix_entries: array of MSI-X entries 305bfcc09ddSBjoern A. Zeeb * @msix_enabled: true if managed to enable MSI-X 306bfcc09ddSBjoern A. Zeeb * @shared_vec_mask: the type of causes the shared vector handles 307bfcc09ddSBjoern A. Zeeb * (see iwl_shared_irq_flags). 308bfcc09ddSBjoern A. Zeeb * @alloc_vecs: the number of interrupt vectors allocated by the OS 309bfcc09ddSBjoern A. Zeeb * @def_irq: default irq for non rx causes 310bfcc09ddSBjoern A. Zeeb * @fh_init_mask: initial unmasked fh causes 311bfcc09ddSBjoern A. Zeeb * @hw_init_mask: initial unmasked hw causes 312bfcc09ddSBjoern A. Zeeb * @fh_mask: current unmasked fh causes 313bfcc09ddSBjoern A. Zeeb * @hw_mask: current unmasked hw causes 314bfcc09ddSBjoern A. Zeeb * @in_rescan: true if we have triggered a device rescan 315bfcc09ddSBjoern A. Zeeb * @base_rb_stts: base virtual address of receive buffer status for all queues 316bfcc09ddSBjoern A. Zeeb * @base_rb_stts_dma: base physical address of receive buffer status 317bfcc09ddSBjoern A. Zeeb * @supported_dma_mask: DMA mask to validate the actual address against, 318bfcc09ddSBjoern A. Zeeb * will be DMA_BIT_MASK(11) or DMA_BIT_MASK(12) depending on the device 319bfcc09ddSBjoern A. Zeeb * @alloc_page_lock: spinlock for the page allocator 320bfcc09ddSBjoern A. Zeeb * @alloc_page: allocated page to still use parts of 321bfcc09ddSBjoern A. Zeeb * @alloc_page_used: how much of the allocated page was already used (bytes) 322bfcc09ddSBjoern A. Zeeb * @rf_name: name/version of the CRF, if any 323bfcc09ddSBjoern A. Zeeb */ 324bfcc09ddSBjoern A. Zeeb struct iwl_trans_pcie { 325bfcc09ddSBjoern A. Zeeb struct iwl_rxq *rxq; 326bfcc09ddSBjoern A. Zeeb struct iwl_rx_mem_buffer *rx_pool; 327bfcc09ddSBjoern A. Zeeb struct iwl_rx_mem_buffer **global_table; 328bfcc09ddSBjoern A. Zeeb struct iwl_rb_allocator rba; 329bfcc09ddSBjoern A. Zeeb union { 330bfcc09ddSBjoern A. Zeeb struct iwl_context_info *ctxt_info; 331bfcc09ddSBjoern A. Zeeb struct iwl_context_info_gen3 *ctxt_info_gen3; 332bfcc09ddSBjoern A. Zeeb }; 333bfcc09ddSBjoern A. Zeeb struct iwl_prph_info *prph_info; 334bfcc09ddSBjoern A. Zeeb struct iwl_prph_scratch *prph_scratch; 335bfcc09ddSBjoern A. Zeeb void *iml; 336bfcc09ddSBjoern A. Zeeb dma_addr_t ctxt_info_dma_addr; 337bfcc09ddSBjoern A. Zeeb dma_addr_t prph_info_dma_addr; 338bfcc09ddSBjoern A. Zeeb dma_addr_t prph_scratch_dma_addr; 339bfcc09ddSBjoern A. Zeeb dma_addr_t iml_dma_addr; 340bfcc09ddSBjoern A. Zeeb struct iwl_trans *trans; 341bfcc09ddSBjoern A. Zeeb 342bfcc09ddSBjoern A. Zeeb struct net_device napi_dev; 343bfcc09ddSBjoern A. Zeeb 344bfcc09ddSBjoern A. Zeeb /* INT ICT Table */ 345bfcc09ddSBjoern A. Zeeb __le32 *ict_tbl; 346bfcc09ddSBjoern A. Zeeb dma_addr_t ict_tbl_dma; 347bfcc09ddSBjoern A. Zeeb int ict_index; 348bfcc09ddSBjoern A. Zeeb bool use_ict; 349bfcc09ddSBjoern A. Zeeb bool is_down, opmode_down; 350bfcc09ddSBjoern A. Zeeb s8 debug_rfkill; 351bfcc09ddSBjoern A. Zeeb struct isr_statistics isr_stats; 352bfcc09ddSBjoern A. Zeeb 353bfcc09ddSBjoern A. Zeeb spinlock_t irq_lock; 354bfcc09ddSBjoern A. Zeeb struct mutex mutex; 355bfcc09ddSBjoern A. Zeeb u32 inta_mask; 356bfcc09ddSBjoern A. Zeeb u32 scd_base_addr; 357bfcc09ddSBjoern A. Zeeb struct iwl_dma_ptr kw; 358bfcc09ddSBjoern A. Zeeb 359bfcc09ddSBjoern A. Zeeb struct iwl_dram_data pnvm_dram; 360bfcc09ddSBjoern A. Zeeb struct iwl_dram_data reduce_power_dram; 361bfcc09ddSBjoern A. Zeeb 362bfcc09ddSBjoern A. Zeeb struct iwl_txq *txq_memory; 363bfcc09ddSBjoern A. Zeeb 364bfcc09ddSBjoern A. Zeeb /* PCI bus related data */ 365bfcc09ddSBjoern A. Zeeb struct pci_dev *pci_dev; 366bfcc09ddSBjoern A. Zeeb void __iomem *hw_base; 367bfcc09ddSBjoern A. Zeeb 368bfcc09ddSBjoern A. Zeeb bool ucode_write_complete; 369bfcc09ddSBjoern A. Zeeb bool sx_complete; 370bfcc09ddSBjoern A. Zeeb wait_queue_head_t ucode_write_waitq; 371bfcc09ddSBjoern A. Zeeb wait_queue_head_t sx_waitq; 372bfcc09ddSBjoern A. Zeeb 373bfcc09ddSBjoern A. Zeeb u8 def_rx_queue; 374bfcc09ddSBjoern A. Zeeb u8 n_no_reclaim_cmds; 375bfcc09ddSBjoern A. Zeeb u8 no_reclaim_cmds[MAX_NO_RECLAIM_CMDS]; 376bfcc09ddSBjoern A. Zeeb u16 num_rx_bufs; 377bfcc09ddSBjoern A. Zeeb 378bfcc09ddSBjoern A. Zeeb enum iwl_amsdu_size rx_buf_size; 379bfcc09ddSBjoern A. Zeeb bool scd_set_active; 380bfcc09ddSBjoern A. Zeeb bool pcie_dbg_dumped_once; 381bfcc09ddSBjoern A. Zeeb u32 rx_page_order; 382bfcc09ddSBjoern A. Zeeb u32 rx_buf_bytes; 383bfcc09ddSBjoern A. Zeeb u32 supported_dma_mask; 384bfcc09ddSBjoern A. Zeeb 385bfcc09ddSBjoern A. Zeeb /* allocator lock for the two values below */ 386bfcc09ddSBjoern A. Zeeb spinlock_t alloc_page_lock; 387bfcc09ddSBjoern A. Zeeb struct page *alloc_page; 388bfcc09ddSBjoern A. Zeeb u32 alloc_page_used; 389bfcc09ddSBjoern A. Zeeb 390bfcc09ddSBjoern A. Zeeb /*protect hw register */ 391bfcc09ddSBjoern A. Zeeb spinlock_t reg_lock; 392bfcc09ddSBjoern A. Zeeb bool cmd_hold_nic_awake; 393bfcc09ddSBjoern A. Zeeb 394bfcc09ddSBjoern A. Zeeb #ifdef CONFIG_IWLWIFI_DEBUGFS 395bfcc09ddSBjoern A. Zeeb struct cont_rec fw_mon_data; 396bfcc09ddSBjoern A. Zeeb #endif 397bfcc09ddSBjoern A. Zeeb 398bfcc09ddSBjoern A. Zeeb struct msix_entry msix_entries[IWL_MAX_RX_HW_QUEUES]; 399bfcc09ddSBjoern A. Zeeb bool msix_enabled; 400bfcc09ddSBjoern A. Zeeb u8 shared_vec_mask; 401bfcc09ddSBjoern A. Zeeb u32 alloc_vecs; 402bfcc09ddSBjoern A. Zeeb u32 def_irq; 403bfcc09ddSBjoern A. Zeeb u32 fh_init_mask; 404bfcc09ddSBjoern A. Zeeb u32 hw_init_mask; 405bfcc09ddSBjoern A. Zeeb u32 fh_mask; 406bfcc09ddSBjoern A. Zeeb u32 hw_mask; 407bfcc09ddSBjoern A. Zeeb cpumask_t affinity_mask[IWL_MAX_RX_HW_QUEUES]; 408bfcc09ddSBjoern A. Zeeb u16 tx_cmd_queue_size; 409bfcc09ddSBjoern A. Zeeb bool in_rescan; 410bfcc09ddSBjoern A. Zeeb 411bfcc09ddSBjoern A. Zeeb void *base_rb_stts; 412bfcc09ddSBjoern A. Zeeb dma_addr_t base_rb_stts_dma; 413bfcc09ddSBjoern A. Zeeb 414bfcc09ddSBjoern A. Zeeb bool fw_reset_handshake; 415bfcc09ddSBjoern A. Zeeb enum iwl_pcie_fw_reset_state fw_reset_state; 416bfcc09ddSBjoern A. Zeeb wait_queue_head_t fw_reset_waitq; 417bfcc09ddSBjoern A. Zeeb 418bfcc09ddSBjoern A. Zeeb char rf_name[32]; 419bfcc09ddSBjoern A. Zeeb }; 420bfcc09ddSBjoern A. Zeeb 421bfcc09ddSBjoern A. Zeeb static inline struct iwl_trans_pcie * 422bfcc09ddSBjoern A. Zeeb IWL_TRANS_GET_PCIE_TRANS(struct iwl_trans *trans) 423bfcc09ddSBjoern A. Zeeb { 424bfcc09ddSBjoern A. Zeeb return (void *)trans->trans_specific; 425bfcc09ddSBjoern A. Zeeb } 426bfcc09ddSBjoern A. Zeeb 427bfcc09ddSBjoern A. Zeeb static inline void iwl_pcie_clear_irq(struct iwl_trans *trans, int queue) 428bfcc09ddSBjoern A. Zeeb { 429bfcc09ddSBjoern A. Zeeb /* 430bfcc09ddSBjoern A. Zeeb * Before sending the interrupt the HW disables it to prevent 431bfcc09ddSBjoern A. Zeeb * a nested interrupt. This is done by writing 1 to the corresponding 432bfcc09ddSBjoern A. Zeeb * bit in the mask register. After handling the interrupt, it should be 433bfcc09ddSBjoern A. Zeeb * re-enabled by clearing this bit. This register is defined as 434bfcc09ddSBjoern A. Zeeb * write 1 clear (W1C) register, meaning that it's being clear 435bfcc09ddSBjoern A. Zeeb * by writing 1 to the bit. 436bfcc09ddSBjoern A. Zeeb */ 437bfcc09ddSBjoern A. Zeeb iwl_write32(trans, CSR_MSIX_AUTOMASK_ST_AD, BIT(queue)); 438bfcc09ddSBjoern A. Zeeb } 439bfcc09ddSBjoern A. Zeeb 440bfcc09ddSBjoern A. Zeeb static inline struct iwl_trans * 441bfcc09ddSBjoern A. Zeeb iwl_trans_pcie_get_trans(struct iwl_trans_pcie *trans_pcie) 442bfcc09ddSBjoern A. Zeeb { 443bfcc09ddSBjoern A. Zeeb return container_of((void *)trans_pcie, struct iwl_trans, 444bfcc09ddSBjoern A. Zeeb trans_specific); 445bfcc09ddSBjoern A. Zeeb } 446bfcc09ddSBjoern A. Zeeb 447bfcc09ddSBjoern A. Zeeb /* 448bfcc09ddSBjoern A. Zeeb * Convention: trans API functions: iwl_trans_pcie_XXX 449bfcc09ddSBjoern A. Zeeb * Other functions: iwl_pcie_XXX 450bfcc09ddSBjoern A. Zeeb */ 451bfcc09ddSBjoern A. Zeeb struct iwl_trans 452bfcc09ddSBjoern A. Zeeb *iwl_trans_pcie_alloc(struct pci_dev *pdev, 453bfcc09ddSBjoern A. Zeeb const struct pci_device_id *ent, 454bfcc09ddSBjoern A. Zeeb const struct iwl_cfg_trans_params *cfg_trans); 455bfcc09ddSBjoern A. Zeeb void iwl_trans_pcie_free(struct iwl_trans *trans); 456bfcc09ddSBjoern A. Zeeb 457bfcc09ddSBjoern A. Zeeb bool __iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans); 458bfcc09ddSBjoern A. Zeeb #define _iwl_trans_pcie_grab_nic_access(trans) \ 459bfcc09ddSBjoern A. Zeeb __cond_lock(nic_access_nobh, \ 460bfcc09ddSBjoern A. Zeeb likely(__iwl_trans_pcie_grab_nic_access(trans))) 461bfcc09ddSBjoern A. Zeeb 462bfcc09ddSBjoern A. Zeeb /***************************************************** 463bfcc09ddSBjoern A. Zeeb * RX 464bfcc09ddSBjoern A. Zeeb ******************************************************/ 465bfcc09ddSBjoern A. Zeeb int iwl_pcie_rx_init(struct iwl_trans *trans); 466bfcc09ddSBjoern A. Zeeb int iwl_pcie_gen2_rx_init(struct iwl_trans *trans); 467bfcc09ddSBjoern A. Zeeb irqreturn_t iwl_pcie_msix_isr(int irq, void *data); 468bfcc09ddSBjoern A. Zeeb irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id); 469bfcc09ddSBjoern A. Zeeb irqreturn_t iwl_pcie_irq_msix_handler(int irq, void *dev_id); 470bfcc09ddSBjoern A. Zeeb irqreturn_t iwl_pcie_irq_rx_msix_handler(int irq, void *dev_id); 471bfcc09ddSBjoern A. Zeeb int iwl_pcie_rx_stop(struct iwl_trans *trans); 472bfcc09ddSBjoern A. Zeeb void iwl_pcie_rx_free(struct iwl_trans *trans); 473bfcc09ddSBjoern A. Zeeb void iwl_pcie_free_rbs_pool(struct iwl_trans *trans); 474bfcc09ddSBjoern A. Zeeb void iwl_pcie_rx_init_rxb_lists(struct iwl_rxq *rxq); 475bfcc09ddSBjoern A. Zeeb void iwl_pcie_rxq_alloc_rbs(struct iwl_trans *trans, gfp_t priority, 476bfcc09ddSBjoern A. Zeeb struct iwl_rxq *rxq); 477bfcc09ddSBjoern A. Zeeb 478bfcc09ddSBjoern A. Zeeb /***************************************************** 479bfcc09ddSBjoern A. Zeeb * ICT - interrupt handling 480bfcc09ddSBjoern A. Zeeb ******************************************************/ 481bfcc09ddSBjoern A. Zeeb irqreturn_t iwl_pcie_isr(int irq, void *data); 482bfcc09ddSBjoern A. Zeeb int iwl_pcie_alloc_ict(struct iwl_trans *trans); 483bfcc09ddSBjoern A. Zeeb void iwl_pcie_free_ict(struct iwl_trans *trans); 484bfcc09ddSBjoern A. Zeeb void iwl_pcie_reset_ict(struct iwl_trans *trans); 485bfcc09ddSBjoern A. Zeeb void iwl_pcie_disable_ict(struct iwl_trans *trans); 486bfcc09ddSBjoern A. Zeeb 487bfcc09ddSBjoern A. Zeeb /***************************************************** 488bfcc09ddSBjoern A. Zeeb * TX / HCMD 489bfcc09ddSBjoern A. Zeeb ******************************************************/ 490bfcc09ddSBjoern A. Zeeb int iwl_pcie_tx_init(struct iwl_trans *trans); 491bfcc09ddSBjoern A. Zeeb void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr); 492bfcc09ddSBjoern A. Zeeb int iwl_pcie_tx_stop(struct iwl_trans *trans); 493bfcc09ddSBjoern A. Zeeb void iwl_pcie_tx_free(struct iwl_trans *trans); 494bfcc09ddSBjoern A. Zeeb bool iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int queue, u16 ssn, 495bfcc09ddSBjoern A. Zeeb const struct iwl_trans_txq_scd_cfg *cfg, 496bfcc09ddSBjoern A. Zeeb unsigned int wdg_timeout); 497bfcc09ddSBjoern A. Zeeb void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int queue, 498bfcc09ddSBjoern A. Zeeb bool configure_scd); 499bfcc09ddSBjoern A. Zeeb void iwl_trans_pcie_txq_set_shared_mode(struct iwl_trans *trans, u32 txq_id, 500bfcc09ddSBjoern A. Zeeb bool shared_mode); 501bfcc09ddSBjoern A. Zeeb int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb, 502bfcc09ddSBjoern A. Zeeb struct iwl_device_tx_cmd *dev_cmd, int txq_id); 503bfcc09ddSBjoern A. Zeeb void iwl_pcie_txq_check_wrptrs(struct iwl_trans *trans); 504bfcc09ddSBjoern A. Zeeb int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd); 505bfcc09ddSBjoern A. Zeeb void iwl_pcie_hcmd_complete(struct iwl_trans *trans, 506bfcc09ddSBjoern A. Zeeb struct iwl_rx_cmd_buffer *rxb); 507bfcc09ddSBjoern A. Zeeb void iwl_trans_pcie_tx_reset(struct iwl_trans *trans); 508bfcc09ddSBjoern A. Zeeb 509bfcc09ddSBjoern A. Zeeb /***************************************************** 510bfcc09ddSBjoern A. Zeeb * Error handling 511bfcc09ddSBjoern A. Zeeb ******************************************************/ 512bfcc09ddSBjoern A. Zeeb void iwl_pcie_dump_csr(struct iwl_trans *trans); 513bfcc09ddSBjoern A. Zeeb 514bfcc09ddSBjoern A. Zeeb /***************************************************** 515bfcc09ddSBjoern A. Zeeb * Helpers 516bfcc09ddSBjoern A. Zeeb ******************************************************/ 517bfcc09ddSBjoern A. Zeeb static inline void _iwl_disable_interrupts(struct iwl_trans *trans) 518bfcc09ddSBjoern A. Zeeb { 519bfcc09ddSBjoern A. Zeeb struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 520bfcc09ddSBjoern A. Zeeb 521bfcc09ddSBjoern A. Zeeb clear_bit(STATUS_INT_ENABLED, &trans->status); 522bfcc09ddSBjoern A. Zeeb if (!trans_pcie->msix_enabled) { 523bfcc09ddSBjoern A. Zeeb /* disable interrupts from uCode/NIC to host */ 524bfcc09ddSBjoern A. Zeeb iwl_write32(trans, CSR_INT_MASK, 0x00000000); 525bfcc09ddSBjoern A. Zeeb 526bfcc09ddSBjoern A. Zeeb /* acknowledge/clear/reset any interrupts still pending 527bfcc09ddSBjoern A. Zeeb * from uCode or flow handler (Rx/Tx DMA) */ 528bfcc09ddSBjoern A. Zeeb iwl_write32(trans, CSR_INT, 0xffffffff); 529bfcc09ddSBjoern A. Zeeb iwl_write32(trans, CSR_FH_INT_STATUS, 0xffffffff); 530bfcc09ddSBjoern A. Zeeb } else { 531bfcc09ddSBjoern A. Zeeb /* disable all the interrupt we might use */ 532bfcc09ddSBjoern A. Zeeb iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, 533bfcc09ddSBjoern A. Zeeb trans_pcie->fh_init_mask); 534bfcc09ddSBjoern A. Zeeb iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD, 535bfcc09ddSBjoern A. Zeeb trans_pcie->hw_init_mask); 536bfcc09ddSBjoern A. Zeeb } 537bfcc09ddSBjoern A. Zeeb IWL_DEBUG_ISR(trans, "Disabled interrupts\n"); 538bfcc09ddSBjoern A. Zeeb } 539bfcc09ddSBjoern A. Zeeb 540bfcc09ddSBjoern A. Zeeb static inline int iwl_pcie_get_num_sections(const struct fw_img *fw, 541bfcc09ddSBjoern A. Zeeb int start) 542bfcc09ddSBjoern A. Zeeb { 543bfcc09ddSBjoern A. Zeeb int i = 0; 544bfcc09ddSBjoern A. Zeeb 545bfcc09ddSBjoern A. Zeeb while (start < fw->num_sec && 546bfcc09ddSBjoern A. Zeeb fw->sec[start].offset != CPU1_CPU2_SEPARATOR_SECTION && 547bfcc09ddSBjoern A. Zeeb fw->sec[start].offset != PAGING_SEPARATOR_SECTION) { 548bfcc09ddSBjoern A. Zeeb start++; 549bfcc09ddSBjoern A. Zeeb i++; 550bfcc09ddSBjoern A. Zeeb } 551bfcc09ddSBjoern A. Zeeb 552bfcc09ddSBjoern A. Zeeb return i; 553bfcc09ddSBjoern A. Zeeb } 554bfcc09ddSBjoern A. Zeeb 555bfcc09ddSBjoern A. Zeeb static inline void iwl_pcie_ctxt_info_free_fw_img(struct iwl_trans *trans) 556bfcc09ddSBjoern A. Zeeb { 557bfcc09ddSBjoern A. Zeeb struct iwl_self_init_dram *dram = &trans->init_dram; 558bfcc09ddSBjoern A. Zeeb int i; 559bfcc09ddSBjoern A. Zeeb 560bfcc09ddSBjoern A. Zeeb if (!dram->fw) { 561bfcc09ddSBjoern A. Zeeb WARN_ON(dram->fw_cnt); 562bfcc09ddSBjoern A. Zeeb return; 563bfcc09ddSBjoern A. Zeeb } 564bfcc09ddSBjoern A. Zeeb 565bfcc09ddSBjoern A. Zeeb for (i = 0; i < dram->fw_cnt; i++) 566bfcc09ddSBjoern A. Zeeb dma_free_coherent(trans->dev, dram->fw[i].size, 567bfcc09ddSBjoern A. Zeeb dram->fw[i].block, dram->fw[i].physical); 568bfcc09ddSBjoern A. Zeeb 569bfcc09ddSBjoern A. Zeeb kfree(dram->fw); 570bfcc09ddSBjoern A. Zeeb dram->fw_cnt = 0; 571bfcc09ddSBjoern A. Zeeb dram->fw = NULL; 572bfcc09ddSBjoern A. Zeeb } 573bfcc09ddSBjoern A. Zeeb 574bfcc09ddSBjoern A. Zeeb static inline void iwl_disable_interrupts(struct iwl_trans *trans) 575bfcc09ddSBjoern A. Zeeb { 576bfcc09ddSBjoern A. Zeeb struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 577bfcc09ddSBjoern A. Zeeb 578bfcc09ddSBjoern A. Zeeb spin_lock_bh(&trans_pcie->irq_lock); 579bfcc09ddSBjoern A. Zeeb _iwl_disable_interrupts(trans); 580bfcc09ddSBjoern A. Zeeb spin_unlock_bh(&trans_pcie->irq_lock); 581bfcc09ddSBjoern A. Zeeb } 582bfcc09ddSBjoern A. Zeeb 583bfcc09ddSBjoern A. Zeeb static inline void _iwl_enable_interrupts(struct iwl_trans *trans) 584bfcc09ddSBjoern A. Zeeb { 585bfcc09ddSBjoern A. Zeeb struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 586bfcc09ddSBjoern A. Zeeb 587bfcc09ddSBjoern A. Zeeb IWL_DEBUG_ISR(trans, "Enabling interrupts\n"); 588bfcc09ddSBjoern A. Zeeb set_bit(STATUS_INT_ENABLED, &trans->status); 589bfcc09ddSBjoern A. Zeeb if (!trans_pcie->msix_enabled) { 590bfcc09ddSBjoern A. Zeeb trans_pcie->inta_mask = CSR_INI_SET_MASK; 591bfcc09ddSBjoern A. Zeeb iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask); 592bfcc09ddSBjoern A. Zeeb } else { 593bfcc09ddSBjoern A. Zeeb /* 594bfcc09ddSBjoern A. Zeeb * fh/hw_mask keeps all the unmasked causes. 595bfcc09ddSBjoern A. Zeeb * Unlike msi, in msix cause is enabled when it is unset. 596bfcc09ddSBjoern A. Zeeb */ 597bfcc09ddSBjoern A. Zeeb trans_pcie->hw_mask = trans_pcie->hw_init_mask; 598bfcc09ddSBjoern A. Zeeb trans_pcie->fh_mask = trans_pcie->fh_init_mask; 599bfcc09ddSBjoern A. Zeeb iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, 600bfcc09ddSBjoern A. Zeeb ~trans_pcie->fh_mask); 601bfcc09ddSBjoern A. Zeeb iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD, 602bfcc09ddSBjoern A. Zeeb ~trans_pcie->hw_mask); 603bfcc09ddSBjoern A. Zeeb } 604bfcc09ddSBjoern A. Zeeb } 605bfcc09ddSBjoern A. Zeeb 606bfcc09ddSBjoern A. Zeeb static inline void iwl_enable_interrupts(struct iwl_trans *trans) 607bfcc09ddSBjoern A. Zeeb { 608bfcc09ddSBjoern A. Zeeb struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 609bfcc09ddSBjoern A. Zeeb 610bfcc09ddSBjoern A. Zeeb spin_lock_bh(&trans_pcie->irq_lock); 611bfcc09ddSBjoern A. Zeeb _iwl_enable_interrupts(trans); 612bfcc09ddSBjoern A. Zeeb spin_unlock_bh(&trans_pcie->irq_lock); 613bfcc09ddSBjoern A. Zeeb } 614bfcc09ddSBjoern A. Zeeb static inline void iwl_enable_hw_int_msk_msix(struct iwl_trans *trans, u32 msk) 615bfcc09ddSBjoern A. Zeeb { 616bfcc09ddSBjoern A. Zeeb struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 617bfcc09ddSBjoern A. Zeeb 618bfcc09ddSBjoern A. Zeeb iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD, ~msk); 619bfcc09ddSBjoern A. Zeeb trans_pcie->hw_mask = msk; 620bfcc09ddSBjoern A. Zeeb } 621bfcc09ddSBjoern A. Zeeb 622bfcc09ddSBjoern A. Zeeb static inline void iwl_enable_fh_int_msk_msix(struct iwl_trans *trans, u32 msk) 623bfcc09ddSBjoern A. Zeeb { 624bfcc09ddSBjoern A. Zeeb struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 625bfcc09ddSBjoern A. Zeeb 626bfcc09ddSBjoern A. Zeeb iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~msk); 627bfcc09ddSBjoern A. Zeeb trans_pcie->fh_mask = msk; 628bfcc09ddSBjoern A. Zeeb } 629bfcc09ddSBjoern A. Zeeb 630bfcc09ddSBjoern A. Zeeb static inline void iwl_enable_fw_load_int(struct iwl_trans *trans) 631bfcc09ddSBjoern A. Zeeb { 632bfcc09ddSBjoern A. Zeeb struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 633bfcc09ddSBjoern A. Zeeb 634bfcc09ddSBjoern A. Zeeb IWL_DEBUG_ISR(trans, "Enabling FW load interrupt\n"); 635bfcc09ddSBjoern A. Zeeb if (!trans_pcie->msix_enabled) { 636bfcc09ddSBjoern A. Zeeb trans_pcie->inta_mask = CSR_INT_BIT_FH_TX; 637bfcc09ddSBjoern A. Zeeb iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask); 638bfcc09ddSBjoern A. Zeeb } else { 639bfcc09ddSBjoern A. Zeeb iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD, 640bfcc09ddSBjoern A. Zeeb trans_pcie->hw_init_mask); 641bfcc09ddSBjoern A. Zeeb iwl_enable_fh_int_msk_msix(trans, 642bfcc09ddSBjoern A. Zeeb MSIX_FH_INT_CAUSES_D2S_CH0_NUM); 643bfcc09ddSBjoern A. Zeeb } 644bfcc09ddSBjoern A. Zeeb } 645bfcc09ddSBjoern A. Zeeb 646bfcc09ddSBjoern A. Zeeb static inline void iwl_enable_fw_load_int_ctx_info(struct iwl_trans *trans) 647bfcc09ddSBjoern A. Zeeb { 648bfcc09ddSBjoern A. Zeeb struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 649bfcc09ddSBjoern A. Zeeb 650bfcc09ddSBjoern A. Zeeb IWL_DEBUG_ISR(trans, "Enabling ALIVE interrupt only\n"); 651bfcc09ddSBjoern A. Zeeb 652bfcc09ddSBjoern A. Zeeb if (!trans_pcie->msix_enabled) { 653bfcc09ddSBjoern A. Zeeb /* 654bfcc09ddSBjoern A. Zeeb * When we'll receive the ALIVE interrupt, the ISR will call 655bfcc09ddSBjoern A. Zeeb * iwl_enable_fw_load_int_ctx_info again to set the ALIVE 656bfcc09ddSBjoern A. Zeeb * interrupt (which is not really needed anymore) but also the 657bfcc09ddSBjoern A. Zeeb * RX interrupt which will allow us to receive the ALIVE 658bfcc09ddSBjoern A. Zeeb * notification (which is Rx) and continue the flow. 659bfcc09ddSBjoern A. Zeeb */ 660bfcc09ddSBjoern A. Zeeb trans_pcie->inta_mask = CSR_INT_BIT_ALIVE | CSR_INT_BIT_FH_RX; 661bfcc09ddSBjoern A. Zeeb iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask); 662bfcc09ddSBjoern A. Zeeb } else { 663bfcc09ddSBjoern A. Zeeb iwl_enable_hw_int_msk_msix(trans, 664bfcc09ddSBjoern A. Zeeb MSIX_HW_INT_CAUSES_REG_ALIVE); 665bfcc09ddSBjoern A. Zeeb /* 666bfcc09ddSBjoern A. Zeeb * Leave all the FH causes enabled to get the ALIVE 667bfcc09ddSBjoern A. Zeeb * notification. 668bfcc09ddSBjoern A. Zeeb */ 669bfcc09ddSBjoern A. Zeeb iwl_enable_fh_int_msk_msix(trans, trans_pcie->fh_init_mask); 670bfcc09ddSBjoern A. Zeeb } 671bfcc09ddSBjoern A. Zeeb } 672bfcc09ddSBjoern A. Zeeb 673bfcc09ddSBjoern A. Zeeb static inline const char *queue_name(struct device *dev, 674bfcc09ddSBjoern A. Zeeb struct iwl_trans_pcie *trans_p, int i) 675bfcc09ddSBjoern A. Zeeb { 676bfcc09ddSBjoern A. Zeeb if (trans_p->shared_vec_mask) { 677bfcc09ddSBjoern A. Zeeb int vec = trans_p->shared_vec_mask & 678bfcc09ddSBjoern A. Zeeb IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0; 679bfcc09ddSBjoern A. Zeeb 680bfcc09ddSBjoern A. Zeeb if (i == 0) 681bfcc09ddSBjoern A. Zeeb return DRV_NAME ":shared_IRQ"; 682bfcc09ddSBjoern A. Zeeb 683bfcc09ddSBjoern A. Zeeb return devm_kasprintf(dev, GFP_KERNEL, 684bfcc09ddSBjoern A. Zeeb DRV_NAME ":queue_%d", i + vec); 685bfcc09ddSBjoern A. Zeeb } 686bfcc09ddSBjoern A. Zeeb if (i == 0) 687bfcc09ddSBjoern A. Zeeb return DRV_NAME ":default_queue"; 688bfcc09ddSBjoern A. Zeeb 689bfcc09ddSBjoern A. Zeeb if (i == trans_p->alloc_vecs - 1) 690bfcc09ddSBjoern A. Zeeb return DRV_NAME ":exception"; 691bfcc09ddSBjoern A. Zeeb 692bfcc09ddSBjoern A. Zeeb return devm_kasprintf(dev, GFP_KERNEL, 693bfcc09ddSBjoern A. Zeeb DRV_NAME ":queue_%d", i); 694bfcc09ddSBjoern A. Zeeb } 695bfcc09ddSBjoern A. Zeeb 696bfcc09ddSBjoern A. Zeeb static inline void iwl_enable_rfkill_int(struct iwl_trans *trans) 697bfcc09ddSBjoern A. Zeeb { 698bfcc09ddSBjoern A. Zeeb struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 699bfcc09ddSBjoern A. Zeeb 700bfcc09ddSBjoern A. Zeeb IWL_DEBUG_ISR(trans, "Enabling rfkill interrupt\n"); 701bfcc09ddSBjoern A. Zeeb if (!trans_pcie->msix_enabled) { 702bfcc09ddSBjoern A. Zeeb trans_pcie->inta_mask = CSR_INT_BIT_RF_KILL; 703bfcc09ddSBjoern A. Zeeb iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask); 704bfcc09ddSBjoern A. Zeeb } else { 705bfcc09ddSBjoern A. Zeeb iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, 706bfcc09ddSBjoern A. Zeeb trans_pcie->fh_init_mask); 707bfcc09ddSBjoern A. Zeeb iwl_enable_hw_int_msk_msix(trans, 708bfcc09ddSBjoern A. Zeeb MSIX_HW_INT_CAUSES_REG_RF_KILL); 709bfcc09ddSBjoern A. Zeeb } 710bfcc09ddSBjoern A. Zeeb 711bfcc09ddSBjoern A. Zeeb if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_9000) { 712bfcc09ddSBjoern A. Zeeb /* 713bfcc09ddSBjoern A. Zeeb * On 9000-series devices this bit isn't enabled by default, so 714bfcc09ddSBjoern A. Zeeb * when we power down the device we need set the bit to allow it 715bfcc09ddSBjoern A. Zeeb * to wake up the PCI-E bus for RF-kill interrupts. 716bfcc09ddSBjoern A. Zeeb */ 717bfcc09ddSBjoern A. Zeeb iwl_set_bit(trans, CSR_GP_CNTRL, 718bfcc09ddSBjoern A. Zeeb CSR_GP_CNTRL_REG_FLAG_RFKILL_WAKE_L1A_EN); 719bfcc09ddSBjoern A. Zeeb } 720bfcc09ddSBjoern A. Zeeb } 721bfcc09ddSBjoern A. Zeeb 722bfcc09ddSBjoern A. Zeeb void iwl_pcie_handle_rfkill_irq(struct iwl_trans *trans); 723bfcc09ddSBjoern A. Zeeb 724bfcc09ddSBjoern A. Zeeb static inline bool iwl_is_rfkill_set(struct iwl_trans *trans) 725bfcc09ddSBjoern A. Zeeb { 726bfcc09ddSBjoern A. Zeeb struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 727bfcc09ddSBjoern A. Zeeb 728bfcc09ddSBjoern A. Zeeb lockdep_assert_held(&trans_pcie->mutex); 729bfcc09ddSBjoern A. Zeeb 730bfcc09ddSBjoern A. Zeeb if (trans_pcie->debug_rfkill == 1) 731bfcc09ddSBjoern A. Zeeb return true; 732bfcc09ddSBjoern A. Zeeb 733bfcc09ddSBjoern A. Zeeb return !(iwl_read32(trans, CSR_GP_CNTRL) & 734bfcc09ddSBjoern A. Zeeb CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW); 735bfcc09ddSBjoern A. Zeeb } 736bfcc09ddSBjoern A. Zeeb 737bfcc09ddSBjoern A. Zeeb static inline void __iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, 738bfcc09ddSBjoern A. Zeeb u32 reg, u32 mask, u32 value) 739bfcc09ddSBjoern A. Zeeb { 740bfcc09ddSBjoern A. Zeeb u32 v; 741bfcc09ddSBjoern A. Zeeb 742bfcc09ddSBjoern A. Zeeb #ifdef CONFIG_IWLWIFI_DEBUG 743bfcc09ddSBjoern A. Zeeb WARN_ON_ONCE(value & ~mask); 744bfcc09ddSBjoern A. Zeeb #endif 745bfcc09ddSBjoern A. Zeeb 746bfcc09ddSBjoern A. Zeeb v = iwl_read32(trans, reg); 747bfcc09ddSBjoern A. Zeeb v &= ~mask; 748bfcc09ddSBjoern A. Zeeb v |= value; 749bfcc09ddSBjoern A. Zeeb iwl_write32(trans, reg, v); 750bfcc09ddSBjoern A. Zeeb } 751bfcc09ddSBjoern A. Zeeb 752bfcc09ddSBjoern A. Zeeb static inline void __iwl_trans_pcie_clear_bit(struct iwl_trans *trans, 753bfcc09ddSBjoern A. Zeeb u32 reg, u32 mask) 754bfcc09ddSBjoern A. Zeeb { 755bfcc09ddSBjoern A. Zeeb __iwl_trans_pcie_set_bits_mask(trans, reg, mask, 0); 756bfcc09ddSBjoern A. Zeeb } 757bfcc09ddSBjoern A. Zeeb 758bfcc09ddSBjoern A. Zeeb static inline void __iwl_trans_pcie_set_bit(struct iwl_trans *trans, 759bfcc09ddSBjoern A. Zeeb u32 reg, u32 mask) 760bfcc09ddSBjoern A. Zeeb { 761bfcc09ddSBjoern A. Zeeb __iwl_trans_pcie_set_bits_mask(trans, reg, mask, mask); 762bfcc09ddSBjoern A. Zeeb } 763bfcc09ddSBjoern A. Zeeb 764bfcc09ddSBjoern A. Zeeb static inline bool iwl_pcie_dbg_on(struct iwl_trans *trans) 765bfcc09ddSBjoern A. Zeeb { 766bfcc09ddSBjoern A. Zeeb return (trans->dbg.dest_tlv || iwl_trans_dbg_ini_valid(trans)); 767bfcc09ddSBjoern A. Zeeb } 768bfcc09ddSBjoern A. Zeeb 769bfcc09ddSBjoern A. Zeeb void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state); 770bfcc09ddSBjoern A. Zeeb void iwl_trans_pcie_dump_regs(struct iwl_trans *trans); 771bfcc09ddSBjoern A. Zeeb 772bfcc09ddSBjoern A. Zeeb #ifdef CONFIG_IWLWIFI_DEBUGFS 773bfcc09ddSBjoern A. Zeeb void iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans); 774bfcc09ddSBjoern A. Zeeb #else 775bfcc09ddSBjoern A. Zeeb static inline void iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans) { } 776bfcc09ddSBjoern A. Zeeb #endif 777bfcc09ddSBjoern A. Zeeb 778bfcc09ddSBjoern A. Zeeb void iwl_pcie_rx_allocator_work(struct work_struct *data); 779bfcc09ddSBjoern A. Zeeb 780bfcc09ddSBjoern A. Zeeb /* common functions that are used by gen2 transport */ 781bfcc09ddSBjoern A. Zeeb int iwl_pcie_gen2_apm_init(struct iwl_trans *trans); 782bfcc09ddSBjoern A. Zeeb void iwl_pcie_apm_config(struct iwl_trans *trans); 783bfcc09ddSBjoern A. Zeeb int iwl_pcie_prepare_card_hw(struct iwl_trans *trans); 784bfcc09ddSBjoern A. Zeeb void iwl_pcie_synchronize_irqs(struct iwl_trans *trans); 785bfcc09ddSBjoern A. Zeeb bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans); 786bfcc09ddSBjoern A. Zeeb void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans, 787bfcc09ddSBjoern A. Zeeb bool was_in_rfkill); 788bfcc09ddSBjoern A. Zeeb void iwl_pcie_apm_stop_master(struct iwl_trans *trans); 789bfcc09ddSBjoern A. Zeeb void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie); 790bfcc09ddSBjoern A. Zeeb int iwl_pcie_alloc_dma_ptr(struct iwl_trans *trans, 791bfcc09ddSBjoern A. Zeeb struct iwl_dma_ptr *ptr, size_t size); 792bfcc09ddSBjoern A. Zeeb void iwl_pcie_free_dma_ptr(struct iwl_trans *trans, struct iwl_dma_ptr *ptr); 793bfcc09ddSBjoern A. Zeeb void iwl_pcie_apply_destination(struct iwl_trans *trans); 794bfcc09ddSBjoern A. Zeeb 795bfcc09ddSBjoern A. Zeeb /* common functions that are used by gen3 transport */ 796bfcc09ddSBjoern A. Zeeb void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power); 797bfcc09ddSBjoern A. Zeeb 798bfcc09ddSBjoern A. Zeeb /* transport gen 2 exported functions */ 799bfcc09ddSBjoern A. Zeeb int iwl_trans_pcie_gen2_start_fw(struct iwl_trans *trans, 800bfcc09ddSBjoern A. Zeeb const struct fw_img *fw, bool run_in_rfkill); 801bfcc09ddSBjoern A. Zeeb void iwl_trans_pcie_gen2_fw_alive(struct iwl_trans *trans, u32 scd_addr); 802bfcc09ddSBjoern A. Zeeb int iwl_trans_pcie_gen2_send_hcmd(struct iwl_trans *trans, 803bfcc09ddSBjoern A. Zeeb struct iwl_host_cmd *cmd); 804bfcc09ddSBjoern A. Zeeb void iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans); 805bfcc09ddSBjoern A. Zeeb void _iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans); 806bfcc09ddSBjoern A. Zeeb void iwl_pcie_d3_complete_suspend(struct iwl_trans *trans, 807bfcc09ddSBjoern A. Zeeb bool test, bool reset); 808bfcc09ddSBjoern A. Zeeb int iwl_pcie_gen2_enqueue_hcmd(struct iwl_trans *trans, 809bfcc09ddSBjoern A. Zeeb struct iwl_host_cmd *cmd); 810bfcc09ddSBjoern A. Zeeb int iwl_pcie_enqueue_hcmd(struct iwl_trans *trans, 811bfcc09ddSBjoern A. Zeeb struct iwl_host_cmd *cmd); 812bfcc09ddSBjoern A. Zeeb #endif /* __iwl_trans_int_pcie_h__ */ 813