16c92544dSBjoern A. Zeeb /* SPDX-License-Identifier: ISC */ 26c92544dSBjoern A. Zeeb /* Copyright (C) 2020 MediaTek Inc. */ 36c92544dSBjoern A. Zeeb 46c92544dSBjoern A. Zeeb #ifndef __MT76_CONNAC_MCU_H 56c92544dSBjoern A. Zeeb #define __MT76_CONNAC_MCU_H 66c92544dSBjoern A. Zeeb 76c92544dSBjoern A. Zeeb #include "mt76_connac.h" 86c92544dSBjoern A. Zeeb 96c92544dSBjoern A. Zeeb #define FW_FEATURE_SET_ENCRYPT BIT(0) 106c92544dSBjoern A. Zeeb #define FW_FEATURE_SET_KEY_IDX GENMASK(2, 1) 116c92544dSBjoern A. Zeeb #define FW_FEATURE_ENCRY_MODE BIT(4) 126c92544dSBjoern A. Zeeb #define FW_FEATURE_OVERRIDE_ADDR BIT(5) 136c92544dSBjoern A. Zeeb #define FW_FEATURE_NON_DL BIT(6) 146c92544dSBjoern A. Zeeb 156c92544dSBjoern A. Zeeb #define DL_MODE_ENCRYPT BIT(0) 166c92544dSBjoern A. Zeeb #define DL_MODE_KEY_IDX GENMASK(2, 1) 176c92544dSBjoern A. Zeeb #define DL_MODE_RESET_SEC_IV BIT(3) 186c92544dSBjoern A. Zeeb #define DL_MODE_WORKING_PDA_CR4 BIT(4) 196c92544dSBjoern A. Zeeb #define DL_MODE_VALID_RAM_ENTRY BIT(5) 206c92544dSBjoern A. Zeeb #define DL_CONFIG_ENCRY_MODE_SEL BIT(6) 216c92544dSBjoern A. Zeeb #define DL_MODE_NEED_RSP BIT(31) 226c92544dSBjoern A. Zeeb 236c92544dSBjoern A. Zeeb #define FW_START_OVERRIDE BIT(0) 246c92544dSBjoern A. Zeeb #define FW_START_WORKING_PDA_CR4 BIT(2) 256c92544dSBjoern A. Zeeb 266c92544dSBjoern A. Zeeb #define PATCH_SEC_NOT_SUPPORT GENMASK(31, 0) 276c92544dSBjoern A. Zeeb #define PATCH_SEC_TYPE_MASK GENMASK(15, 0) 286c92544dSBjoern A. Zeeb #define PATCH_SEC_TYPE_INFO 0x2 296c92544dSBjoern A. Zeeb 306c92544dSBjoern A. Zeeb #define PATCH_SEC_ENC_TYPE_MASK GENMASK(31, 24) 316c92544dSBjoern A. Zeeb #define PATCH_SEC_ENC_TYPE_PLAIN 0x00 326c92544dSBjoern A. Zeeb #define PATCH_SEC_ENC_TYPE_AES 0x01 336c92544dSBjoern A. Zeeb #define PATCH_SEC_ENC_TYPE_SCRAMBLE 0x02 346c92544dSBjoern A. Zeeb #define PATCH_SEC_ENC_SCRAMBLE_INFO_MASK GENMASK(15, 0) 356c92544dSBjoern A. Zeeb #define PATCH_SEC_ENC_AES_KEY_MASK GENMASK(7, 0) 366c92544dSBjoern A. Zeeb 376c92544dSBjoern A. Zeeb enum { 386c92544dSBjoern A. Zeeb FW_TYPE_DEFAULT = 0, 396c92544dSBjoern A. Zeeb FW_TYPE_CLC = 2, 406c92544dSBjoern A. Zeeb FW_TYPE_MAX_NUM = 255 416c92544dSBjoern A. Zeeb }; 426c92544dSBjoern A. Zeeb 436c92544dSBjoern A. Zeeb #define MCU_PQ_ID(p, q) (((p) << 15) | ((q) << 10)) 446c92544dSBjoern A. Zeeb #define MCU_PKT_ID 0xa0 456c92544dSBjoern A. Zeeb 466c92544dSBjoern A. Zeeb struct mt76_connac2_mcu_txd { 476c92544dSBjoern A. Zeeb __le32 txd[8]; 486c92544dSBjoern A. Zeeb 496c92544dSBjoern A. Zeeb __le16 len; 506c92544dSBjoern A. Zeeb __le16 pq_id; 516c92544dSBjoern A. Zeeb 526c92544dSBjoern A. Zeeb u8 cid; 536c92544dSBjoern A. Zeeb u8 pkt_type; 546c92544dSBjoern A. Zeeb u8 set_query; /* FW don't care */ 556c92544dSBjoern A. Zeeb u8 seq; 566c92544dSBjoern A. Zeeb 576c92544dSBjoern A. Zeeb u8 uc_d2b0_rev; 586c92544dSBjoern A. Zeeb u8 ext_cid; 596c92544dSBjoern A. Zeeb u8 s2d_index; 606c92544dSBjoern A. Zeeb u8 ext_cid_ack; 616c92544dSBjoern A. Zeeb 626c92544dSBjoern A. Zeeb u32 rsv[5]; 636c92544dSBjoern A. Zeeb } __packed __aligned(4); 646c92544dSBjoern A. Zeeb 656c92544dSBjoern A. Zeeb /** 666c92544dSBjoern A. Zeeb * struct mt76_connac2_mcu_uni_txd - mcu command descriptor for firmware v3 676c92544dSBjoern A. Zeeb * @txd: hardware descriptor 686c92544dSBjoern A. Zeeb * @len: total length not including txd 696c92544dSBjoern A. Zeeb * @cid: command identifier 706c92544dSBjoern A. Zeeb * @pkt_type: must be 0xa0 (cmd packet by long format) 716c92544dSBjoern A. Zeeb * @frag_n: fragment number 726c92544dSBjoern A. Zeeb * @seq: sequence number 736c92544dSBjoern A. Zeeb * @checksum: 0 mean there is no checksum 746c92544dSBjoern A. Zeeb * @s2d_index: index for command source and destination 756c92544dSBjoern A. Zeeb * Definition | value | note 766c92544dSBjoern A. Zeeb * CMD_S2D_IDX_H2N | 0x00 | command from HOST to WM 776c92544dSBjoern A. Zeeb * CMD_S2D_IDX_C2N | 0x01 | command from WA to WM 786c92544dSBjoern A. Zeeb * CMD_S2D_IDX_H2C | 0x02 | command from HOST to WA 796c92544dSBjoern A. Zeeb * CMD_S2D_IDX_H2N_AND_H2C | 0x03 | command from HOST to WA and WM 806c92544dSBjoern A. Zeeb * 816c92544dSBjoern A. Zeeb * @option: command option 826c92544dSBjoern A. Zeeb * BIT[0]: UNI_CMD_OPT_BIT_ACK 836c92544dSBjoern A. Zeeb * set to 1 to request a fw reply 846c92544dSBjoern A. Zeeb * if UNI_CMD_OPT_BIT_0_ACK is set and UNI_CMD_OPT_BIT_2_SET_QUERY 856c92544dSBjoern A. Zeeb * is set, mcu firmware will send response event EID = 0x01 866c92544dSBjoern A. Zeeb * (UNI_EVENT_ID_CMD_RESULT) to the host. 876c92544dSBjoern A. Zeeb * BIT[1]: UNI_CMD_OPT_BIT_UNI_CMD 886c92544dSBjoern A. Zeeb * 0: original command 896c92544dSBjoern A. Zeeb * 1: unified command 906c92544dSBjoern A. Zeeb * BIT[2]: UNI_CMD_OPT_BIT_SET_QUERY 916c92544dSBjoern A. Zeeb * 0: QUERY command 926c92544dSBjoern A. Zeeb * 1: SET command 936c92544dSBjoern A. Zeeb */ 946c92544dSBjoern A. Zeeb struct mt76_connac2_mcu_uni_txd { 956c92544dSBjoern A. Zeeb __le32 txd[8]; 966c92544dSBjoern A. Zeeb 976c92544dSBjoern A. Zeeb /* DW1 */ 986c92544dSBjoern A. Zeeb __le16 len; 996c92544dSBjoern A. Zeeb __le16 cid; 1006c92544dSBjoern A. Zeeb 1016c92544dSBjoern A. Zeeb /* DW2 */ 1026c92544dSBjoern A. Zeeb u8 rsv; 1036c92544dSBjoern A. Zeeb u8 pkt_type; 1046c92544dSBjoern A. Zeeb u8 frag_n; 1056c92544dSBjoern A. Zeeb u8 seq; 1066c92544dSBjoern A. Zeeb 1076c92544dSBjoern A. Zeeb /* DW3 */ 1086c92544dSBjoern A. Zeeb __le16 checksum; 1096c92544dSBjoern A. Zeeb u8 s2d_index; 1106c92544dSBjoern A. Zeeb u8 option; 1116c92544dSBjoern A. Zeeb 1126c92544dSBjoern A. Zeeb /* DW4 */ 1136c92544dSBjoern A. Zeeb u8 rsv1[4]; 1146c92544dSBjoern A. Zeeb } __packed __aligned(4); 1156c92544dSBjoern A. Zeeb 1166c92544dSBjoern A. Zeeb struct mt76_connac2_mcu_rxd { 1176c92544dSBjoern A. Zeeb __le32 rxd[6]; 1186c92544dSBjoern A. Zeeb 1196c92544dSBjoern A. Zeeb __le16 len; 1206c92544dSBjoern A. Zeeb __le16 pkt_type_id; 1216c92544dSBjoern A. Zeeb 1226c92544dSBjoern A. Zeeb u8 eid; 1236c92544dSBjoern A. Zeeb u8 seq; 1246c92544dSBjoern A. Zeeb u8 rsv[2]; 1256c92544dSBjoern A. Zeeb 1266c92544dSBjoern A. Zeeb u8 ext_eid; 1276c92544dSBjoern A. Zeeb u8 rsv1[2]; 1286c92544dSBjoern A. Zeeb u8 s2d_index; 1296c92544dSBjoern A. Zeeb }; 1306c92544dSBjoern A. Zeeb 1316c92544dSBjoern A. Zeeb struct mt76_connac2_patch_hdr { 1326c92544dSBjoern A. Zeeb char build_date[16]; 1336c92544dSBjoern A. Zeeb char platform[4]; 1346c92544dSBjoern A. Zeeb __be32 hw_sw_ver; 1356c92544dSBjoern A. Zeeb __be32 patch_ver; 1366c92544dSBjoern A. Zeeb __be16 checksum; 1376c92544dSBjoern A. Zeeb u16 rsv; 1386c92544dSBjoern A. Zeeb struct { 1396c92544dSBjoern A. Zeeb __be32 patch_ver; 1406c92544dSBjoern A. Zeeb __be32 subsys; 1416c92544dSBjoern A. Zeeb __be32 feature; 1426c92544dSBjoern A. Zeeb __be32 n_region; 1436c92544dSBjoern A. Zeeb __be32 crc; 1446c92544dSBjoern A. Zeeb u32 rsv[11]; 1456c92544dSBjoern A. Zeeb } desc; 1466c92544dSBjoern A. Zeeb } __packed; 1476c92544dSBjoern A. Zeeb 1486c92544dSBjoern A. Zeeb struct mt76_connac2_patch_sec { 1496c92544dSBjoern A. Zeeb __be32 type; 1506c92544dSBjoern A. Zeeb __be32 offs; 1516c92544dSBjoern A. Zeeb __be32 size; 1526c92544dSBjoern A. Zeeb union { 1536c92544dSBjoern A. Zeeb __be32 spec[13]; 1546c92544dSBjoern A. Zeeb struct { 1556c92544dSBjoern A. Zeeb __be32 addr; 1566c92544dSBjoern A. Zeeb __be32 len; 1576c92544dSBjoern A. Zeeb __be32 sec_key_idx; 1586c92544dSBjoern A. Zeeb __be32 align_len; 1596c92544dSBjoern A. Zeeb u32 rsv[9]; 1606c92544dSBjoern A. Zeeb } info; 1616c92544dSBjoern A. Zeeb }; 1626c92544dSBjoern A. Zeeb } __packed; 1636c92544dSBjoern A. Zeeb 1646c92544dSBjoern A. Zeeb struct mt76_connac2_fw_trailer { 1656c92544dSBjoern A. Zeeb u8 chip_id; 1666c92544dSBjoern A. Zeeb u8 eco_code; 1676c92544dSBjoern A. Zeeb u8 n_region; 1686c92544dSBjoern A. Zeeb u8 format_ver; 1696c92544dSBjoern A. Zeeb u8 format_flag; 1706c92544dSBjoern A. Zeeb u8 rsv[2]; 1716c92544dSBjoern A. Zeeb char fw_ver[10]; 1726c92544dSBjoern A. Zeeb char build_date[15]; 1736c92544dSBjoern A. Zeeb __le32 crc; 1746c92544dSBjoern A. Zeeb } __packed; 1756c92544dSBjoern A. Zeeb 1766c92544dSBjoern A. Zeeb struct mt76_connac2_fw_region { 1776c92544dSBjoern A. Zeeb __le32 decomp_crc; 1786c92544dSBjoern A. Zeeb __le32 decomp_len; 1796c92544dSBjoern A. Zeeb __le32 decomp_blk_sz; 1806c92544dSBjoern A. Zeeb u8 rsv[4]; 1816c92544dSBjoern A. Zeeb __le32 addr; 1826c92544dSBjoern A. Zeeb __le32 len; 1836c92544dSBjoern A. Zeeb u8 feature_set; 1846c92544dSBjoern A. Zeeb u8 type; 1856c92544dSBjoern A. Zeeb u8 rsv1[14]; 1866c92544dSBjoern A. Zeeb } __packed; 1876c92544dSBjoern A. Zeeb 1886c92544dSBjoern A. Zeeb struct tlv { 1896c92544dSBjoern A. Zeeb __le16 tag; 1906c92544dSBjoern A. Zeeb __le16 len; 1916c92544dSBjoern A. Zeeb } __packed; 1926c92544dSBjoern A. Zeeb 1936c92544dSBjoern A. Zeeb struct bss_info_omac { 1946c92544dSBjoern A. Zeeb __le16 tag; 1956c92544dSBjoern A. Zeeb __le16 len; 1966c92544dSBjoern A. Zeeb u8 hw_bss_idx; 1976c92544dSBjoern A. Zeeb u8 omac_idx; 1986c92544dSBjoern A. Zeeb u8 band_idx; 1996c92544dSBjoern A. Zeeb u8 rsv0; 2006c92544dSBjoern A. Zeeb __le32 conn_type; 2016c92544dSBjoern A. Zeeb u32 rsv1; 2026c92544dSBjoern A. Zeeb } __packed; 2036c92544dSBjoern A. Zeeb 2046c92544dSBjoern A. Zeeb struct bss_info_basic { 2056c92544dSBjoern A. Zeeb __le16 tag; 2066c92544dSBjoern A. Zeeb __le16 len; 2076c92544dSBjoern A. Zeeb __le32 network_type; 2086c92544dSBjoern A. Zeeb u8 active; 2096c92544dSBjoern A. Zeeb u8 rsv0; 2106c92544dSBjoern A. Zeeb __le16 bcn_interval; 2116c92544dSBjoern A. Zeeb u8 bssid[ETH_ALEN]; 2126c92544dSBjoern A. Zeeb u8 wmm_idx; 2136c92544dSBjoern A. Zeeb u8 dtim_period; 2146c92544dSBjoern A. Zeeb u8 bmc_wcid_lo; 2156c92544dSBjoern A. Zeeb u8 cipher; 2166c92544dSBjoern A. Zeeb u8 phy_mode; 2176c92544dSBjoern A. Zeeb u8 max_bssid; /* max BSSID. range: 1 ~ 8, 0: MBSSID disabled */ 2186c92544dSBjoern A. Zeeb u8 non_tx_bssid;/* non-transmitted BSSID, 0: transmitted BSSID */ 2196c92544dSBjoern A. Zeeb u8 bmc_wcid_hi; /* high Byte and version */ 2206c92544dSBjoern A. Zeeb u8 rsv[2]; 2216c92544dSBjoern A. Zeeb } __packed; 2226c92544dSBjoern A. Zeeb 2236c92544dSBjoern A. Zeeb struct bss_info_rf_ch { 2246c92544dSBjoern A. Zeeb __le16 tag; 2256c92544dSBjoern A. Zeeb __le16 len; 2266c92544dSBjoern A. Zeeb u8 pri_ch; 2276c92544dSBjoern A. Zeeb u8 center_ch0; 2286c92544dSBjoern A. Zeeb u8 center_ch1; 2296c92544dSBjoern A. Zeeb u8 bw; 2306c92544dSBjoern A. Zeeb u8 he_ru26_block; /* 1: don't send HETB in RU26, 0: allow */ 2316c92544dSBjoern A. Zeeb u8 he_all_disable; /* 1: disallow all HETB, 0: allow */ 2326c92544dSBjoern A. Zeeb u8 rsv[2]; 2336c92544dSBjoern A. Zeeb } __packed; 2346c92544dSBjoern A. Zeeb 2356c92544dSBjoern A. Zeeb struct bss_info_ext_bss { 2366c92544dSBjoern A. Zeeb __le16 tag; 2376c92544dSBjoern A. Zeeb __le16 len; 2386c92544dSBjoern A. Zeeb __le32 mbss_tsf_offset; /* in unit of us */ 2396c92544dSBjoern A. Zeeb u8 rsv[8]; 2406c92544dSBjoern A. Zeeb } __packed; 2416c92544dSBjoern A. Zeeb 2426c92544dSBjoern A. Zeeb enum { 2436c92544dSBjoern A. Zeeb BSS_INFO_OMAC, 2446c92544dSBjoern A. Zeeb BSS_INFO_BASIC, 2456c92544dSBjoern A. Zeeb BSS_INFO_RF_CH, /* optional, for BT/LTE coex */ 2466c92544dSBjoern A. Zeeb BSS_INFO_PM, /* sta only */ 2476c92544dSBjoern A. Zeeb BSS_INFO_UAPSD, /* sta only */ 2486c92544dSBjoern A. Zeeb BSS_INFO_ROAM_DETECT, /* obsoleted */ 2496c92544dSBjoern A. Zeeb BSS_INFO_LQ_RM, /* obsoleted */ 2506c92544dSBjoern A. Zeeb BSS_INFO_EXT_BSS, 2516c92544dSBjoern A. Zeeb BSS_INFO_BMC_RATE, /* for bmc rate control in CR4 */ 2526c92544dSBjoern A. Zeeb BSS_INFO_SYNC_MODE, /* obsoleted */ 2536c92544dSBjoern A. Zeeb BSS_INFO_RA, 2546c92544dSBjoern A. Zeeb BSS_INFO_HW_AMSDU, 2556c92544dSBjoern A. Zeeb BSS_INFO_BSS_COLOR, 2566c92544dSBjoern A. Zeeb BSS_INFO_HE_BASIC, 2576c92544dSBjoern A. Zeeb BSS_INFO_PROTECT_INFO, 2586c92544dSBjoern A. Zeeb BSS_INFO_OFFLOAD, 2596c92544dSBjoern A. Zeeb BSS_INFO_11V_MBSSID, 2606c92544dSBjoern A. Zeeb BSS_INFO_MAX_NUM 2616c92544dSBjoern A. Zeeb }; 2626c92544dSBjoern A. Zeeb 2636c92544dSBjoern A. Zeeb /* sta_rec */ 2646c92544dSBjoern A. Zeeb 2656c92544dSBjoern A. Zeeb struct sta_ntlv_hdr { 2666c92544dSBjoern A. Zeeb u8 rsv[2]; 2676c92544dSBjoern A. Zeeb __le16 tlv_num; 2686c92544dSBjoern A. Zeeb } __packed; 2696c92544dSBjoern A. Zeeb 2706c92544dSBjoern A. Zeeb struct sta_req_hdr { 2716c92544dSBjoern A. Zeeb u8 bss_idx; 2726c92544dSBjoern A. Zeeb u8 wlan_idx_lo; 2736c92544dSBjoern A. Zeeb __le16 tlv_num; 2746c92544dSBjoern A. Zeeb u8 is_tlv_append; 2756c92544dSBjoern A. Zeeb u8 muar_idx; 2766c92544dSBjoern A. Zeeb u8 wlan_idx_hi; 2776c92544dSBjoern A. Zeeb u8 rsv; 2786c92544dSBjoern A. Zeeb } __packed; 2796c92544dSBjoern A. Zeeb 2806c92544dSBjoern A. Zeeb struct sta_rec_basic { 2816c92544dSBjoern A. Zeeb __le16 tag; 2826c92544dSBjoern A. Zeeb __le16 len; 2836c92544dSBjoern A. Zeeb __le32 conn_type; 2846c92544dSBjoern A. Zeeb u8 conn_state; 2856c92544dSBjoern A. Zeeb u8 qos; 2866c92544dSBjoern A. Zeeb __le16 aid; 2876c92544dSBjoern A. Zeeb u8 peer_addr[ETH_ALEN]; 2886c92544dSBjoern A. Zeeb #define EXTRA_INFO_VER BIT(0) 2896c92544dSBjoern A. Zeeb #define EXTRA_INFO_NEW BIT(1) 2906c92544dSBjoern A. Zeeb __le16 extra_info; 2916c92544dSBjoern A. Zeeb } __packed; 2926c92544dSBjoern A. Zeeb 2936c92544dSBjoern A. Zeeb struct sta_rec_ht { 2946c92544dSBjoern A. Zeeb __le16 tag; 2956c92544dSBjoern A. Zeeb __le16 len; 2966c92544dSBjoern A. Zeeb __le16 ht_cap; 2976c92544dSBjoern A. Zeeb u16 rsv; 2986c92544dSBjoern A. Zeeb } __packed; 2996c92544dSBjoern A. Zeeb 3006c92544dSBjoern A. Zeeb struct sta_rec_vht { 3016c92544dSBjoern A. Zeeb __le16 tag; 3026c92544dSBjoern A. Zeeb __le16 len; 3036c92544dSBjoern A. Zeeb __le32 vht_cap; 3046c92544dSBjoern A. Zeeb __le16 vht_rx_mcs_map; 3056c92544dSBjoern A. Zeeb __le16 vht_tx_mcs_map; 3066c92544dSBjoern A. Zeeb /* mt7915 - mt7921 */ 3076c92544dSBjoern A. Zeeb u8 rts_bw_sig; 3086c92544dSBjoern A. Zeeb u8 rsv[3]; 3096c92544dSBjoern A. Zeeb } __packed; 3106c92544dSBjoern A. Zeeb 3116c92544dSBjoern A. Zeeb struct sta_rec_uapsd { 3126c92544dSBjoern A. Zeeb __le16 tag; 3136c92544dSBjoern A. Zeeb __le16 len; 3146c92544dSBjoern A. Zeeb u8 dac_map; 3156c92544dSBjoern A. Zeeb u8 tac_map; 3166c92544dSBjoern A. Zeeb u8 max_sp; 3176c92544dSBjoern A. Zeeb u8 rsv0; 3186c92544dSBjoern A. Zeeb __le16 listen_interval; 3196c92544dSBjoern A. Zeeb u8 rsv1[2]; 3206c92544dSBjoern A. Zeeb } __packed; 3216c92544dSBjoern A. Zeeb 3226c92544dSBjoern A. Zeeb struct sta_rec_ba { 3236c92544dSBjoern A. Zeeb __le16 tag; 3246c92544dSBjoern A. Zeeb __le16 len; 3256c92544dSBjoern A. Zeeb u8 tid; 3266c92544dSBjoern A. Zeeb u8 ba_type; 3276c92544dSBjoern A. Zeeb u8 amsdu; 3286c92544dSBjoern A. Zeeb u8 ba_en; 3296c92544dSBjoern A. Zeeb __le16 ssn; 3306c92544dSBjoern A. Zeeb __le16 winsize; 3316c92544dSBjoern A. Zeeb } __packed; 3326c92544dSBjoern A. Zeeb 3336c92544dSBjoern A. Zeeb struct sta_rec_he { 3346c92544dSBjoern A. Zeeb __le16 tag; 3356c92544dSBjoern A. Zeeb __le16 len; 3366c92544dSBjoern A. Zeeb 3376c92544dSBjoern A. Zeeb __le32 he_cap; 3386c92544dSBjoern A. Zeeb 3396c92544dSBjoern A. Zeeb u8 t_frame_dur; 3406c92544dSBjoern A. Zeeb u8 max_ampdu_exp; 3416c92544dSBjoern A. Zeeb u8 bw_set; 3426c92544dSBjoern A. Zeeb u8 device_class; 3436c92544dSBjoern A. Zeeb u8 dcm_tx_mode; 3446c92544dSBjoern A. Zeeb u8 dcm_tx_max_nss; 3456c92544dSBjoern A. Zeeb u8 dcm_rx_mode; 3466c92544dSBjoern A. Zeeb u8 dcm_rx_max_nss; 3476c92544dSBjoern A. Zeeb u8 dcm_max_ru; 3486c92544dSBjoern A. Zeeb u8 punc_pream_rx; 3496c92544dSBjoern A. Zeeb u8 pkt_ext; 3506c92544dSBjoern A. Zeeb u8 rsv1; 3516c92544dSBjoern A. Zeeb 3526c92544dSBjoern A. Zeeb __le16 max_nss_mcs[CMD_HE_MCS_BW_NUM]; 3536c92544dSBjoern A. Zeeb 3546c92544dSBjoern A. Zeeb u8 rsv2[2]; 3556c92544dSBjoern A. Zeeb } __packed; 3566c92544dSBjoern A. Zeeb 3576c92544dSBjoern A. Zeeb struct sta_rec_amsdu { 3586c92544dSBjoern A. Zeeb __le16 tag; 3596c92544dSBjoern A. Zeeb __le16 len; 3606c92544dSBjoern A. Zeeb u8 max_amsdu_num; 3616c92544dSBjoern A. Zeeb u8 max_mpdu_size; 3626c92544dSBjoern A. Zeeb u8 amsdu_en; 3636c92544dSBjoern A. Zeeb u8 rsv; 3646c92544dSBjoern A. Zeeb } __packed; 3656c92544dSBjoern A. Zeeb 3666c92544dSBjoern A. Zeeb struct sta_rec_state { 3676c92544dSBjoern A. Zeeb __le16 tag; 3686c92544dSBjoern A. Zeeb __le16 len; 3696c92544dSBjoern A. Zeeb __le32 flags; 3706c92544dSBjoern A. Zeeb u8 state; 3716c92544dSBjoern A. Zeeb u8 vht_opmode; 3726c92544dSBjoern A. Zeeb u8 action; 3736c92544dSBjoern A. Zeeb u8 rsv[1]; 3746c92544dSBjoern A. Zeeb } __packed; 3756c92544dSBjoern A. Zeeb 3766c92544dSBjoern A. Zeeb #define RA_LEGACY_OFDM GENMASK(13, 6) 3776c92544dSBjoern A. Zeeb #define RA_LEGACY_CCK GENMASK(3, 0) 3786c92544dSBjoern A. Zeeb #define HT_MCS_MASK_NUM 10 3796c92544dSBjoern A. Zeeb struct sta_rec_ra_info { 3806c92544dSBjoern A. Zeeb __le16 tag; 3816c92544dSBjoern A. Zeeb __le16 len; 3826c92544dSBjoern A. Zeeb __le16 legacy; 3836c92544dSBjoern A. Zeeb u8 rx_mcs_bitmask[HT_MCS_MASK_NUM]; 3846c92544dSBjoern A. Zeeb } __packed; 3856c92544dSBjoern A. Zeeb 3866c92544dSBjoern A. Zeeb struct sta_rec_phy { 3876c92544dSBjoern A. Zeeb __le16 tag; 3886c92544dSBjoern A. Zeeb __le16 len; 3896c92544dSBjoern A. Zeeb __le16 basic_rate; 3906c92544dSBjoern A. Zeeb u8 phy_type; 3916c92544dSBjoern A. Zeeb u8 ampdu; 3926c92544dSBjoern A. Zeeb u8 rts_policy; 3936c92544dSBjoern A. Zeeb u8 rcpi; 3946c92544dSBjoern A. Zeeb u8 rsv[2]; 3956c92544dSBjoern A. Zeeb } __packed; 3966c92544dSBjoern A. Zeeb 3976c92544dSBjoern A. Zeeb struct sta_rec_he_6g_capa { 3986c92544dSBjoern A. Zeeb __le16 tag; 3996c92544dSBjoern A. Zeeb __le16 len; 4006c92544dSBjoern A. Zeeb __le16 capa; 4016c92544dSBjoern A. Zeeb u8 rsv[2]; 4026c92544dSBjoern A. Zeeb } __packed; 4036c92544dSBjoern A. Zeeb 4046c92544dSBjoern A. Zeeb struct sec_key { 4056c92544dSBjoern A. Zeeb u8 cipher_id; 4066c92544dSBjoern A. Zeeb u8 cipher_len; 4076c92544dSBjoern A. Zeeb u8 key_id; 4086c92544dSBjoern A. Zeeb u8 key_len; 4096c92544dSBjoern A. Zeeb u8 key[32]; 4106c92544dSBjoern A. Zeeb } __packed; 4116c92544dSBjoern A. Zeeb 4126c92544dSBjoern A. Zeeb struct sta_rec_sec { 4136c92544dSBjoern A. Zeeb __le16 tag; 4146c92544dSBjoern A. Zeeb __le16 len; 4156c92544dSBjoern A. Zeeb u8 add; 4166c92544dSBjoern A. Zeeb u8 n_cipher; 4176c92544dSBjoern A. Zeeb u8 rsv[2]; 4186c92544dSBjoern A. Zeeb 4196c92544dSBjoern A. Zeeb struct sec_key key[2]; 4206c92544dSBjoern A. Zeeb } __packed; 4216c92544dSBjoern A. Zeeb 4226c92544dSBjoern A. Zeeb struct sta_rec_bf { 4236c92544dSBjoern A. Zeeb __le16 tag; 4246c92544dSBjoern A. Zeeb __le16 len; 4256c92544dSBjoern A. Zeeb 4266c92544dSBjoern A. Zeeb __le16 pfmu; /* 0xffff: no access right for PFMU */ 4276c92544dSBjoern A. Zeeb bool su_mu; /* 0: SU, 1: MU */ 4286c92544dSBjoern A. Zeeb u8 bf_cap; /* 0: iBF, 1: eBF */ 4296c92544dSBjoern A. Zeeb u8 sounding_phy; /* 0: legacy, 1: OFDM, 2: HT, 4: VHT */ 4306c92544dSBjoern A. Zeeb u8 ndpa_rate; 4316c92544dSBjoern A. Zeeb u8 ndp_rate; 4326c92544dSBjoern A. Zeeb u8 rept_poll_rate; 4336c92544dSBjoern A. Zeeb u8 tx_mode; /* 0: legacy, 1: OFDM, 2: HT, 4: VHT ... */ 4346c92544dSBjoern A. Zeeb u8 ncol; 4356c92544dSBjoern A. Zeeb u8 nrow; 4366c92544dSBjoern A. Zeeb u8 bw; /* 0: 20M, 1: 40M, 2: 80M, 3: 160M */ 4376c92544dSBjoern A. Zeeb 4386c92544dSBjoern A. Zeeb u8 mem_total; 4396c92544dSBjoern A. Zeeb u8 mem_20m; 4406c92544dSBjoern A. Zeeb struct { 4416c92544dSBjoern A. Zeeb u8 row; 4426c92544dSBjoern A. Zeeb u8 col: 6, row_msb: 2; 4436c92544dSBjoern A. Zeeb } mem[4]; 4446c92544dSBjoern A. Zeeb 4456c92544dSBjoern A. Zeeb __le16 smart_ant; 4466c92544dSBjoern A. Zeeb u8 se_idx; 4476c92544dSBjoern A. Zeeb u8 auto_sounding; /* b7: low traffic indicator 4486c92544dSBjoern A. Zeeb * b6: Stop sounding for this entry 4496c92544dSBjoern A. Zeeb * b5 ~ b0: postpone sounding 4506c92544dSBjoern A. Zeeb */ 4516c92544dSBjoern A. Zeeb u8 ibf_timeout; 4526c92544dSBjoern A. Zeeb u8 ibf_dbw; 4536c92544dSBjoern A. Zeeb u8 ibf_ncol; 4546c92544dSBjoern A. Zeeb u8 ibf_nrow; 4556c92544dSBjoern A. Zeeb u8 nrow_bw160; 4566c92544dSBjoern A. Zeeb u8 ncol_bw160; 4576c92544dSBjoern A. Zeeb u8 ru_start_idx; 4586c92544dSBjoern A. Zeeb u8 ru_end_idx; 4596c92544dSBjoern A. Zeeb 4606c92544dSBjoern A. Zeeb bool trigger_su; 4616c92544dSBjoern A. Zeeb bool trigger_mu; 4626c92544dSBjoern A. Zeeb bool ng16_su; 4636c92544dSBjoern A. Zeeb bool ng16_mu; 4646c92544dSBjoern A. Zeeb bool codebook42_su; 4656c92544dSBjoern A. Zeeb bool codebook75_mu; 4666c92544dSBjoern A. Zeeb 4676c92544dSBjoern A. Zeeb u8 he_ltf; 4686c92544dSBjoern A. Zeeb u8 rsv[3]; 4696c92544dSBjoern A. Zeeb } __packed; 4706c92544dSBjoern A. Zeeb 4716c92544dSBjoern A. Zeeb struct sta_rec_bfee { 4726c92544dSBjoern A. Zeeb __le16 tag; 4736c92544dSBjoern A. Zeeb __le16 len; 4746c92544dSBjoern A. Zeeb bool fb_identity_matrix; /* 1: feedback identity matrix */ 4756c92544dSBjoern A. Zeeb bool ignore_feedback; /* 1: ignore */ 4766c92544dSBjoern A. Zeeb u8 rsv[2]; 4776c92544dSBjoern A. Zeeb } __packed; 4786c92544dSBjoern A. Zeeb 4796c92544dSBjoern A. Zeeb struct sta_rec_muru { 4806c92544dSBjoern A. Zeeb __le16 tag; 4816c92544dSBjoern A. Zeeb __le16 len; 4826c92544dSBjoern A. Zeeb 4836c92544dSBjoern A. Zeeb struct { 4846c92544dSBjoern A. Zeeb bool ofdma_dl_en; 4856c92544dSBjoern A. Zeeb bool ofdma_ul_en; 4866c92544dSBjoern A. Zeeb bool mimo_dl_en; 4876c92544dSBjoern A. Zeeb bool mimo_ul_en; 4886c92544dSBjoern A. Zeeb u8 rsv[4]; 4896c92544dSBjoern A. Zeeb } cfg; 4906c92544dSBjoern A. Zeeb 4916c92544dSBjoern A. Zeeb struct { 4926c92544dSBjoern A. Zeeb u8 punc_pream_rx; 4936c92544dSBjoern A. Zeeb bool he_20m_in_40m_2g; 4946c92544dSBjoern A. Zeeb bool he_20m_in_160m; 4956c92544dSBjoern A. Zeeb bool he_80m_in_160m; 4966c92544dSBjoern A. Zeeb bool lt16_sigb; 4976c92544dSBjoern A. Zeeb bool rx_su_comp_sigb; 4986c92544dSBjoern A. Zeeb bool rx_su_non_comp_sigb; 4996c92544dSBjoern A. Zeeb u8 rsv; 5006c92544dSBjoern A. Zeeb } ofdma_dl; 5016c92544dSBjoern A. Zeeb 5026c92544dSBjoern A. Zeeb struct { 5036c92544dSBjoern A. Zeeb u8 t_frame_dur; 5046c92544dSBjoern A. Zeeb u8 mu_cascading; 5056c92544dSBjoern A. Zeeb u8 uo_ra; 5066c92544dSBjoern A. Zeeb u8 he_2x996_tone; 5076c92544dSBjoern A. Zeeb u8 rx_t_frame_11ac; 5086c92544dSBjoern A. Zeeb u8 rsv[3]; 5096c92544dSBjoern A. Zeeb } ofdma_ul; 5106c92544dSBjoern A. Zeeb 5116c92544dSBjoern A. Zeeb struct { 5126c92544dSBjoern A. Zeeb bool vht_mu_bfee; 5136c92544dSBjoern A. Zeeb bool partial_bw_dl_mimo; 5146c92544dSBjoern A. Zeeb u8 rsv[2]; 5156c92544dSBjoern A. Zeeb } mimo_dl; 5166c92544dSBjoern A. Zeeb 5176c92544dSBjoern A. Zeeb struct { 5186c92544dSBjoern A. Zeeb bool full_ul_mimo; 5196c92544dSBjoern A. Zeeb bool partial_ul_mimo; 5206c92544dSBjoern A. Zeeb u8 rsv[2]; 5216c92544dSBjoern A. Zeeb } mimo_ul; 5226c92544dSBjoern A. Zeeb } __packed; 5236c92544dSBjoern A. Zeeb 5246c92544dSBjoern A. Zeeb struct sta_phy { 5256c92544dSBjoern A. Zeeb u8 type; 5266c92544dSBjoern A. Zeeb u8 flag; 5276c92544dSBjoern A. Zeeb u8 stbc; 5286c92544dSBjoern A. Zeeb u8 sgi; 5296c92544dSBjoern A. Zeeb u8 bw; 5306c92544dSBjoern A. Zeeb u8 ldpc; 5316c92544dSBjoern A. Zeeb u8 mcs; 5326c92544dSBjoern A. Zeeb u8 nss; 5336c92544dSBjoern A. Zeeb u8 he_ltf; 5346c92544dSBjoern A. Zeeb }; 5356c92544dSBjoern A. Zeeb 5366c92544dSBjoern A. Zeeb struct sta_rec_ra { 5376c92544dSBjoern A. Zeeb __le16 tag; 5386c92544dSBjoern A. Zeeb __le16 len; 5396c92544dSBjoern A. Zeeb 5406c92544dSBjoern A. Zeeb u8 valid; 5416c92544dSBjoern A. Zeeb u8 auto_rate; 5426c92544dSBjoern A. Zeeb u8 phy_mode; 5436c92544dSBjoern A. Zeeb u8 channel; 5446c92544dSBjoern A. Zeeb u8 bw; 5456c92544dSBjoern A. Zeeb u8 disable_cck; 5466c92544dSBjoern A. Zeeb u8 ht_mcs32; 5476c92544dSBjoern A. Zeeb u8 ht_gf; 5486c92544dSBjoern A. Zeeb u8 ht_mcs[4]; 5496c92544dSBjoern A. Zeeb u8 mmps_mode; 5506c92544dSBjoern A. Zeeb u8 gband_256; 5516c92544dSBjoern A. Zeeb u8 af; 5526c92544dSBjoern A. Zeeb u8 auth_wapi_mode; 5536c92544dSBjoern A. Zeeb u8 rate_len; 5546c92544dSBjoern A. Zeeb 5556c92544dSBjoern A. Zeeb u8 supp_mode; 5566c92544dSBjoern A. Zeeb u8 supp_cck_rate; 5576c92544dSBjoern A. Zeeb u8 supp_ofdm_rate; 5586c92544dSBjoern A. Zeeb __le32 supp_ht_mcs; 5596c92544dSBjoern A. Zeeb __le16 supp_vht_mcs[4]; 5606c92544dSBjoern A. Zeeb 5616c92544dSBjoern A. Zeeb u8 op_mode; 5626c92544dSBjoern A. Zeeb u8 op_vht_chan_width; 5636c92544dSBjoern A. Zeeb u8 op_vht_rx_nss; 5646c92544dSBjoern A. Zeeb u8 op_vht_rx_nss_type; 5656c92544dSBjoern A. Zeeb 5666c92544dSBjoern A. Zeeb __le32 sta_cap; 5676c92544dSBjoern A. Zeeb 5686c92544dSBjoern A. Zeeb struct sta_phy phy; 5696c92544dSBjoern A. Zeeb } __packed; 5706c92544dSBjoern A. Zeeb 5716c92544dSBjoern A. Zeeb struct sta_rec_ra_fixed { 5726c92544dSBjoern A. Zeeb __le16 tag; 5736c92544dSBjoern A. Zeeb __le16 len; 5746c92544dSBjoern A. Zeeb 5756c92544dSBjoern A. Zeeb __le32 field; 5766c92544dSBjoern A. Zeeb u8 op_mode; 5776c92544dSBjoern A. Zeeb u8 op_vht_chan_width; 5786c92544dSBjoern A. Zeeb u8 op_vht_rx_nss; 5796c92544dSBjoern A. Zeeb u8 op_vht_rx_nss_type; 5806c92544dSBjoern A. Zeeb 5816c92544dSBjoern A. Zeeb struct sta_phy phy; 5826c92544dSBjoern A. Zeeb 5836c92544dSBjoern A. Zeeb u8 spe_en; 5846c92544dSBjoern A. Zeeb u8 short_preamble; 5856c92544dSBjoern A. Zeeb u8 is_5g; 5866c92544dSBjoern A. Zeeb u8 mmps_mode; 5876c92544dSBjoern A. Zeeb } __packed; 5886c92544dSBjoern A. Zeeb 5896c92544dSBjoern A. Zeeb /* wtbl_rec */ 5906c92544dSBjoern A. Zeeb 5916c92544dSBjoern A. Zeeb struct wtbl_req_hdr { 5926c92544dSBjoern A. Zeeb u8 wlan_idx_lo; 5936c92544dSBjoern A. Zeeb u8 operation; 5946c92544dSBjoern A. Zeeb __le16 tlv_num; 5956c92544dSBjoern A. Zeeb u8 wlan_idx_hi; 5966c92544dSBjoern A. Zeeb u8 rsv[3]; 5976c92544dSBjoern A. Zeeb } __packed; 5986c92544dSBjoern A. Zeeb 5996c92544dSBjoern A. Zeeb struct wtbl_generic { 6006c92544dSBjoern A. Zeeb __le16 tag; 6016c92544dSBjoern A. Zeeb __le16 len; 6026c92544dSBjoern A. Zeeb u8 peer_addr[ETH_ALEN]; 6036c92544dSBjoern A. Zeeb u8 muar_idx; 6046c92544dSBjoern A. Zeeb u8 skip_tx; 6056c92544dSBjoern A. Zeeb u8 cf_ack; 6066c92544dSBjoern A. Zeeb u8 qos; 6076c92544dSBjoern A. Zeeb u8 mesh; 6086c92544dSBjoern A. Zeeb u8 adm; 6096c92544dSBjoern A. Zeeb __le16 partial_aid; 6106c92544dSBjoern A. Zeeb u8 baf_en; 6116c92544dSBjoern A. Zeeb u8 aad_om; 6126c92544dSBjoern A. Zeeb } __packed; 6136c92544dSBjoern A. Zeeb 6146c92544dSBjoern A. Zeeb struct wtbl_rx { 6156c92544dSBjoern A. Zeeb __le16 tag; 6166c92544dSBjoern A. Zeeb __le16 len; 6176c92544dSBjoern A. Zeeb u8 rcid; 6186c92544dSBjoern A. Zeeb u8 rca1; 6196c92544dSBjoern A. Zeeb u8 rca2; 6206c92544dSBjoern A. Zeeb u8 rv; 6216c92544dSBjoern A. Zeeb u8 rsv[4]; 6226c92544dSBjoern A. Zeeb } __packed; 6236c92544dSBjoern A. Zeeb 6246c92544dSBjoern A. Zeeb struct wtbl_ht { 6256c92544dSBjoern A. Zeeb __le16 tag; 6266c92544dSBjoern A. Zeeb __le16 len; 6276c92544dSBjoern A. Zeeb u8 ht; 6286c92544dSBjoern A. Zeeb u8 ldpc; 6296c92544dSBjoern A. Zeeb u8 af; 6306c92544dSBjoern A. Zeeb u8 mm; 6316c92544dSBjoern A. Zeeb u8 rsv[4]; 6326c92544dSBjoern A. Zeeb } __packed; 6336c92544dSBjoern A. Zeeb 6346c92544dSBjoern A. Zeeb struct wtbl_vht { 6356c92544dSBjoern A. Zeeb __le16 tag; 6366c92544dSBjoern A. Zeeb __le16 len; 6376c92544dSBjoern A. Zeeb u8 ldpc; 6386c92544dSBjoern A. Zeeb u8 dyn_bw; 6396c92544dSBjoern A. Zeeb u8 vht; 6406c92544dSBjoern A. Zeeb u8 txop_ps; 6416c92544dSBjoern A. Zeeb u8 rsv[4]; 6426c92544dSBjoern A. Zeeb } __packed; 6436c92544dSBjoern A. Zeeb 6446c92544dSBjoern A. Zeeb struct wtbl_tx_ps { 6456c92544dSBjoern A. Zeeb __le16 tag; 6466c92544dSBjoern A. Zeeb __le16 len; 6476c92544dSBjoern A. Zeeb u8 txps; 6486c92544dSBjoern A. Zeeb u8 rsv[3]; 6496c92544dSBjoern A. Zeeb } __packed; 6506c92544dSBjoern A. Zeeb 6516c92544dSBjoern A. Zeeb struct wtbl_hdr_trans { 6526c92544dSBjoern A. Zeeb __le16 tag; 6536c92544dSBjoern A. Zeeb __le16 len; 6546c92544dSBjoern A. Zeeb u8 to_ds; 6556c92544dSBjoern A. Zeeb u8 from_ds; 6566c92544dSBjoern A. Zeeb u8 no_rx_trans; 6576c92544dSBjoern A. Zeeb u8 rsv; 6586c92544dSBjoern A. Zeeb } __packed; 6596c92544dSBjoern A. Zeeb 6606c92544dSBjoern A. Zeeb struct wtbl_ba { 6616c92544dSBjoern A. Zeeb __le16 tag; 6626c92544dSBjoern A. Zeeb __le16 len; 6636c92544dSBjoern A. Zeeb /* common */ 6646c92544dSBjoern A. Zeeb u8 tid; 6656c92544dSBjoern A. Zeeb u8 ba_type; 6666c92544dSBjoern A. Zeeb u8 rsv0[2]; 6676c92544dSBjoern A. Zeeb /* originator only */ 6686c92544dSBjoern A. Zeeb __le16 sn; 6696c92544dSBjoern A. Zeeb u8 ba_en; 6706c92544dSBjoern A. Zeeb u8 ba_winsize_idx; 6716c92544dSBjoern A. Zeeb /* originator & recipient */ 6726c92544dSBjoern A. Zeeb __le16 ba_winsize; 6736c92544dSBjoern A. Zeeb /* recipient only */ 6746c92544dSBjoern A. Zeeb u8 peer_addr[ETH_ALEN]; 6756c92544dSBjoern A. Zeeb u8 rst_ba_tid; 6766c92544dSBjoern A. Zeeb u8 rst_ba_sel; 6776c92544dSBjoern A. Zeeb u8 rst_ba_sb; 6786c92544dSBjoern A. Zeeb u8 band_idx; 6796c92544dSBjoern A. Zeeb u8 rsv1[4]; 6806c92544dSBjoern A. Zeeb } __packed; 6816c92544dSBjoern A. Zeeb 6826c92544dSBjoern A. Zeeb struct wtbl_smps { 6836c92544dSBjoern A. Zeeb __le16 tag; 6846c92544dSBjoern A. Zeeb __le16 len; 6856c92544dSBjoern A. Zeeb u8 smps; 6866c92544dSBjoern A. Zeeb u8 rsv[3]; 6876c92544dSBjoern A. Zeeb } __packed; 6886c92544dSBjoern A. Zeeb 6896c92544dSBjoern A. Zeeb /* mt7615 only */ 6906c92544dSBjoern A. Zeeb 6916c92544dSBjoern A. Zeeb struct wtbl_bf { 6926c92544dSBjoern A. Zeeb __le16 tag; 6936c92544dSBjoern A. Zeeb __le16 len; 6946c92544dSBjoern A. Zeeb u8 ibf; 6956c92544dSBjoern A. Zeeb u8 ebf; 6966c92544dSBjoern A. Zeeb u8 ibf_vht; 6976c92544dSBjoern A. Zeeb u8 ebf_vht; 6986c92544dSBjoern A. Zeeb u8 gid; 6996c92544dSBjoern A. Zeeb u8 pfmu_idx; 7006c92544dSBjoern A. Zeeb u8 rsv[2]; 7016c92544dSBjoern A. Zeeb } __packed; 7026c92544dSBjoern A. Zeeb 7036c92544dSBjoern A. Zeeb struct wtbl_pn { 7046c92544dSBjoern A. Zeeb __le16 tag; 7056c92544dSBjoern A. Zeeb __le16 len; 7066c92544dSBjoern A. Zeeb u8 pn[6]; 7076c92544dSBjoern A. Zeeb u8 rsv[2]; 7086c92544dSBjoern A. Zeeb } __packed; 7096c92544dSBjoern A. Zeeb 7106c92544dSBjoern A. Zeeb struct wtbl_spe { 7116c92544dSBjoern A. Zeeb __le16 tag; 7126c92544dSBjoern A. Zeeb __le16 len; 7136c92544dSBjoern A. Zeeb u8 spe_idx; 7146c92544dSBjoern A. Zeeb u8 rsv[3]; 7156c92544dSBjoern A. Zeeb } __packed; 7166c92544dSBjoern A. Zeeb 7176c92544dSBjoern A. Zeeb struct wtbl_raw { 7186c92544dSBjoern A. Zeeb __le16 tag; 7196c92544dSBjoern A. Zeeb __le16 len; 7206c92544dSBjoern A. Zeeb u8 wtbl_idx; 7216c92544dSBjoern A. Zeeb u8 dw; 7226c92544dSBjoern A. Zeeb u8 rsv[2]; 7236c92544dSBjoern A. Zeeb __le32 msk; 7246c92544dSBjoern A. Zeeb __le32 val; 7256c92544dSBjoern A. Zeeb } __packed; 7266c92544dSBjoern A. Zeeb 7276c92544dSBjoern A. Zeeb #define MT76_CONNAC_WTBL_UPDATE_MAX_SIZE (sizeof(struct wtbl_req_hdr) + \ 7286c92544dSBjoern A. Zeeb sizeof(struct wtbl_generic) + \ 7296c92544dSBjoern A. Zeeb sizeof(struct wtbl_rx) + \ 7306c92544dSBjoern A. Zeeb sizeof(struct wtbl_ht) + \ 7316c92544dSBjoern A. Zeeb sizeof(struct wtbl_vht) + \ 7326c92544dSBjoern A. Zeeb sizeof(struct wtbl_tx_ps) + \ 7336c92544dSBjoern A. Zeeb sizeof(struct wtbl_hdr_trans) +\ 7346c92544dSBjoern A. Zeeb sizeof(struct wtbl_ba) + \ 7356c92544dSBjoern A. Zeeb sizeof(struct wtbl_bf) + \ 7366c92544dSBjoern A. Zeeb sizeof(struct wtbl_smps) + \ 7376c92544dSBjoern A. Zeeb sizeof(struct wtbl_pn) + \ 7386c92544dSBjoern A. Zeeb sizeof(struct wtbl_spe)) 7396c92544dSBjoern A. Zeeb 7406c92544dSBjoern A. Zeeb #define MT76_CONNAC_STA_UPDATE_MAX_SIZE (sizeof(struct sta_req_hdr) + \ 7416c92544dSBjoern A. Zeeb sizeof(struct sta_rec_basic) + \ 7426c92544dSBjoern A. Zeeb sizeof(struct sta_rec_bf) + \ 7436c92544dSBjoern A. Zeeb sizeof(struct sta_rec_ht) + \ 7446c92544dSBjoern A. Zeeb sizeof(struct sta_rec_he) + \ 7456c92544dSBjoern A. Zeeb sizeof(struct sta_rec_ba) + \ 7466c92544dSBjoern A. Zeeb sizeof(struct sta_rec_vht) + \ 7476c92544dSBjoern A. Zeeb sizeof(struct sta_rec_uapsd) + \ 7486c92544dSBjoern A. Zeeb sizeof(struct sta_rec_amsdu) + \ 7496c92544dSBjoern A. Zeeb sizeof(struct sta_rec_muru) + \ 7506c92544dSBjoern A. Zeeb sizeof(struct sta_rec_bfee) + \ 7516c92544dSBjoern A. Zeeb sizeof(struct sta_rec_ra) + \ 7526c92544dSBjoern A. Zeeb sizeof(struct sta_rec_sec) + \ 7536c92544dSBjoern A. Zeeb sizeof(struct sta_rec_ra_fixed) + \ 7546c92544dSBjoern A. Zeeb sizeof(struct sta_rec_he_6g_capa) + \ 7556c92544dSBjoern A. Zeeb sizeof(struct tlv) + \ 7566c92544dSBjoern A. Zeeb MT76_CONNAC_WTBL_UPDATE_MAX_SIZE) 7576c92544dSBjoern A. Zeeb 7586c92544dSBjoern A. Zeeb enum { 7596c92544dSBjoern A. Zeeb STA_REC_BASIC, 7606c92544dSBjoern A. Zeeb STA_REC_RA, 7616c92544dSBjoern A. Zeeb STA_REC_RA_CMM_INFO, 7626c92544dSBjoern A. Zeeb STA_REC_RA_UPDATE, 7636c92544dSBjoern A. Zeeb STA_REC_BF, 7646c92544dSBjoern A. Zeeb STA_REC_AMSDU, 7656c92544dSBjoern A. Zeeb STA_REC_BA, 7666c92544dSBjoern A. Zeeb STA_REC_STATE, 7676c92544dSBjoern A. Zeeb STA_REC_TX_PROC, /* for hdr trans and CSO in CR4 */ 7686c92544dSBjoern A. Zeeb STA_REC_HT, 7696c92544dSBjoern A. Zeeb STA_REC_VHT, 7706c92544dSBjoern A. Zeeb STA_REC_APPS, 7716c92544dSBjoern A. Zeeb STA_REC_KEY, 7726c92544dSBjoern A. Zeeb STA_REC_WTBL, 7736c92544dSBjoern A. Zeeb STA_REC_HE, 7746c92544dSBjoern A. Zeeb STA_REC_HW_AMSDU, 7756c92544dSBjoern A. Zeeb STA_REC_WTBL_AADOM, 7766c92544dSBjoern A. Zeeb STA_REC_KEY_V2, 7776c92544dSBjoern A. Zeeb STA_REC_MURU, 7786c92544dSBjoern A. Zeeb STA_REC_MUEDCA, 7796c92544dSBjoern A. Zeeb STA_REC_BFEE, 7806c92544dSBjoern A. Zeeb STA_REC_PHY = 0x15, 7816c92544dSBjoern A. Zeeb STA_REC_HE_6G = 0x17, 7826c92544dSBjoern A. Zeeb STA_REC_MAX_NUM 7836c92544dSBjoern A. Zeeb }; 7846c92544dSBjoern A. Zeeb 7856c92544dSBjoern A. Zeeb enum { 7866c92544dSBjoern A. Zeeb WTBL_GENERIC, 7876c92544dSBjoern A. Zeeb WTBL_RX, 7886c92544dSBjoern A. Zeeb WTBL_HT, 7896c92544dSBjoern A. Zeeb WTBL_VHT, 7906c92544dSBjoern A. Zeeb WTBL_PEER_PS, /* not used */ 7916c92544dSBjoern A. Zeeb WTBL_TX_PS, 7926c92544dSBjoern A. Zeeb WTBL_HDR_TRANS, 7936c92544dSBjoern A. Zeeb WTBL_SEC_KEY, 7946c92544dSBjoern A. Zeeb WTBL_BA, 7956c92544dSBjoern A. Zeeb WTBL_RDG, /* obsoleted */ 7966c92544dSBjoern A. Zeeb WTBL_PROTECT, /* not used */ 7976c92544dSBjoern A. Zeeb WTBL_CLEAR, /* not used */ 7986c92544dSBjoern A. Zeeb WTBL_BF, 7996c92544dSBjoern A. Zeeb WTBL_SMPS, 8006c92544dSBjoern A. Zeeb WTBL_RAW_DATA, /* debug only */ 8016c92544dSBjoern A. Zeeb WTBL_PN, 8026c92544dSBjoern A. Zeeb WTBL_SPE, 8036c92544dSBjoern A. Zeeb WTBL_MAX_NUM 8046c92544dSBjoern A. Zeeb }; 8056c92544dSBjoern A. Zeeb 8066c92544dSBjoern A. Zeeb #define STA_TYPE_STA BIT(0) 8076c92544dSBjoern A. Zeeb #define STA_TYPE_AP BIT(1) 8086c92544dSBjoern A. Zeeb #define STA_TYPE_ADHOC BIT(2) 8096c92544dSBjoern A. Zeeb #define STA_TYPE_WDS BIT(4) 8106c92544dSBjoern A. Zeeb #define STA_TYPE_BC BIT(5) 8116c92544dSBjoern A. Zeeb 8126c92544dSBjoern A. Zeeb #define NETWORK_INFRA BIT(16) 8136c92544dSBjoern A. Zeeb #define NETWORK_P2P BIT(17) 8146c92544dSBjoern A. Zeeb #define NETWORK_IBSS BIT(18) 8156c92544dSBjoern A. Zeeb #define NETWORK_WDS BIT(21) 8166c92544dSBjoern A. Zeeb 8176c92544dSBjoern A. Zeeb #define SCAN_FUNC_RANDOM_MAC BIT(0) 8186c92544dSBjoern A. Zeeb #define SCAN_FUNC_SPLIT_SCAN BIT(5) 8196c92544dSBjoern A. Zeeb 8206c92544dSBjoern A. Zeeb #define CONNECTION_INFRA_STA (STA_TYPE_STA | NETWORK_INFRA) 8216c92544dSBjoern A. Zeeb #define CONNECTION_INFRA_AP (STA_TYPE_AP | NETWORK_INFRA) 8226c92544dSBjoern A. Zeeb #define CONNECTION_P2P_GC (STA_TYPE_STA | NETWORK_P2P) 8236c92544dSBjoern A. Zeeb #define CONNECTION_P2P_GO (STA_TYPE_AP | NETWORK_P2P) 8246c92544dSBjoern A. Zeeb #define CONNECTION_IBSS_ADHOC (STA_TYPE_ADHOC | NETWORK_IBSS) 8256c92544dSBjoern A. Zeeb #define CONNECTION_WDS (STA_TYPE_WDS | NETWORK_WDS) 8266c92544dSBjoern A. Zeeb #define CONNECTION_INFRA_BC (STA_TYPE_BC | NETWORK_INFRA) 8276c92544dSBjoern A. Zeeb 8286c92544dSBjoern A. Zeeb #define CONN_STATE_DISCONNECT 0 8296c92544dSBjoern A. Zeeb #define CONN_STATE_CONNECT 1 8306c92544dSBjoern A. Zeeb #define CONN_STATE_PORT_SECURE 2 8316c92544dSBjoern A. Zeeb 8326c92544dSBjoern A. Zeeb /* HE MAC */ 8336c92544dSBjoern A. Zeeb #define STA_REC_HE_CAP_HTC BIT(0) 8346c92544dSBjoern A. Zeeb #define STA_REC_HE_CAP_BQR BIT(1) 8356c92544dSBjoern A. Zeeb #define STA_REC_HE_CAP_BSR BIT(2) 8366c92544dSBjoern A. Zeeb #define STA_REC_HE_CAP_OM BIT(3) 8376c92544dSBjoern A. Zeeb #define STA_REC_HE_CAP_AMSDU_IN_AMPDU BIT(4) 8386c92544dSBjoern A. Zeeb /* HE PHY */ 8396c92544dSBjoern A. Zeeb #define STA_REC_HE_CAP_DUAL_BAND BIT(5) 8406c92544dSBjoern A. Zeeb #define STA_REC_HE_CAP_LDPC BIT(6) 8416c92544dSBjoern A. Zeeb #define STA_REC_HE_CAP_TRIG_CQI_FK BIT(7) 8426c92544dSBjoern A. Zeeb #define STA_REC_HE_CAP_PARTIAL_BW_EXT_RANGE BIT(8) 8436c92544dSBjoern A. Zeeb /* STBC */ 8446c92544dSBjoern A. Zeeb #define STA_REC_HE_CAP_LE_EQ_80M_TX_STBC BIT(9) 8456c92544dSBjoern A. Zeeb #define STA_REC_HE_CAP_LE_EQ_80M_RX_STBC BIT(10) 8466c92544dSBjoern A. Zeeb #define STA_REC_HE_CAP_GT_80M_TX_STBC BIT(11) 8476c92544dSBjoern A. Zeeb #define STA_REC_HE_CAP_GT_80M_RX_STBC BIT(12) 8486c92544dSBjoern A. Zeeb /* GI */ 8496c92544dSBjoern A. Zeeb #define STA_REC_HE_CAP_SU_PPDU_1LTF_8US_GI BIT(13) 8506c92544dSBjoern A. Zeeb #define STA_REC_HE_CAP_SU_MU_PPDU_4LTF_8US_GI BIT(14) 8516c92544dSBjoern A. Zeeb #define STA_REC_HE_CAP_ER_SU_PPDU_1LTF_8US_GI BIT(15) 8526c92544dSBjoern A. Zeeb #define STA_REC_HE_CAP_ER_SU_PPDU_4LTF_8US_GI BIT(16) 8536c92544dSBjoern A. Zeeb #define STA_REC_HE_CAP_NDP_4LTF_3DOT2MS_GI BIT(17) 8546c92544dSBjoern A. Zeeb /* 242 TONE */ 8556c92544dSBjoern A. Zeeb #define STA_REC_HE_CAP_BW20_RU242_SUPPORT BIT(18) 8566c92544dSBjoern A. Zeeb #define STA_REC_HE_CAP_TX_1024QAM_UNDER_RU242 BIT(19) 8576c92544dSBjoern A. Zeeb #define STA_REC_HE_CAP_RX_1024QAM_UNDER_RU242 BIT(20) 8586c92544dSBjoern A. Zeeb 8596c92544dSBjoern A. Zeeb #define PHY_MODE_A BIT(0) 8606c92544dSBjoern A. Zeeb #define PHY_MODE_B BIT(1) 8616c92544dSBjoern A. Zeeb #define PHY_MODE_G BIT(2) 8626c92544dSBjoern A. Zeeb #define PHY_MODE_GN BIT(3) 8636c92544dSBjoern A. Zeeb #define PHY_MODE_AN BIT(4) 8646c92544dSBjoern A. Zeeb #define PHY_MODE_AC BIT(5) 8656c92544dSBjoern A. Zeeb #define PHY_MODE_AX_24G BIT(6) 8666c92544dSBjoern A. Zeeb #define PHY_MODE_AX_5G BIT(7) 8676c92544dSBjoern A. Zeeb 8686c92544dSBjoern A. Zeeb #define PHY_MODE_AX_6G BIT(0) /* phymode_ext */ 8696c92544dSBjoern A. Zeeb 8706c92544dSBjoern A. Zeeb #define MODE_CCK BIT(0) 8716c92544dSBjoern A. Zeeb #define MODE_OFDM BIT(1) 8726c92544dSBjoern A. Zeeb #define MODE_HT BIT(2) 8736c92544dSBjoern A. Zeeb #define MODE_VHT BIT(3) 8746c92544dSBjoern A. Zeeb #define MODE_HE BIT(4) 8756c92544dSBjoern A. Zeeb 8766c92544dSBjoern A. Zeeb #define STA_CAP_WMM BIT(0) 8776c92544dSBjoern A. Zeeb #define STA_CAP_SGI_20 BIT(4) 8786c92544dSBjoern A. Zeeb #define STA_CAP_SGI_40 BIT(5) 8796c92544dSBjoern A. Zeeb #define STA_CAP_TX_STBC BIT(6) 8806c92544dSBjoern A. Zeeb #define STA_CAP_RX_STBC BIT(7) 8816c92544dSBjoern A. Zeeb #define STA_CAP_VHT_SGI_80 BIT(16) 8826c92544dSBjoern A. Zeeb #define STA_CAP_VHT_SGI_160 BIT(17) 8836c92544dSBjoern A. Zeeb #define STA_CAP_VHT_TX_STBC BIT(18) 8846c92544dSBjoern A. Zeeb #define STA_CAP_VHT_RX_STBC BIT(19) 8856c92544dSBjoern A. Zeeb #define STA_CAP_VHT_LDPC BIT(23) 8866c92544dSBjoern A. Zeeb #define STA_CAP_LDPC BIT(24) 8876c92544dSBjoern A. Zeeb #define STA_CAP_HT BIT(26) 8886c92544dSBjoern A. Zeeb #define STA_CAP_VHT BIT(27) 8896c92544dSBjoern A. Zeeb #define STA_CAP_HE BIT(28) 8906c92544dSBjoern A. Zeeb 8916c92544dSBjoern A. Zeeb enum { 8926c92544dSBjoern A. Zeeb PHY_TYPE_HR_DSSS_INDEX = 0, 8936c92544dSBjoern A. Zeeb PHY_TYPE_ERP_INDEX, 8946c92544dSBjoern A. Zeeb PHY_TYPE_ERP_P2P_INDEX, 8956c92544dSBjoern A. Zeeb PHY_TYPE_OFDM_INDEX, 8966c92544dSBjoern A. Zeeb PHY_TYPE_HT_INDEX, 8976c92544dSBjoern A. Zeeb PHY_TYPE_VHT_INDEX, 8986c92544dSBjoern A. Zeeb PHY_TYPE_HE_INDEX, 8996c92544dSBjoern A. Zeeb PHY_TYPE_INDEX_NUM 9006c92544dSBjoern A. Zeeb }; 9016c92544dSBjoern A. Zeeb 9026c92544dSBjoern A. Zeeb #define PHY_TYPE_BIT_HR_DSSS BIT(PHY_TYPE_HR_DSSS_INDEX) 9036c92544dSBjoern A. Zeeb #define PHY_TYPE_BIT_ERP BIT(PHY_TYPE_ERP_INDEX) 9046c92544dSBjoern A. Zeeb #define PHY_TYPE_BIT_OFDM BIT(PHY_TYPE_OFDM_INDEX) 9056c92544dSBjoern A. Zeeb #define PHY_TYPE_BIT_HT BIT(PHY_TYPE_HT_INDEX) 9066c92544dSBjoern A. Zeeb #define PHY_TYPE_BIT_VHT BIT(PHY_TYPE_VHT_INDEX) 9076c92544dSBjoern A. Zeeb #define PHY_TYPE_BIT_HE BIT(PHY_TYPE_HE_INDEX) 9086c92544dSBjoern A. Zeeb 9096c92544dSBjoern A. Zeeb #define MT_WTBL_RATE_TX_MODE GENMASK(9, 6) 9106c92544dSBjoern A. Zeeb #define MT_WTBL_RATE_MCS GENMASK(5, 0) 9116c92544dSBjoern A. Zeeb #define MT_WTBL_RATE_NSS GENMASK(12, 10) 9126c92544dSBjoern A. Zeeb #define MT_WTBL_RATE_HE_GI GENMASK(7, 4) 9136c92544dSBjoern A. Zeeb #define MT_WTBL_RATE_GI GENMASK(3, 0) 9146c92544dSBjoern A. Zeeb 9156c92544dSBjoern A. Zeeb #define MT_WTBL_W5_CHANGE_BW_RATE GENMASK(7, 5) 9166c92544dSBjoern A. Zeeb #define MT_WTBL_W5_SHORT_GI_20 BIT(8) 9176c92544dSBjoern A. Zeeb #define MT_WTBL_W5_SHORT_GI_40 BIT(9) 9186c92544dSBjoern A. Zeeb #define MT_WTBL_W5_SHORT_GI_80 BIT(10) 9196c92544dSBjoern A. Zeeb #define MT_WTBL_W5_SHORT_GI_160 BIT(11) 9206c92544dSBjoern A. Zeeb #define MT_WTBL_W5_BW_CAP GENMASK(13, 12) 9216c92544dSBjoern A. Zeeb #define MT_WTBL_W5_MPDU_FAIL_COUNT GENMASK(25, 23) 9226c92544dSBjoern A. Zeeb #define MT_WTBL_W5_MPDU_OK_COUNT GENMASK(28, 26) 9236c92544dSBjoern A. Zeeb #define MT_WTBL_W5_RATE_IDX GENMASK(31, 29) 9246c92544dSBjoern A. Zeeb 9256c92544dSBjoern A. Zeeb enum { 9266c92544dSBjoern A. Zeeb WTBL_RESET_AND_SET = 1, 9276c92544dSBjoern A. Zeeb WTBL_SET, 9286c92544dSBjoern A. Zeeb WTBL_QUERY, 9296c92544dSBjoern A. Zeeb WTBL_RESET_ALL 9306c92544dSBjoern A. Zeeb }; 9316c92544dSBjoern A. Zeeb 9326c92544dSBjoern A. Zeeb enum { 9336c92544dSBjoern A. Zeeb MT_BA_TYPE_INVALID, 9346c92544dSBjoern A. Zeeb MT_BA_TYPE_ORIGINATOR, 9356c92544dSBjoern A. Zeeb MT_BA_TYPE_RECIPIENT 9366c92544dSBjoern A. Zeeb }; 9376c92544dSBjoern A. Zeeb 9386c92544dSBjoern A. Zeeb enum { 9396c92544dSBjoern A. Zeeb RST_BA_MAC_TID_MATCH, 9406c92544dSBjoern A. Zeeb RST_BA_MAC_MATCH, 9416c92544dSBjoern A. Zeeb RST_BA_NO_MATCH 9426c92544dSBjoern A. Zeeb }; 9436c92544dSBjoern A. Zeeb 9446c92544dSBjoern A. Zeeb enum { 9456c92544dSBjoern A. Zeeb DEV_INFO_ACTIVE, 9466c92544dSBjoern A. Zeeb DEV_INFO_MAX_NUM 9476c92544dSBjoern A. Zeeb }; 9486c92544dSBjoern A. Zeeb 9496c92544dSBjoern A. Zeeb /* event table */ 9506c92544dSBjoern A. Zeeb enum { 9516c92544dSBjoern A. Zeeb MCU_EVENT_TARGET_ADDRESS_LEN = 0x01, 9526c92544dSBjoern A. Zeeb MCU_EVENT_FW_START = 0x01, 9536c92544dSBjoern A. Zeeb MCU_EVENT_GENERIC = 0x01, 9546c92544dSBjoern A. Zeeb MCU_EVENT_ACCESS_REG = 0x02, 9556c92544dSBjoern A. Zeeb MCU_EVENT_MT_PATCH_SEM = 0x04, 9566c92544dSBjoern A. Zeeb MCU_EVENT_REG_ACCESS = 0x05, 9576c92544dSBjoern A. Zeeb MCU_EVENT_LP_INFO = 0x07, 9586c92544dSBjoern A. Zeeb MCU_EVENT_SCAN_DONE = 0x0d, 9596c92544dSBjoern A. Zeeb MCU_EVENT_TX_DONE = 0x0f, 9606c92544dSBjoern A. Zeeb MCU_EVENT_ROC = 0x10, 9616c92544dSBjoern A. Zeeb MCU_EVENT_BSS_ABSENCE = 0x11, 9626c92544dSBjoern A. Zeeb MCU_EVENT_BSS_BEACON_LOSS = 0x13, 9636c92544dSBjoern A. Zeeb MCU_EVENT_CH_PRIVILEGE = 0x18, 9646c92544dSBjoern A. Zeeb MCU_EVENT_SCHED_SCAN_DONE = 0x23, 9656c92544dSBjoern A. Zeeb MCU_EVENT_DBG_MSG = 0x27, 9666c92544dSBjoern A. Zeeb MCU_EVENT_TXPWR = 0xd0, 9676c92544dSBjoern A. Zeeb MCU_EVENT_EXT = 0xed, 9686c92544dSBjoern A. Zeeb MCU_EVENT_RESTART_DL = 0xef, 9696c92544dSBjoern A. Zeeb MCU_EVENT_COREDUMP = 0xf0, 9706c92544dSBjoern A. Zeeb }; 9716c92544dSBjoern A. Zeeb 9726c92544dSBjoern A. Zeeb /* ext event table */ 9736c92544dSBjoern A. Zeeb enum { 9746c92544dSBjoern A. Zeeb MCU_EXT_EVENT_PS_SYNC = 0x5, 9756c92544dSBjoern A. Zeeb MCU_EXT_EVENT_FW_LOG_2_HOST = 0x13, 9766c92544dSBjoern A. Zeeb MCU_EXT_EVENT_THERMAL_PROTECT = 0x22, 9776c92544dSBjoern A. Zeeb MCU_EXT_EVENT_ASSERT_DUMP = 0x23, 9786c92544dSBjoern A. Zeeb MCU_EXT_EVENT_RDD_REPORT = 0x3a, 9796c92544dSBjoern A. Zeeb MCU_EXT_EVENT_CSA_NOTIFY = 0x4f, 9806c92544dSBjoern A. Zeeb MCU_EXT_EVENT_BCC_NOTIFY = 0x75, 9816c92544dSBjoern A. Zeeb MCU_EXT_EVENT_MURU_CTRL = 0x9f, 9826c92544dSBjoern A. Zeeb }; 9836c92544dSBjoern A. Zeeb 9846c92544dSBjoern A. Zeeb enum { 9856c92544dSBjoern A. Zeeb MCU_Q_QUERY, 9866c92544dSBjoern A. Zeeb MCU_Q_SET, 9876c92544dSBjoern A. Zeeb MCU_Q_RESERVED, 9886c92544dSBjoern A. Zeeb MCU_Q_NA 9896c92544dSBjoern A. Zeeb }; 9906c92544dSBjoern A. Zeeb 9916c92544dSBjoern A. Zeeb enum { 9926c92544dSBjoern A. Zeeb MCU_S2D_H2N, 9936c92544dSBjoern A. Zeeb MCU_S2D_C2N, 9946c92544dSBjoern A. Zeeb MCU_S2D_H2C, 9956c92544dSBjoern A. Zeeb MCU_S2D_H2CN 9966c92544dSBjoern A. Zeeb }; 9976c92544dSBjoern A. Zeeb 9986c92544dSBjoern A. Zeeb enum { 9996c92544dSBjoern A. Zeeb PATCH_NOT_DL_SEM_FAIL, 10006c92544dSBjoern A. Zeeb PATCH_IS_DL, 10016c92544dSBjoern A. Zeeb PATCH_NOT_DL_SEM_SUCCESS, 10026c92544dSBjoern A. Zeeb PATCH_REL_SEM_SUCCESS 10036c92544dSBjoern A. Zeeb }; 10046c92544dSBjoern A. Zeeb 10056c92544dSBjoern A. Zeeb enum { 10066c92544dSBjoern A. Zeeb FW_STATE_INITIAL, 10076c92544dSBjoern A. Zeeb FW_STATE_FW_DOWNLOAD, 10086c92544dSBjoern A. Zeeb FW_STATE_NORMAL_OPERATION, 10096c92544dSBjoern A. Zeeb FW_STATE_NORMAL_TRX, 10106c92544dSBjoern A. Zeeb FW_STATE_RDY = 7 10116c92544dSBjoern A. Zeeb }; 10126c92544dSBjoern A. Zeeb 10136c92544dSBjoern A. Zeeb enum { 10146c92544dSBjoern A. Zeeb CH_SWITCH_NORMAL = 0, 10156c92544dSBjoern A. Zeeb CH_SWITCH_SCAN = 3, 10166c92544dSBjoern A. Zeeb CH_SWITCH_MCC = 4, 10176c92544dSBjoern A. Zeeb CH_SWITCH_DFS = 5, 10186c92544dSBjoern A. Zeeb CH_SWITCH_BACKGROUND_SCAN_START = 6, 10196c92544dSBjoern A. Zeeb CH_SWITCH_BACKGROUND_SCAN_RUNNING = 7, 10206c92544dSBjoern A. Zeeb CH_SWITCH_BACKGROUND_SCAN_STOP = 8, 10216c92544dSBjoern A. Zeeb CH_SWITCH_SCAN_BYPASS_DPD = 9 10226c92544dSBjoern A. Zeeb }; 10236c92544dSBjoern A. Zeeb 10246c92544dSBjoern A. Zeeb enum { 10256c92544dSBjoern A. Zeeb THERMAL_SENSOR_TEMP_QUERY, 10266c92544dSBjoern A. Zeeb THERMAL_SENSOR_MANUAL_CTRL, 10276c92544dSBjoern A. Zeeb THERMAL_SENSOR_INFO_QUERY, 10286c92544dSBjoern A. Zeeb THERMAL_SENSOR_TASK_CTRL, 10296c92544dSBjoern A. Zeeb }; 10306c92544dSBjoern A. Zeeb 10316c92544dSBjoern A. Zeeb enum mcu_cipher_type { 10326c92544dSBjoern A. Zeeb MCU_CIPHER_NONE = 0, 10336c92544dSBjoern A. Zeeb MCU_CIPHER_WEP40, 10346c92544dSBjoern A. Zeeb MCU_CIPHER_WEP104, 10356c92544dSBjoern A. Zeeb MCU_CIPHER_WEP128, 10366c92544dSBjoern A. Zeeb MCU_CIPHER_TKIP, 10376c92544dSBjoern A. Zeeb MCU_CIPHER_AES_CCMP, 10386c92544dSBjoern A. Zeeb MCU_CIPHER_CCMP_256, 10396c92544dSBjoern A. Zeeb MCU_CIPHER_GCMP, 10406c92544dSBjoern A. Zeeb MCU_CIPHER_GCMP_256, 10416c92544dSBjoern A. Zeeb MCU_CIPHER_WAPI, 10426c92544dSBjoern A. Zeeb MCU_CIPHER_BIP_CMAC_128, 10436c92544dSBjoern A. Zeeb }; 10446c92544dSBjoern A. Zeeb 10456c92544dSBjoern A. Zeeb enum { 10466c92544dSBjoern A. Zeeb EE_MODE_EFUSE, 10476c92544dSBjoern A. Zeeb EE_MODE_BUFFER, 10486c92544dSBjoern A. Zeeb }; 10496c92544dSBjoern A. Zeeb 10506c92544dSBjoern A. Zeeb enum { 10516c92544dSBjoern A. Zeeb EE_FORMAT_BIN, 10526c92544dSBjoern A. Zeeb EE_FORMAT_WHOLE, 10536c92544dSBjoern A. Zeeb EE_FORMAT_MULTIPLE, 10546c92544dSBjoern A. Zeeb }; 10556c92544dSBjoern A. Zeeb 10566c92544dSBjoern A. Zeeb enum { 10576c92544dSBjoern A. Zeeb MCU_PHY_STATE_TX_RATE, 10586c92544dSBjoern A. Zeeb MCU_PHY_STATE_RX_RATE, 10596c92544dSBjoern A. Zeeb MCU_PHY_STATE_RSSI, 10606c92544dSBjoern A. Zeeb MCU_PHY_STATE_CONTENTION_RX_RATE, 10616c92544dSBjoern A. Zeeb MCU_PHY_STATE_OFDMLQ_CNINFO, 10626c92544dSBjoern A. Zeeb }; 10636c92544dSBjoern A. Zeeb 10646c92544dSBjoern A. Zeeb #define MCU_CMD_ACK BIT(0) 10656c92544dSBjoern A. Zeeb #define MCU_CMD_UNI BIT(1) 10666c92544dSBjoern A. Zeeb #define MCU_CMD_QUERY BIT(2) 10676c92544dSBjoern A. Zeeb 10686c92544dSBjoern A. Zeeb #define MCU_CMD_UNI_EXT_ACK (MCU_CMD_ACK | MCU_CMD_UNI | \ 10696c92544dSBjoern A. Zeeb MCU_CMD_QUERY) 10706c92544dSBjoern A. Zeeb 10716c92544dSBjoern A. Zeeb #define __MCU_CMD_FIELD_ID GENMASK(7, 0) 10726c92544dSBjoern A. Zeeb #define __MCU_CMD_FIELD_EXT_ID GENMASK(15, 8) 10736c92544dSBjoern A. Zeeb #define __MCU_CMD_FIELD_QUERY BIT(16) 10746c92544dSBjoern A. Zeeb #define __MCU_CMD_FIELD_UNI BIT(17) 10756c92544dSBjoern A. Zeeb #define __MCU_CMD_FIELD_CE BIT(18) 10766c92544dSBjoern A. Zeeb #define __MCU_CMD_FIELD_WA BIT(19) 10776c92544dSBjoern A. Zeeb 10786c92544dSBjoern A. Zeeb #define MCU_CMD(_t) FIELD_PREP(__MCU_CMD_FIELD_ID, \ 10796c92544dSBjoern A. Zeeb MCU_CMD_##_t) 10806c92544dSBjoern A. Zeeb #define MCU_EXT_CMD(_t) (MCU_CMD(EXT_CID) | \ 10816c92544dSBjoern A. Zeeb FIELD_PREP(__MCU_CMD_FIELD_EXT_ID, \ 10826c92544dSBjoern A. Zeeb MCU_EXT_CMD_##_t)) 10836c92544dSBjoern A. Zeeb #define MCU_EXT_QUERY(_t) (MCU_EXT_CMD(_t) | __MCU_CMD_FIELD_QUERY) 10846c92544dSBjoern A. Zeeb #define MCU_UNI_CMD(_t) (__MCU_CMD_FIELD_UNI | \ 10856c92544dSBjoern A. Zeeb FIELD_PREP(__MCU_CMD_FIELD_ID, \ 10866c92544dSBjoern A. Zeeb MCU_UNI_CMD_##_t)) 10876c92544dSBjoern A. Zeeb #define MCU_CE_CMD(_t) (__MCU_CMD_FIELD_CE | \ 10886c92544dSBjoern A. Zeeb FIELD_PREP(__MCU_CMD_FIELD_ID, \ 10896c92544dSBjoern A. Zeeb MCU_CE_CMD_##_t)) 10906c92544dSBjoern A. Zeeb #define MCU_CE_QUERY(_t) (MCU_CE_CMD(_t) | __MCU_CMD_FIELD_QUERY) 10916c92544dSBjoern A. Zeeb 10926c92544dSBjoern A. Zeeb #define MCU_WA_CMD(_t) (MCU_CMD(_t) | __MCU_CMD_FIELD_WA) 10936c92544dSBjoern A. Zeeb #define MCU_WA_EXT_CMD(_t) (MCU_EXT_CMD(_t) | __MCU_CMD_FIELD_WA) 10946c92544dSBjoern A. Zeeb #define MCU_WA_PARAM_CMD(_t) (MCU_WA_CMD(WA_PARAM) | \ 10956c92544dSBjoern A. Zeeb FIELD_PREP(__MCU_CMD_FIELD_EXT_ID, \ 10966c92544dSBjoern A. Zeeb MCU_WA_PARAM_CMD_##_t)) 10976c92544dSBjoern A. Zeeb 10986c92544dSBjoern A. Zeeb enum { 10996c92544dSBjoern A. Zeeb MCU_EXT_CMD_EFUSE_ACCESS = 0x01, 11006c92544dSBjoern A. Zeeb MCU_EXT_CMD_RF_REG_ACCESS = 0x02, 11016c92544dSBjoern A. Zeeb MCU_EXT_CMD_RF_TEST = 0x04, 11026c92544dSBjoern A. Zeeb MCU_EXT_CMD_PM_STATE_CTRL = 0x07, 11036c92544dSBjoern A. Zeeb MCU_EXT_CMD_CHANNEL_SWITCH = 0x08, 11046c92544dSBjoern A. Zeeb MCU_EXT_CMD_SET_TX_POWER_CTRL = 0x11, 11056c92544dSBjoern A. Zeeb MCU_EXT_CMD_FW_LOG_2_HOST = 0x13, 11066c92544dSBjoern A. Zeeb MCU_EXT_CMD_TXBF_ACTION = 0x1e, 11076c92544dSBjoern A. Zeeb MCU_EXT_CMD_EFUSE_BUFFER_MODE = 0x21, 11086c92544dSBjoern A. Zeeb MCU_EXT_CMD_THERMAL_PROT = 0x23, 11096c92544dSBjoern A. Zeeb MCU_EXT_CMD_STA_REC_UPDATE = 0x25, 11106c92544dSBjoern A. Zeeb MCU_EXT_CMD_BSS_INFO_UPDATE = 0x26, 11116c92544dSBjoern A. Zeeb MCU_EXT_CMD_EDCA_UPDATE = 0x27, 11126c92544dSBjoern A. Zeeb MCU_EXT_CMD_DEV_INFO_UPDATE = 0x2A, 11136c92544dSBjoern A. Zeeb MCU_EXT_CMD_THERMAL_CTRL = 0x2c, 11146c92544dSBjoern A. Zeeb MCU_EXT_CMD_WTBL_UPDATE = 0x32, 11156c92544dSBjoern A. Zeeb MCU_EXT_CMD_SET_DRR_CTRL = 0x36, 11166c92544dSBjoern A. Zeeb MCU_EXT_CMD_SET_RDD_CTRL = 0x3a, 11176c92544dSBjoern A. Zeeb MCU_EXT_CMD_ATE_CTRL = 0x3d, 11186c92544dSBjoern A. Zeeb MCU_EXT_CMD_PROTECT_CTRL = 0x3e, 11196c92544dSBjoern A. Zeeb MCU_EXT_CMD_DBDC_CTRL = 0x45, 11206c92544dSBjoern A. Zeeb MCU_EXT_CMD_MAC_INIT_CTRL = 0x46, 11216c92544dSBjoern A. Zeeb MCU_EXT_CMD_RX_HDR_TRANS = 0x47, 11226c92544dSBjoern A. Zeeb MCU_EXT_CMD_MUAR_UPDATE = 0x48, 11236c92544dSBjoern A. Zeeb MCU_EXT_CMD_BCN_OFFLOAD = 0x49, 11246c92544dSBjoern A. Zeeb MCU_EXT_CMD_RX_AIRTIME_CTRL = 0x4a, 11256c92544dSBjoern A. Zeeb MCU_EXT_CMD_SET_RX_PATH = 0x4e, 11266c92544dSBjoern A. Zeeb MCU_EXT_CMD_EFUSE_FREE_BLOCK = 0x4f, 11276c92544dSBjoern A. Zeeb MCU_EXT_CMD_TX_POWER_FEATURE_CTRL = 0x58, 11286c92544dSBjoern A. Zeeb MCU_EXT_CMD_RXDCOC_CAL = 0x59, 11296c92544dSBjoern A. Zeeb MCU_EXT_CMD_GET_MIB_INFO = 0x5a, 11306c92544dSBjoern A. Zeeb MCU_EXT_CMD_TXDPD_CAL = 0x60, 11316c92544dSBjoern A. Zeeb MCU_EXT_CMD_CAL_CACHE = 0x67, 11326c92544dSBjoern A. Zeeb MCU_EXT_CMD_SET_RADAR_TH = 0x7c, 11336c92544dSBjoern A. Zeeb MCU_EXT_CMD_SET_RDD_PATTERN = 0x7d, 11346c92544dSBjoern A. Zeeb MCU_EXT_CMD_MWDS_SUPPORT = 0x80, 11356c92544dSBjoern A. Zeeb MCU_EXT_CMD_SET_SER_TRIGGER = 0x81, 11366c92544dSBjoern A. Zeeb MCU_EXT_CMD_TWT_AGRT_UPDATE = 0x94, 11376c92544dSBjoern A. Zeeb MCU_EXT_CMD_FW_DBG_CTRL = 0x95, 11386c92544dSBjoern A. Zeeb MCU_EXT_CMD_OFFCH_SCAN_CTRL = 0x9a, 11396c92544dSBjoern A. Zeeb MCU_EXT_CMD_SET_RDD_TH = 0x9d, 11406c92544dSBjoern A. Zeeb MCU_EXT_CMD_MURU_CTRL = 0x9f, 11416c92544dSBjoern A. Zeeb MCU_EXT_CMD_SET_SPR = 0xa8, 11426c92544dSBjoern A. Zeeb MCU_EXT_CMD_GROUP_PRE_CAL_INFO = 0xab, 11436c92544dSBjoern A. Zeeb MCU_EXT_CMD_DPD_PRE_CAL_INFO = 0xac, 11446c92544dSBjoern A. Zeeb MCU_EXT_CMD_PHY_STAT_INFO = 0xad, 11456c92544dSBjoern A. Zeeb }; 11466c92544dSBjoern A. Zeeb 11476c92544dSBjoern A. Zeeb enum { 11486c92544dSBjoern A. Zeeb MCU_UNI_CMD_DEV_INFO_UPDATE = 0x01, 11496c92544dSBjoern A. Zeeb MCU_UNI_CMD_BSS_INFO_UPDATE = 0x02, 11506c92544dSBjoern A. Zeeb MCU_UNI_CMD_STA_REC_UPDATE = 0x03, 11516c92544dSBjoern A. Zeeb MCU_UNI_CMD_SUSPEND = 0x05, 11526c92544dSBjoern A. Zeeb MCU_UNI_CMD_OFFLOAD = 0x06, 11536c92544dSBjoern A. Zeeb MCU_UNI_CMD_HIF_CTRL = 0x07, 11546c92544dSBjoern A. Zeeb MCU_UNI_CMD_SNIFFER = 0x24, 11556c92544dSBjoern A. Zeeb }; 11566c92544dSBjoern A. Zeeb 11576c92544dSBjoern A. Zeeb enum { 11586c92544dSBjoern A. Zeeb MCU_CMD_TARGET_ADDRESS_LEN_REQ = 0x01, 11596c92544dSBjoern A. Zeeb MCU_CMD_FW_START_REQ = 0x02, 11606c92544dSBjoern A. Zeeb MCU_CMD_INIT_ACCESS_REG = 0x3, 11616c92544dSBjoern A. Zeeb MCU_CMD_NIC_POWER_CTRL = 0x4, 11626c92544dSBjoern A. Zeeb MCU_CMD_PATCH_START_REQ = 0x05, 11636c92544dSBjoern A. Zeeb MCU_CMD_PATCH_FINISH_REQ = 0x07, 11646c92544dSBjoern A. Zeeb MCU_CMD_PATCH_SEM_CONTROL = 0x10, 11656c92544dSBjoern A. Zeeb MCU_CMD_WA_PARAM = 0xc4, 11666c92544dSBjoern A. Zeeb MCU_CMD_EXT_CID = 0xed, 11676c92544dSBjoern A. Zeeb MCU_CMD_FW_SCATTER = 0xee, 11686c92544dSBjoern A. Zeeb MCU_CMD_RESTART_DL_REQ = 0xef, 11696c92544dSBjoern A. Zeeb }; 11706c92544dSBjoern A. Zeeb 11716c92544dSBjoern A. Zeeb /* offload mcu commands */ 11726c92544dSBjoern A. Zeeb enum { 11736c92544dSBjoern A. Zeeb MCU_CE_CMD_TEST_CTRL = 0x01, 11746c92544dSBjoern A. Zeeb MCU_CE_CMD_START_HW_SCAN = 0x03, 11756c92544dSBjoern A. Zeeb MCU_CE_CMD_SET_PS_PROFILE = 0x05, 11766c92544dSBjoern A. Zeeb MCU_CE_CMD_SET_CHAN_DOMAIN = 0x0f, 11776c92544dSBjoern A. Zeeb MCU_CE_CMD_SET_BSS_CONNECTED = 0x16, 11786c92544dSBjoern A. Zeeb MCU_CE_CMD_SET_BSS_ABORT = 0x17, 11796c92544dSBjoern A. Zeeb MCU_CE_CMD_CANCEL_HW_SCAN = 0x1b, 11806c92544dSBjoern A. Zeeb MCU_CE_CMD_SET_ROC = 0x1c, 11816c92544dSBjoern A. Zeeb MCU_CE_CMD_SET_EDCA_PARMS = 0x1d, 11826c92544dSBjoern A. Zeeb MCU_CE_CMD_SET_P2P_OPPPS = 0x33, 11836c92544dSBjoern A. Zeeb MCU_CE_CMD_SET_CLC = 0x5c, 11846c92544dSBjoern A. Zeeb MCU_CE_CMD_SET_RATE_TX_POWER = 0x5d, 11856c92544dSBjoern A. Zeeb MCU_CE_CMD_SCHED_SCAN_ENABLE = 0x61, 11866c92544dSBjoern A. Zeeb MCU_CE_CMD_SCHED_SCAN_REQ = 0x62, 11876c92544dSBjoern A. Zeeb MCU_CE_CMD_GET_NIC_CAPAB = 0x8a, 11886c92544dSBjoern A. Zeeb MCU_CE_CMD_SET_MU_EDCA_PARMS = 0xb0, 11896c92544dSBjoern A. Zeeb MCU_CE_CMD_REG_WRITE = 0xc0, 11906c92544dSBjoern A. Zeeb MCU_CE_CMD_REG_READ = 0xc0, 11916c92544dSBjoern A. Zeeb MCU_CE_CMD_CHIP_CONFIG = 0xca, 11926c92544dSBjoern A. Zeeb MCU_CE_CMD_FWLOG_2_HOST = 0xc5, 11936c92544dSBjoern A. Zeeb MCU_CE_CMD_GET_WTBL = 0xcd, 11946c92544dSBjoern A. Zeeb MCU_CE_CMD_GET_TXPWR = 0xd0, 11956c92544dSBjoern A. Zeeb }; 11966c92544dSBjoern A. Zeeb 11976c92544dSBjoern A. Zeeb enum { 11986c92544dSBjoern A. Zeeb PATCH_SEM_RELEASE, 11996c92544dSBjoern A. Zeeb PATCH_SEM_GET 12006c92544dSBjoern A. Zeeb }; 12016c92544dSBjoern A. Zeeb 12026c92544dSBjoern A. Zeeb enum { 12036c92544dSBjoern A. Zeeb UNI_BSS_INFO_BASIC = 0, 12046c92544dSBjoern A. Zeeb UNI_BSS_INFO_RLM = 2, 12056c92544dSBjoern A. Zeeb UNI_BSS_INFO_BSS_COLOR = 4, 12066c92544dSBjoern A. Zeeb UNI_BSS_INFO_HE_BASIC = 5, 12076c92544dSBjoern A. Zeeb UNI_BSS_INFO_BCN_CONTENT = 7, 12086c92544dSBjoern A. Zeeb UNI_BSS_INFO_QBSS = 15, 12096c92544dSBjoern A. Zeeb UNI_BSS_INFO_UAPSD = 19, 12106c92544dSBjoern A. Zeeb UNI_BSS_INFO_PS = 21, 12116c92544dSBjoern A. Zeeb UNI_BSS_INFO_BCNFT = 22, 12126c92544dSBjoern A. Zeeb }; 12136c92544dSBjoern A. Zeeb 12146c92544dSBjoern A. Zeeb enum { 12156c92544dSBjoern A. Zeeb UNI_OFFLOAD_OFFLOAD_ARP, 12166c92544dSBjoern A. Zeeb UNI_OFFLOAD_OFFLOAD_ND, 12176c92544dSBjoern A. Zeeb UNI_OFFLOAD_OFFLOAD_GTK_REKEY, 12186c92544dSBjoern A. Zeeb UNI_OFFLOAD_OFFLOAD_BMC_RPY_DETECT, 12196c92544dSBjoern A. Zeeb }; 12206c92544dSBjoern A. Zeeb 12216c92544dSBjoern A. Zeeb enum { 12226c92544dSBjoern A. Zeeb MT_NIC_CAP_TX_RESOURCE, 12236c92544dSBjoern A. Zeeb MT_NIC_CAP_TX_EFUSE_ADDR, 12246c92544dSBjoern A. Zeeb MT_NIC_CAP_COEX, 12256c92544dSBjoern A. Zeeb MT_NIC_CAP_SINGLE_SKU, 12266c92544dSBjoern A. Zeeb MT_NIC_CAP_CSUM_OFFLOAD, 12276c92544dSBjoern A. Zeeb MT_NIC_CAP_HW_VER, 12286c92544dSBjoern A. Zeeb MT_NIC_CAP_SW_VER, 12296c92544dSBjoern A. Zeeb MT_NIC_CAP_MAC_ADDR, 12306c92544dSBjoern A. Zeeb MT_NIC_CAP_PHY, 12316c92544dSBjoern A. Zeeb MT_NIC_CAP_MAC, 12326c92544dSBjoern A. Zeeb MT_NIC_CAP_FRAME_BUF, 12336c92544dSBjoern A. Zeeb MT_NIC_CAP_BEAM_FORM, 12346c92544dSBjoern A. Zeeb MT_NIC_CAP_LOCATION, 12356c92544dSBjoern A. Zeeb MT_NIC_CAP_MUMIMO, 12366c92544dSBjoern A. Zeeb MT_NIC_CAP_BUFFER_MODE_INFO, 12376c92544dSBjoern A. Zeeb MT_NIC_CAP_HW_ADIE_VERSION = 0x14, 12386c92544dSBjoern A. Zeeb MT_NIC_CAP_ANTSWP = 0x16, 12396c92544dSBjoern A. Zeeb MT_NIC_CAP_WFDMA_REALLOC, 12406c92544dSBjoern A. Zeeb MT_NIC_CAP_6G, 12416c92544dSBjoern A. Zeeb }; 12426c92544dSBjoern A. Zeeb 12436c92544dSBjoern A. Zeeb #define UNI_WOW_DETECT_TYPE_MAGIC BIT(0) 12446c92544dSBjoern A. Zeeb #define UNI_WOW_DETECT_TYPE_ANY BIT(1) 12456c92544dSBjoern A. Zeeb #define UNI_WOW_DETECT_TYPE_DISCONNECT BIT(2) 12466c92544dSBjoern A. Zeeb #define UNI_WOW_DETECT_TYPE_GTK_REKEY_FAIL BIT(3) 12476c92544dSBjoern A. Zeeb #define UNI_WOW_DETECT_TYPE_BCN_LOST BIT(4) 12486c92544dSBjoern A. Zeeb #define UNI_WOW_DETECT_TYPE_SCH_SCAN_HIT BIT(5) 12496c92544dSBjoern A. Zeeb #define UNI_WOW_DETECT_TYPE_BITMAP BIT(6) 12506c92544dSBjoern A. Zeeb 12516c92544dSBjoern A. Zeeb enum { 12526c92544dSBjoern A. Zeeb UNI_SUSPEND_MODE_SETTING, 12536c92544dSBjoern A. Zeeb UNI_SUSPEND_WOW_CTRL, 12546c92544dSBjoern A. Zeeb UNI_SUSPEND_WOW_GPIO_PARAM, 12556c92544dSBjoern A. Zeeb UNI_SUSPEND_WOW_WAKEUP_PORT, 12566c92544dSBjoern A. Zeeb UNI_SUSPEND_WOW_PATTERN, 12576c92544dSBjoern A. Zeeb }; 12586c92544dSBjoern A. Zeeb 12596c92544dSBjoern A. Zeeb enum { 12606c92544dSBjoern A. Zeeb WOW_USB = 1, 12616c92544dSBjoern A. Zeeb WOW_PCIE = 2, 12626c92544dSBjoern A. Zeeb WOW_GPIO = 3, 12636c92544dSBjoern A. Zeeb }; 12646c92544dSBjoern A. Zeeb 12656c92544dSBjoern A. Zeeb struct mt76_connac_bss_basic_tlv { 12666c92544dSBjoern A. Zeeb __le16 tag; 12676c92544dSBjoern A. Zeeb __le16 len; 12686c92544dSBjoern A. Zeeb u8 active; 12696c92544dSBjoern A. Zeeb u8 omac_idx; 12706c92544dSBjoern A. Zeeb u8 hw_bss_idx; 12716c92544dSBjoern A. Zeeb u8 band_idx; 12726c92544dSBjoern A. Zeeb __le32 conn_type; 12736c92544dSBjoern A. Zeeb u8 conn_state; 12746c92544dSBjoern A. Zeeb u8 wmm_idx; 12756c92544dSBjoern A. Zeeb u8 bssid[ETH_ALEN]; 12766c92544dSBjoern A. Zeeb __le16 bmc_tx_wlan_idx; 12776c92544dSBjoern A. Zeeb __le16 bcn_interval; 12786c92544dSBjoern A. Zeeb u8 dtim_period; 12796c92544dSBjoern A. Zeeb u8 phymode; /* bit(0): A 12806c92544dSBjoern A. Zeeb * bit(1): B 12816c92544dSBjoern A. Zeeb * bit(2): G 12826c92544dSBjoern A. Zeeb * bit(3): GN 12836c92544dSBjoern A. Zeeb * bit(4): AN 12846c92544dSBjoern A. Zeeb * bit(5): AC 12856c92544dSBjoern A. Zeeb * bit(6): AX2 12866c92544dSBjoern A. Zeeb * bit(7): AX5 12876c92544dSBjoern A. Zeeb * bit(8): AX6 12886c92544dSBjoern A. Zeeb */ 12896c92544dSBjoern A. Zeeb __le16 sta_idx; 12906c92544dSBjoern A. Zeeb __le16 nonht_basic_phy; 12916c92544dSBjoern A. Zeeb u8 phymode_ext; /* bit(0) AX_6G */ 12926c92544dSBjoern A. Zeeb u8 pad[1]; 12936c92544dSBjoern A. Zeeb } __packed; 12946c92544dSBjoern A. Zeeb 12956c92544dSBjoern A. Zeeb struct mt76_connac_bss_qos_tlv { 12966c92544dSBjoern A. Zeeb __le16 tag; 12976c92544dSBjoern A. Zeeb __le16 len; 12986c92544dSBjoern A. Zeeb u8 qos; 12996c92544dSBjoern A. Zeeb u8 pad[3]; 13006c92544dSBjoern A. Zeeb } __packed; 13016c92544dSBjoern A. Zeeb 13026c92544dSBjoern A. Zeeb struct mt76_connac_beacon_loss_event { 13036c92544dSBjoern A. Zeeb u8 bss_idx; 13046c92544dSBjoern A. Zeeb u8 reason; 13056c92544dSBjoern A. Zeeb u8 pad[2]; 13066c92544dSBjoern A. Zeeb } __packed; 13076c92544dSBjoern A. Zeeb 13086c92544dSBjoern A. Zeeb struct mt76_connac_mcu_bss_event { 13096c92544dSBjoern A. Zeeb u8 bss_idx; 13106c92544dSBjoern A. Zeeb u8 is_absent; 13116c92544dSBjoern A. Zeeb u8 free_quota; 13126c92544dSBjoern A. Zeeb u8 pad; 13136c92544dSBjoern A. Zeeb } __packed; 13146c92544dSBjoern A. Zeeb 13156c92544dSBjoern A. Zeeb struct mt76_connac_mcu_scan_ssid { 13166c92544dSBjoern A. Zeeb __le32 ssid_len; 13176c92544dSBjoern A. Zeeb u8 ssid[IEEE80211_MAX_SSID_LEN]; 13186c92544dSBjoern A. Zeeb } __packed; 13196c92544dSBjoern A. Zeeb 13206c92544dSBjoern A. Zeeb struct mt76_connac_mcu_scan_channel { 13216c92544dSBjoern A. Zeeb u8 band; /* 1: 2.4GHz 13226c92544dSBjoern A. Zeeb * 2: 5.0GHz 13236c92544dSBjoern A. Zeeb * Others: Reserved 13246c92544dSBjoern A. Zeeb */ 13256c92544dSBjoern A. Zeeb u8 channel_num; 13266c92544dSBjoern A. Zeeb } __packed; 13276c92544dSBjoern A. Zeeb 13286c92544dSBjoern A. Zeeb struct mt76_connac_mcu_scan_match { 13296c92544dSBjoern A. Zeeb __le32 rssi_th; 13306c92544dSBjoern A. Zeeb u8 ssid[IEEE80211_MAX_SSID_LEN]; 13316c92544dSBjoern A. Zeeb u8 ssid_len; 13326c92544dSBjoern A. Zeeb u8 rsv[3]; 13336c92544dSBjoern A. Zeeb } __packed; 13346c92544dSBjoern A. Zeeb 13356c92544dSBjoern A. Zeeb struct mt76_connac_hw_scan_req { 13366c92544dSBjoern A. Zeeb u8 seq_num; 13376c92544dSBjoern A. Zeeb u8 bss_idx; 13386c92544dSBjoern A. Zeeb u8 scan_type; /* 0: PASSIVE SCAN 13396c92544dSBjoern A. Zeeb * 1: ACTIVE SCAN 13406c92544dSBjoern A. Zeeb */ 13416c92544dSBjoern A. Zeeb u8 ssid_type; /* BIT(0) wildcard SSID 13426c92544dSBjoern A. Zeeb * BIT(1) P2P wildcard SSID 13436c92544dSBjoern A. Zeeb * BIT(2) specified SSID + wildcard SSID 13446c92544dSBjoern A. Zeeb * BIT(2) + ssid_type_ext BIT(0) specified SSID only 13456c92544dSBjoern A. Zeeb */ 13466c92544dSBjoern A. Zeeb u8 ssids_num; 13476c92544dSBjoern A. Zeeb u8 probe_req_num; /* Number of probe request for each SSID */ 13486c92544dSBjoern A. Zeeb u8 scan_func; /* BIT(0) Enable random MAC scan 13496c92544dSBjoern A. Zeeb * BIT(1) Disable DBDC scan type 1~3. 13506c92544dSBjoern A. Zeeb * BIT(2) Use DBDC scan type 3 (dedicated one RF to scan). 13516c92544dSBjoern A. Zeeb */ 13526c92544dSBjoern A. Zeeb u8 version; /* 0: Not support fields after ies. 13536c92544dSBjoern A. Zeeb * 1: Support fields after ies. 13546c92544dSBjoern A. Zeeb */ 13556c92544dSBjoern A. Zeeb struct mt76_connac_mcu_scan_ssid ssids[4]; 13566c92544dSBjoern A. Zeeb __le16 probe_delay_time; 13576c92544dSBjoern A. Zeeb __le16 channel_dwell_time; /* channel Dwell interval */ 13586c92544dSBjoern A. Zeeb __le16 timeout_value; 13596c92544dSBjoern A. Zeeb u8 channel_type; /* 0: Full channels 13606c92544dSBjoern A. Zeeb * 1: Only 2.4GHz channels 13616c92544dSBjoern A. Zeeb * 2: Only 5GHz channels 13626c92544dSBjoern A. Zeeb * 3: P2P social channel only (channel #1, #6 and #11) 13636c92544dSBjoern A. Zeeb * 4: Specified channels 13646c92544dSBjoern A. Zeeb * Others: Reserved 13656c92544dSBjoern A. Zeeb */ 13666c92544dSBjoern A. Zeeb u8 channels_num; /* valid when channel_type is 4 */ 13676c92544dSBjoern A. Zeeb /* valid when channels_num is set */ 13686c92544dSBjoern A. Zeeb struct mt76_connac_mcu_scan_channel channels[32]; 13696c92544dSBjoern A. Zeeb __le16 ies_len; 13706c92544dSBjoern A. Zeeb u8 ies[MT76_CONNAC_SCAN_IE_LEN]; 13716c92544dSBjoern A. Zeeb /* following fields are valid if version > 0 */ 13726c92544dSBjoern A. Zeeb u8 ext_channels_num; 13736c92544dSBjoern A. Zeeb u8 ext_ssids_num; 13746c92544dSBjoern A. Zeeb __le16 channel_min_dwell_time; 13756c92544dSBjoern A. Zeeb struct mt76_connac_mcu_scan_channel ext_channels[32]; 13766c92544dSBjoern A. Zeeb struct mt76_connac_mcu_scan_ssid ext_ssids[6]; 13776c92544dSBjoern A. Zeeb u8 bssid[ETH_ALEN]; 13786c92544dSBjoern A. Zeeb u8 random_mac[ETH_ALEN]; /* valid when BIT(1) in scan_func is set. */ 13796c92544dSBjoern A. Zeeb u8 pad[63]; 13806c92544dSBjoern A. Zeeb u8 ssid_type_ext; 13816c92544dSBjoern A. Zeeb } __packed; 13826c92544dSBjoern A. Zeeb 13836c92544dSBjoern A. Zeeb #define MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM 64 13846c92544dSBjoern A. Zeeb 13856c92544dSBjoern A. Zeeb struct mt76_connac_hw_scan_done { 13866c92544dSBjoern A. Zeeb u8 seq_num; 13876c92544dSBjoern A. Zeeb u8 sparse_channel_num; 13886c92544dSBjoern A. Zeeb struct mt76_connac_mcu_scan_channel sparse_channel; 13896c92544dSBjoern A. Zeeb u8 complete_channel_num; 13906c92544dSBjoern A. Zeeb u8 current_state; 13916c92544dSBjoern A. Zeeb u8 version; 13926c92544dSBjoern A. Zeeb u8 pad; 13936c92544dSBjoern A. Zeeb __le32 beacon_scan_num; 13946c92544dSBjoern A. Zeeb u8 pno_enabled; 13956c92544dSBjoern A. Zeeb u8 pad2[3]; 13966c92544dSBjoern A. Zeeb u8 sparse_channel_valid_num; 13976c92544dSBjoern A. Zeeb u8 pad3[3]; 13986c92544dSBjoern A. Zeeb u8 channel_num[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM]; 13996c92544dSBjoern A. Zeeb /* idle format for channel_idle_time 14006c92544dSBjoern A. Zeeb * 0: first bytes: idle time(ms) 2nd byte: dwell time(ms) 14016c92544dSBjoern A. Zeeb * 1: first bytes: idle time(8ms) 2nd byte: dwell time(8ms) 14026c92544dSBjoern A. Zeeb * 2: dwell time (16us) 14036c92544dSBjoern A. Zeeb */ 14046c92544dSBjoern A. Zeeb __le16 channel_idle_time[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM]; 14056c92544dSBjoern A. Zeeb /* beacon and probe response count */ 14066c92544dSBjoern A. Zeeb u8 beacon_probe_num[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM]; 14076c92544dSBjoern A. Zeeb u8 mdrdy_count[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM]; 14086c92544dSBjoern A. Zeeb __le32 beacon_2g_num; 14096c92544dSBjoern A. Zeeb __le32 beacon_5g_num; 14106c92544dSBjoern A. Zeeb } __packed; 14116c92544dSBjoern A. Zeeb 14126c92544dSBjoern A. Zeeb struct mt76_connac_sched_scan_req { 14136c92544dSBjoern A. Zeeb u8 version; 14146c92544dSBjoern A. Zeeb u8 seq_num; 14156c92544dSBjoern A. Zeeb u8 stop_on_match; 14166c92544dSBjoern A. Zeeb u8 ssids_num; 14176c92544dSBjoern A. Zeeb u8 match_num; 14186c92544dSBjoern A. Zeeb u8 pad; 14196c92544dSBjoern A. Zeeb __le16 ie_len; 14206c92544dSBjoern A. Zeeb struct mt76_connac_mcu_scan_ssid ssids[MT76_CONNAC_MAX_SCHED_SCAN_SSID]; 14216c92544dSBjoern A. Zeeb struct mt76_connac_mcu_scan_match match[MT76_CONNAC_MAX_SCAN_MATCH]; 14226c92544dSBjoern A. Zeeb u8 channel_type; 14236c92544dSBjoern A. Zeeb u8 channels_num; 14246c92544dSBjoern A. Zeeb u8 intervals_num; 14256c92544dSBjoern A. Zeeb u8 scan_func; /* MT7663: BIT(0) eable random mac address */ 14266c92544dSBjoern A. Zeeb struct mt76_connac_mcu_scan_channel channels[64]; 14276c92544dSBjoern A. Zeeb __le16 intervals[MT76_CONNAC_MAX_NUM_SCHED_SCAN_INTERVAL]; 14286c92544dSBjoern A. Zeeb union { 14296c92544dSBjoern A. Zeeb struct { 14306c92544dSBjoern A. Zeeb u8 random_mac[ETH_ALEN]; 14316c92544dSBjoern A. Zeeb u8 pad2[58]; 14326c92544dSBjoern A. Zeeb } mt7663; 14336c92544dSBjoern A. Zeeb struct { 14346c92544dSBjoern A. Zeeb u8 bss_idx; 14356c92544dSBjoern A. Zeeb u8 pad1[3]; 14366c92544dSBjoern A. Zeeb __le32 delay; 14376c92544dSBjoern A. Zeeb u8 pad2[12]; 14386c92544dSBjoern A. Zeeb u8 random_mac[ETH_ALEN]; 14396c92544dSBjoern A. Zeeb u8 pad3[38]; 14406c92544dSBjoern A. Zeeb } mt7921; 14416c92544dSBjoern A. Zeeb }; 14426c92544dSBjoern A. Zeeb } __packed; 14436c92544dSBjoern A. Zeeb 14446c92544dSBjoern A. Zeeb struct mt76_connac_sched_scan_done { 14456c92544dSBjoern A. Zeeb u8 seq_num; 14466c92544dSBjoern A. Zeeb u8 status; /* 0: ssid found */ 14476c92544dSBjoern A. Zeeb __le16 pad; 14486c92544dSBjoern A. Zeeb } __packed; 14496c92544dSBjoern A. Zeeb 14506c92544dSBjoern A. Zeeb struct bss_info_uni_bss_color { 14516c92544dSBjoern A. Zeeb __le16 tag; 14526c92544dSBjoern A. Zeeb __le16 len; 14536c92544dSBjoern A. Zeeb u8 enable; 14546c92544dSBjoern A. Zeeb u8 bss_color; 14556c92544dSBjoern A. Zeeb u8 rsv[2]; 14566c92544dSBjoern A. Zeeb } __packed; 14576c92544dSBjoern A. Zeeb 14586c92544dSBjoern A. Zeeb struct bss_info_uni_he { 14596c92544dSBjoern A. Zeeb __le16 tag; 14606c92544dSBjoern A. Zeeb __le16 len; 14616c92544dSBjoern A. Zeeb __le16 he_rts_thres; 14626c92544dSBjoern A. Zeeb u8 he_pe_duration; 14636c92544dSBjoern A. Zeeb u8 su_disable; 14646c92544dSBjoern A. Zeeb __le16 max_nss_mcs[CMD_HE_MCS_BW_NUM]; 14656c92544dSBjoern A. Zeeb u8 rsv[2]; 14666c92544dSBjoern A. Zeeb } __packed; 14676c92544dSBjoern A. Zeeb 14686c92544dSBjoern A. Zeeb struct mt76_connac_gtk_rekey_tlv { 14696c92544dSBjoern A. Zeeb __le16 tag; 14706c92544dSBjoern A. Zeeb __le16 len; 14716c92544dSBjoern A. Zeeb u8 kek[NL80211_KEK_LEN]; 14726c92544dSBjoern A. Zeeb u8 kck[NL80211_KCK_LEN]; 14736c92544dSBjoern A. Zeeb u8 replay_ctr[NL80211_REPLAY_CTR_LEN]; 14746c92544dSBjoern A. Zeeb u8 rekey_mode; /* 0: rekey offload enable 14756c92544dSBjoern A. Zeeb * 1: rekey offload disable 14766c92544dSBjoern A. Zeeb * 2: rekey update 14776c92544dSBjoern A. Zeeb */ 14786c92544dSBjoern A. Zeeb u8 keyid; 14796c92544dSBjoern A. Zeeb u8 option; /* 1: rekey data update without enabling offload */ 14806c92544dSBjoern A. Zeeb u8 pad[1]; 14816c92544dSBjoern A. Zeeb __le32 proto; /* WPA-RSN-WAPI-OPSN */ 14826c92544dSBjoern A. Zeeb __le32 pairwise_cipher; 14836c92544dSBjoern A. Zeeb __le32 group_cipher; 14846c92544dSBjoern A. Zeeb __le32 key_mgmt; /* NONE-PSK-IEEE802.1X */ 14856c92544dSBjoern A. Zeeb __le32 mgmt_group_cipher; 14866c92544dSBjoern A. Zeeb u8 reserverd[4]; 14876c92544dSBjoern A. Zeeb } __packed; 14886c92544dSBjoern A. Zeeb 14896c92544dSBjoern A. Zeeb #define MT76_CONNAC_WOW_MASK_MAX_LEN 16 14906c92544dSBjoern A. Zeeb #define MT76_CONNAC_WOW_PATTEN_MAX_LEN 128 14916c92544dSBjoern A. Zeeb 14926c92544dSBjoern A. Zeeb struct mt76_connac_wow_pattern_tlv { 14936c92544dSBjoern A. Zeeb __le16 tag; 14946c92544dSBjoern A. Zeeb __le16 len; 14956c92544dSBjoern A. Zeeb u8 index; /* pattern index */ 14966c92544dSBjoern A. Zeeb u8 enable; /* 0: disable 14976c92544dSBjoern A. Zeeb * 1: enable 14986c92544dSBjoern A. Zeeb */ 14996c92544dSBjoern A. Zeeb u8 data_len; /* pattern length */ 15006c92544dSBjoern A. Zeeb u8 pad; 15016c92544dSBjoern A. Zeeb u8 mask[MT76_CONNAC_WOW_MASK_MAX_LEN]; 15026c92544dSBjoern A. Zeeb u8 pattern[MT76_CONNAC_WOW_PATTEN_MAX_LEN]; 15036c92544dSBjoern A. Zeeb u8 rsv[4]; 15046c92544dSBjoern A. Zeeb } __packed; 15056c92544dSBjoern A. Zeeb 15066c92544dSBjoern A. Zeeb struct mt76_connac_wow_ctrl_tlv { 15076c92544dSBjoern A. Zeeb __le16 tag; 15086c92544dSBjoern A. Zeeb __le16 len; 15096c92544dSBjoern A. Zeeb u8 cmd; /* 0x1: PM_WOWLAN_REQ_START 15106c92544dSBjoern A. Zeeb * 0x2: PM_WOWLAN_REQ_STOP 15116c92544dSBjoern A. Zeeb * 0x3: PM_WOWLAN_PARAM_CLEAR 15126c92544dSBjoern A. Zeeb */ 15136c92544dSBjoern A. Zeeb u8 trigger; /* 0: NONE 15146c92544dSBjoern A. Zeeb * BIT(0): NL80211_WOWLAN_TRIG_MAGIC_PKT 15156c92544dSBjoern A. Zeeb * BIT(1): NL80211_WOWLAN_TRIG_ANY 15166c92544dSBjoern A. Zeeb * BIT(2): NL80211_WOWLAN_TRIG_DISCONNECT 15176c92544dSBjoern A. Zeeb * BIT(3): NL80211_WOWLAN_TRIG_GTK_REKEY_FAILURE 15186c92544dSBjoern A. Zeeb * BIT(4): BEACON_LOST 15196c92544dSBjoern A. Zeeb * BIT(5): NL80211_WOWLAN_TRIG_NET_DETECT 15206c92544dSBjoern A. Zeeb */ 15216c92544dSBjoern A. Zeeb u8 wakeup_hif; /* 0x0: HIF_SDIO 15226c92544dSBjoern A. Zeeb * 0x1: HIF_USB 15236c92544dSBjoern A. Zeeb * 0x2: HIF_PCIE 15246c92544dSBjoern A. Zeeb * 0x3: HIF_GPIO 15256c92544dSBjoern A. Zeeb */ 15266c92544dSBjoern A. Zeeb u8 pad; 15276c92544dSBjoern A. Zeeb u8 rsv[4]; 15286c92544dSBjoern A. Zeeb } __packed; 15296c92544dSBjoern A. Zeeb 15306c92544dSBjoern A. Zeeb struct mt76_connac_wow_gpio_param_tlv { 15316c92544dSBjoern A. Zeeb __le16 tag; 15326c92544dSBjoern A. Zeeb __le16 len; 15336c92544dSBjoern A. Zeeb u8 gpio_pin; 15346c92544dSBjoern A. Zeeb u8 trigger_lvl; 15356c92544dSBjoern A. Zeeb u8 pad[2]; 15366c92544dSBjoern A. Zeeb __le32 gpio_interval; 15376c92544dSBjoern A. Zeeb u8 rsv[4]; 15386c92544dSBjoern A. Zeeb } __packed; 15396c92544dSBjoern A. Zeeb 15406c92544dSBjoern A. Zeeb struct mt76_connac_arpns_tlv { 15416c92544dSBjoern A. Zeeb __le16 tag; 15426c92544dSBjoern A. Zeeb __le16 len; 15436c92544dSBjoern A. Zeeb u8 mode; 15446c92544dSBjoern A. Zeeb u8 ips_num; 15456c92544dSBjoern A. Zeeb u8 option; 15466c92544dSBjoern A. Zeeb u8 pad[1]; 15476c92544dSBjoern A. Zeeb } __packed; 15486c92544dSBjoern A. Zeeb 15496c92544dSBjoern A. Zeeb struct mt76_connac_suspend_tlv { 15506c92544dSBjoern A. Zeeb __le16 tag; 15516c92544dSBjoern A. Zeeb __le16 len; 15526c92544dSBjoern A. Zeeb u8 enable; /* 0: suspend mode disabled 15536c92544dSBjoern A. Zeeb * 1: suspend mode enabled 15546c92544dSBjoern A. Zeeb */ 15556c92544dSBjoern A. Zeeb u8 mdtim; /* LP parameter */ 15566c92544dSBjoern A. Zeeb u8 wow_suspend; /* 0: update by origin policy 15576c92544dSBjoern A. Zeeb * 1: update by wow dtim 15586c92544dSBjoern A. Zeeb */ 15596c92544dSBjoern A. Zeeb u8 pad[5]; 15606c92544dSBjoern A. Zeeb } __packed; 15616c92544dSBjoern A. Zeeb 15626c92544dSBjoern A. Zeeb enum mt76_sta_info_state { 15636c92544dSBjoern A. Zeeb MT76_STA_INFO_STATE_NONE, 15646c92544dSBjoern A. Zeeb MT76_STA_INFO_STATE_AUTH, 15656c92544dSBjoern A. Zeeb MT76_STA_INFO_STATE_ASSOC 15666c92544dSBjoern A. Zeeb }; 15676c92544dSBjoern A. Zeeb 15686c92544dSBjoern A. Zeeb struct mt76_sta_cmd_info { 15696c92544dSBjoern A. Zeeb struct ieee80211_sta *sta; 15706c92544dSBjoern A. Zeeb struct mt76_wcid *wcid; 15716c92544dSBjoern A. Zeeb 15726c92544dSBjoern A. Zeeb struct ieee80211_vif *vif; 15736c92544dSBjoern A. Zeeb 15746c92544dSBjoern A. Zeeb bool offload_fw; 15756c92544dSBjoern A. Zeeb bool enable; 15766c92544dSBjoern A. Zeeb bool newly; 15776c92544dSBjoern A. Zeeb int cmd; 15786c92544dSBjoern A. Zeeb u8 rcpi; 15796c92544dSBjoern A. Zeeb u8 state; 15806c92544dSBjoern A. Zeeb }; 15816c92544dSBjoern A. Zeeb 15826c92544dSBjoern A. Zeeb #define MT_SKU_POWER_LIMIT 161 15836c92544dSBjoern A. Zeeb 15846c92544dSBjoern A. Zeeb struct mt76_connac_sku_tlv { 15856c92544dSBjoern A. Zeeb u8 channel; 15866c92544dSBjoern A. Zeeb s8 pwr_limit[MT_SKU_POWER_LIMIT]; 15876c92544dSBjoern A. Zeeb } __packed; 15886c92544dSBjoern A. Zeeb 15896c92544dSBjoern A. Zeeb struct mt76_connac_tx_power_limit_tlv { 15906c92544dSBjoern A. Zeeb /* DW0 - common info*/ 15916c92544dSBjoern A. Zeeb u8 ver; 15926c92544dSBjoern A. Zeeb u8 pad0; 15936c92544dSBjoern A. Zeeb __le16 len; 15946c92544dSBjoern A. Zeeb /* DW1 - cmd hint */ 15956c92544dSBjoern A. Zeeb u8 n_chan; /* # channel */ 15966c92544dSBjoern A. Zeeb u8 band; /* 2.4GHz - 5GHz - 6GHz */ 15976c92544dSBjoern A. Zeeb u8 last_msg; 15986c92544dSBjoern A. Zeeb u8 pad1; 15996c92544dSBjoern A. Zeeb /* DW3 */ 16006c92544dSBjoern A. Zeeb u8 alpha2[4]; /* regulatory_request.alpha2 */ 16016c92544dSBjoern A. Zeeb u8 pad2[32]; 16026c92544dSBjoern A. Zeeb } __packed; 16036c92544dSBjoern A. Zeeb 16046c92544dSBjoern A. Zeeb struct mt76_connac_config { 16056c92544dSBjoern A. Zeeb __le16 id; 16066c92544dSBjoern A. Zeeb u8 type; 16076c92544dSBjoern A. Zeeb u8 resp_type; 16086c92544dSBjoern A. Zeeb __le16 data_size; 16096c92544dSBjoern A. Zeeb __le16 resv; 16106c92544dSBjoern A. Zeeb u8 data[320]; 16116c92544dSBjoern A. Zeeb } __packed; 16126c92544dSBjoern A. Zeeb 16136c92544dSBjoern A. Zeeb static inline enum mcu_cipher_type 16146c92544dSBjoern A. Zeeb mt76_connac_mcu_get_cipher(int cipher) 16156c92544dSBjoern A. Zeeb { 16166c92544dSBjoern A. Zeeb switch (cipher) { 16176c92544dSBjoern A. Zeeb case WLAN_CIPHER_SUITE_WEP40: 16186c92544dSBjoern A. Zeeb return MCU_CIPHER_WEP40; 16196c92544dSBjoern A. Zeeb case WLAN_CIPHER_SUITE_WEP104: 16206c92544dSBjoern A. Zeeb return MCU_CIPHER_WEP104; 16216c92544dSBjoern A. Zeeb case WLAN_CIPHER_SUITE_TKIP: 16226c92544dSBjoern A. Zeeb return MCU_CIPHER_TKIP; 16236c92544dSBjoern A. Zeeb case WLAN_CIPHER_SUITE_AES_CMAC: 16246c92544dSBjoern A. Zeeb return MCU_CIPHER_BIP_CMAC_128; 16256c92544dSBjoern A. Zeeb case WLAN_CIPHER_SUITE_CCMP: 16266c92544dSBjoern A. Zeeb return MCU_CIPHER_AES_CCMP; 16276c92544dSBjoern A. Zeeb case WLAN_CIPHER_SUITE_CCMP_256: 16286c92544dSBjoern A. Zeeb return MCU_CIPHER_CCMP_256; 16296c92544dSBjoern A. Zeeb case WLAN_CIPHER_SUITE_GCMP: 16306c92544dSBjoern A. Zeeb return MCU_CIPHER_GCMP; 16316c92544dSBjoern A. Zeeb case WLAN_CIPHER_SUITE_GCMP_256: 16326c92544dSBjoern A. Zeeb return MCU_CIPHER_GCMP_256; 16336c92544dSBjoern A. Zeeb case WLAN_CIPHER_SUITE_SMS4: 16346c92544dSBjoern A. Zeeb return MCU_CIPHER_WAPI; 16356c92544dSBjoern A. Zeeb default: 16366c92544dSBjoern A. Zeeb return MCU_CIPHER_NONE; 16376c92544dSBjoern A. Zeeb } 16386c92544dSBjoern A. Zeeb } 16396c92544dSBjoern A. Zeeb 16406c92544dSBjoern A. Zeeb static inline u32 16416c92544dSBjoern A. Zeeb mt76_connac_mcu_gen_dl_mode(struct mt76_dev *dev, u8 feature_set, bool is_wa) 16426c92544dSBjoern A. Zeeb { 16436c92544dSBjoern A. Zeeb u32 ret = 0; 16446c92544dSBjoern A. Zeeb 16456c92544dSBjoern A. Zeeb ret |= feature_set & FW_FEATURE_SET_ENCRYPT ? 16466c92544dSBjoern A. Zeeb DL_MODE_ENCRYPT | DL_MODE_RESET_SEC_IV : 0; 16476c92544dSBjoern A. Zeeb if (is_mt7921(dev)) 16486c92544dSBjoern A. Zeeb ret |= feature_set & FW_FEATURE_ENCRY_MODE ? 16496c92544dSBjoern A. Zeeb DL_CONFIG_ENCRY_MODE_SEL : 0; 16506c92544dSBjoern A. Zeeb ret |= FIELD_PREP(DL_MODE_KEY_IDX, 16516c92544dSBjoern A. Zeeb FIELD_GET(FW_FEATURE_SET_KEY_IDX, feature_set)); 16526c92544dSBjoern A. Zeeb ret |= DL_MODE_NEED_RSP; 16536c92544dSBjoern A. Zeeb ret |= is_wa ? DL_MODE_WORKING_PDA_CR4 : 0; 16546c92544dSBjoern A. Zeeb 16556c92544dSBjoern A. Zeeb return ret; 16566c92544dSBjoern A. Zeeb } 16576c92544dSBjoern A. Zeeb 16586c92544dSBjoern A. Zeeb #define to_wcid_lo(id) FIELD_GET(GENMASK(7, 0), (u16)id) 16596c92544dSBjoern A. Zeeb #define to_wcid_hi(id) FIELD_GET(GENMASK(9, 8), (u16)id) 16606c92544dSBjoern A. Zeeb 16616c92544dSBjoern A. Zeeb static inline void 16626c92544dSBjoern A. Zeeb mt76_connac_mcu_get_wlan_idx(struct mt76_dev *dev, struct mt76_wcid *wcid, 16636c92544dSBjoern A. Zeeb u8 *wlan_idx_lo, u8 *wlan_idx_hi) 16646c92544dSBjoern A. Zeeb { 16656c92544dSBjoern A. Zeeb *wlan_idx_hi = 0; 16666c92544dSBjoern A. Zeeb 16676c92544dSBjoern A. Zeeb if (!is_connac_v1(dev)) { 16686c92544dSBjoern A. Zeeb *wlan_idx_lo = wcid ? to_wcid_lo(wcid->idx) : 0; 16696c92544dSBjoern A. Zeeb *wlan_idx_hi = wcid ? to_wcid_hi(wcid->idx) : 0; 16706c92544dSBjoern A. Zeeb } else { 16716c92544dSBjoern A. Zeeb *wlan_idx_lo = wcid ? wcid->idx : 0; 16726c92544dSBjoern A. Zeeb } 16736c92544dSBjoern A. Zeeb } 16746c92544dSBjoern A. Zeeb 16756c92544dSBjoern A. Zeeb struct sk_buff * 16766c92544dSBjoern A. Zeeb __mt76_connac_mcu_alloc_sta_req(struct mt76_dev *dev, struct mt76_vif *mvif, 16776c92544dSBjoern A. Zeeb struct mt76_wcid *wcid, int len); 16786c92544dSBjoern A. Zeeb static inline struct sk_buff * 16796c92544dSBjoern A. Zeeb mt76_connac_mcu_alloc_sta_req(struct mt76_dev *dev, struct mt76_vif *mvif, 16806c92544dSBjoern A. Zeeb struct mt76_wcid *wcid) 16816c92544dSBjoern A. Zeeb { 16826c92544dSBjoern A. Zeeb return __mt76_connac_mcu_alloc_sta_req(dev, mvif, wcid, 16836c92544dSBjoern A. Zeeb MT76_CONNAC_STA_UPDATE_MAX_SIZE); 16846c92544dSBjoern A. Zeeb } 16856c92544dSBjoern A. Zeeb 16866c92544dSBjoern A. Zeeb struct wtbl_req_hdr * 16876c92544dSBjoern A. Zeeb mt76_connac_mcu_alloc_wtbl_req(struct mt76_dev *dev, struct mt76_wcid *wcid, 16886c92544dSBjoern A. Zeeb int cmd, void *sta_wtbl, struct sk_buff **skb); 16896c92544dSBjoern A. Zeeb struct tlv *mt76_connac_mcu_add_nested_tlv(struct sk_buff *skb, int tag, 16906c92544dSBjoern A. Zeeb int len, void *sta_ntlv, 16916c92544dSBjoern A. Zeeb void *sta_wtbl); 16926c92544dSBjoern A. Zeeb static inline struct tlv * 16936c92544dSBjoern A. Zeeb mt76_connac_mcu_add_tlv(struct sk_buff *skb, int tag, int len) 16946c92544dSBjoern A. Zeeb { 16956c92544dSBjoern A. Zeeb return mt76_connac_mcu_add_nested_tlv(skb, tag, len, skb->data, NULL); 16966c92544dSBjoern A. Zeeb } 16976c92544dSBjoern A. Zeeb 16986c92544dSBjoern A. Zeeb int mt76_connac_mcu_set_channel_domain(struct mt76_phy *phy); 16996c92544dSBjoern A. Zeeb int mt76_connac_mcu_set_vif_ps(struct mt76_dev *dev, struct ieee80211_vif *vif); 17006c92544dSBjoern A. Zeeb void mt76_connac_mcu_sta_basic_tlv(struct sk_buff *skb, 17016c92544dSBjoern A. Zeeb struct ieee80211_vif *vif, 17026c92544dSBjoern A. Zeeb struct ieee80211_sta *sta, bool enable, 17036c92544dSBjoern A. Zeeb bool newly); 17046c92544dSBjoern A. Zeeb void mt76_connac_mcu_wtbl_generic_tlv(struct mt76_dev *dev, struct sk_buff *skb, 17056c92544dSBjoern A. Zeeb struct ieee80211_vif *vif, 17066c92544dSBjoern A. Zeeb struct ieee80211_sta *sta, void *sta_wtbl, 17076c92544dSBjoern A. Zeeb void *wtbl_tlv); 17086c92544dSBjoern A. Zeeb void mt76_connac_mcu_wtbl_hdr_trans_tlv(struct sk_buff *skb, 17096c92544dSBjoern A. Zeeb struct ieee80211_vif *vif, 17106c92544dSBjoern A. Zeeb struct mt76_wcid *wcid, 17116c92544dSBjoern A. Zeeb void *sta_wtbl, void *wtbl_tlv); 17126c92544dSBjoern A. Zeeb int mt76_connac_mcu_sta_update_hdr_trans(struct mt76_dev *dev, 17136c92544dSBjoern A. Zeeb struct ieee80211_vif *vif, 17146c92544dSBjoern A. Zeeb struct mt76_wcid *wcid, int cmd); 17156c92544dSBjoern A. Zeeb int mt76_connac_mcu_wtbl_update_hdr_trans(struct mt76_dev *dev, 17166c92544dSBjoern A. Zeeb struct ieee80211_vif *vif, 17176c92544dSBjoern A. Zeeb struct ieee80211_sta *sta); 17186c92544dSBjoern A. Zeeb void mt76_connac_mcu_sta_tlv(struct mt76_phy *mphy, struct sk_buff *skb, 17196c92544dSBjoern A. Zeeb struct ieee80211_sta *sta, 17206c92544dSBjoern A. Zeeb struct ieee80211_vif *vif, 17216c92544dSBjoern A. Zeeb u8 rcpi, u8 state); 17226c92544dSBjoern A. Zeeb void mt76_connac_mcu_wtbl_ht_tlv(struct mt76_dev *dev, struct sk_buff *skb, 17236c92544dSBjoern A. Zeeb struct ieee80211_sta *sta, void *sta_wtbl, 17246c92544dSBjoern A. Zeeb void *wtbl_tlv, bool ht_ldpc, bool vht_ldpc); 17256c92544dSBjoern A. Zeeb void mt76_connac_mcu_wtbl_ba_tlv(struct mt76_dev *dev, struct sk_buff *skb, 17266c92544dSBjoern A. Zeeb struct ieee80211_ampdu_params *params, 17276c92544dSBjoern A. Zeeb bool enable, bool tx, void *sta_wtbl, 17286c92544dSBjoern A. Zeeb void *wtbl_tlv); 17296c92544dSBjoern A. Zeeb void mt76_connac_mcu_sta_ba_tlv(struct sk_buff *skb, 17306c92544dSBjoern A. Zeeb struct ieee80211_ampdu_params *params, 17316c92544dSBjoern A. Zeeb bool enable, bool tx); 17326c92544dSBjoern A. Zeeb int mt76_connac_mcu_uni_add_dev(struct mt76_phy *phy, 17336c92544dSBjoern A. Zeeb struct ieee80211_vif *vif, 17346c92544dSBjoern A. Zeeb struct mt76_wcid *wcid, 17356c92544dSBjoern A. Zeeb bool enable); 17366c92544dSBjoern A. Zeeb int mt76_connac_mcu_sta_ba(struct mt76_dev *dev, struct mt76_vif *mvif, 17376c92544dSBjoern A. Zeeb struct ieee80211_ampdu_params *params, 17386c92544dSBjoern A. Zeeb int cmd, bool enable, bool tx); 17396c92544dSBjoern A. Zeeb int mt76_connac_mcu_uni_add_bss(struct mt76_phy *phy, 17406c92544dSBjoern A. Zeeb struct ieee80211_vif *vif, 17416c92544dSBjoern A. Zeeb struct mt76_wcid *wcid, 17426c92544dSBjoern A. Zeeb bool enable); 17436c92544dSBjoern A. Zeeb int mt76_connac_mcu_sta_cmd(struct mt76_phy *phy, 17446c92544dSBjoern A. Zeeb struct mt76_sta_cmd_info *info); 17456c92544dSBjoern A. Zeeb void mt76_connac_mcu_beacon_loss_iter(void *priv, u8 *mac, 17466c92544dSBjoern A. Zeeb struct ieee80211_vif *vif); 17476c92544dSBjoern A. Zeeb int mt76_connac_mcu_set_rts_thresh(struct mt76_dev *dev, u32 val, u8 band); 17486c92544dSBjoern A. Zeeb int mt76_connac_mcu_set_mac_enable(struct mt76_dev *dev, int band, bool enable, 17496c92544dSBjoern A. Zeeb bool hdr_trans); 17506c92544dSBjoern A. Zeeb int mt76_connac_mcu_init_download(struct mt76_dev *dev, u32 addr, u32 len, 17516c92544dSBjoern A. Zeeb u32 mode); 17526c92544dSBjoern A. Zeeb int mt76_connac_mcu_start_patch(struct mt76_dev *dev); 17536c92544dSBjoern A. Zeeb int mt76_connac_mcu_patch_sem_ctrl(struct mt76_dev *dev, bool get); 17546c92544dSBjoern A. Zeeb int mt76_connac_mcu_start_firmware(struct mt76_dev *dev, u32 addr, u32 option); 17556c92544dSBjoern A. Zeeb int mt76_connac_mcu_get_nic_capability(struct mt76_phy *phy); 17566c92544dSBjoern A. Zeeb 17576c92544dSBjoern A. Zeeb int mt76_connac_mcu_hw_scan(struct mt76_phy *phy, struct ieee80211_vif *vif, 17586c92544dSBjoern A. Zeeb struct ieee80211_scan_request *scan_req); 17596c92544dSBjoern A. Zeeb int mt76_connac_mcu_cancel_hw_scan(struct mt76_phy *phy, 17606c92544dSBjoern A. Zeeb struct ieee80211_vif *vif); 17616c92544dSBjoern A. Zeeb int mt76_connac_mcu_sched_scan_req(struct mt76_phy *phy, 17626c92544dSBjoern A. Zeeb struct ieee80211_vif *vif, 17636c92544dSBjoern A. Zeeb struct cfg80211_sched_scan_request *sreq); 17646c92544dSBjoern A. Zeeb int mt76_connac_mcu_sched_scan_enable(struct mt76_phy *phy, 17656c92544dSBjoern A. Zeeb struct ieee80211_vif *vif, 17666c92544dSBjoern A. Zeeb bool enable); 17676c92544dSBjoern A. Zeeb int mt76_connac_mcu_update_arp_filter(struct mt76_dev *dev, 17686c92544dSBjoern A. Zeeb struct mt76_vif *vif, 17696c92544dSBjoern A. Zeeb struct ieee80211_bss_conf *info); 17706c92544dSBjoern A. Zeeb int mt76_connac_mcu_update_gtk_rekey(struct ieee80211_hw *hw, 17716c92544dSBjoern A. Zeeb struct ieee80211_vif *vif, 17726c92544dSBjoern A. Zeeb struct cfg80211_gtk_rekey_data *key); 17736c92544dSBjoern A. Zeeb int mt76_connac_mcu_set_hif_suspend(struct mt76_dev *dev, bool suspend); 17746c92544dSBjoern A. Zeeb void mt76_connac_mcu_set_suspend_iter(void *priv, u8 *mac, 17756c92544dSBjoern A. Zeeb struct ieee80211_vif *vif); 17766c92544dSBjoern A. Zeeb int mt76_connac_sta_state_dp(struct mt76_dev *dev, 17776c92544dSBjoern A. Zeeb enum ieee80211_sta_state old_state, 17786c92544dSBjoern A. Zeeb enum ieee80211_sta_state new_state); 17796c92544dSBjoern A. Zeeb int mt76_connac_mcu_chip_config(struct mt76_dev *dev); 17806c92544dSBjoern A. Zeeb int mt76_connac_mcu_set_deep_sleep(struct mt76_dev *dev, bool enable); 17816c92544dSBjoern A. Zeeb void mt76_connac_mcu_coredump_event(struct mt76_dev *dev, struct sk_buff *skb, 17826c92544dSBjoern A. Zeeb struct mt76_connac_coredump *coredump); 17836c92544dSBjoern A. Zeeb int mt76_connac_mcu_set_rate_txpower(struct mt76_phy *phy); 17846c92544dSBjoern A. Zeeb int mt76_connac_mcu_set_p2p_oppps(struct ieee80211_hw *hw, 17856c92544dSBjoern A. Zeeb struct ieee80211_vif *vif); 17866c92544dSBjoern A. Zeeb u32 mt76_connac_mcu_reg_rr(struct mt76_dev *dev, u32 offset); 17876c92544dSBjoern A. Zeeb void mt76_connac_mcu_reg_wr(struct mt76_dev *dev, u32 offset, u32 val); 17886c92544dSBjoern A. Zeeb 17896c92544dSBjoern A. Zeeb const struct ieee80211_sta_he_cap * 17906c92544dSBjoern A. Zeeb mt76_connac_get_he_phy_cap(struct mt76_phy *phy, struct ieee80211_vif *vif); 17916c92544dSBjoern A. Zeeb u8 mt76_connac_get_phy_mode(struct mt76_phy *phy, struct ieee80211_vif *vif, 17926c92544dSBjoern A. Zeeb enum nl80211_band band, struct ieee80211_sta *sta); 17936c92544dSBjoern A. Zeeb 17946c92544dSBjoern A. Zeeb int mt76_connac_mcu_add_key(struct mt76_dev *dev, struct ieee80211_vif *vif, 17956c92544dSBjoern A. Zeeb struct mt76_connac_sta_key_conf *sta_key_conf, 17966c92544dSBjoern A. Zeeb struct ieee80211_key_conf *key, int mcu_cmd, 17976c92544dSBjoern A. Zeeb struct mt76_wcid *wcid, enum set_key_cmd cmd); 17986c92544dSBjoern A. Zeeb 17996c92544dSBjoern A. Zeeb void mt76_connac_mcu_bss_ext_tlv(struct sk_buff *skb, struct mt76_vif *mvif); 18006c92544dSBjoern A. Zeeb void mt76_connac_mcu_bss_omac_tlv(struct sk_buff *skb, 18016c92544dSBjoern A. Zeeb struct ieee80211_vif *vif); 18026c92544dSBjoern A. Zeeb int mt76_connac_mcu_bss_basic_tlv(struct sk_buff *skb, 18036c92544dSBjoern A. Zeeb struct ieee80211_vif *vif, 18046c92544dSBjoern A. Zeeb struct ieee80211_sta *sta, 18056c92544dSBjoern A. Zeeb struct mt76_phy *phy, u16 wlan_idx, 18066c92544dSBjoern A. Zeeb bool enable); 18076c92544dSBjoern A. Zeeb void mt76_connac_mcu_sta_uapsd(struct sk_buff *skb, struct ieee80211_vif *vif, 18086c92544dSBjoern A. Zeeb struct ieee80211_sta *sta); 18096c92544dSBjoern A. Zeeb void mt76_connac_mcu_wtbl_smps_tlv(struct sk_buff *skb, 18106c92544dSBjoern A. Zeeb struct ieee80211_sta *sta, 18116c92544dSBjoern A. Zeeb void *sta_wtbl, void *wtbl_tlv); 18126c92544dSBjoern A. Zeeb int mt76_connac_mcu_set_pm(struct mt76_dev *dev, int band, int enter); 18136c92544dSBjoern A. Zeeb int mt76_connac_mcu_restart(struct mt76_dev *dev); 18146c92544dSBjoern A. Zeeb int mt76_connac_mcu_rdd_cmd(struct mt76_dev *dev, int cmd, u8 index, 18156c92544dSBjoern A. Zeeb u8 rx_sel, u8 val); 18166c92544dSBjoern A. Zeeb int mt76_connac2_load_ram(struct mt76_dev *dev, const char *fw_wm, 18176c92544dSBjoern A. Zeeb const char *fw_wa); 18186c92544dSBjoern A. Zeeb int mt76_connac2_load_patch(struct mt76_dev *dev, const char *fw_name); 18196c92544dSBjoern A. Zeeb int mt76_connac2_mcu_fill_message(struct mt76_dev *mdev, struct sk_buff *skb, 18206c92544dSBjoern A. Zeeb int cmd, int *wait_seq); 18216c92544dSBjoern A. Zeeb #endif /* __MT76_CONNAC_MCU_H */ 1822