16c92544dSBjoern A. Zeeb // SPDX-License-Identifier: ISC
26c92544dSBjoern A. Zeeb /*
36c92544dSBjoern A. Zeeb * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name>
46c92544dSBjoern A. Zeeb * Copyright (C) 2018 Lorenzo Bianconi <lorenzo.bianconi83@gmail.com>
56c92544dSBjoern A. Zeeb */
66c92544dSBjoern A. Zeeb
76c92544dSBjoern A. Zeeb #include <linux/kernel.h>
86c92544dSBjoern A. Zeeb #include <linux/irq.h>
96c92544dSBjoern A. Zeeb
106c92544dSBjoern A. Zeeb #include "mt76x02.h"
116c92544dSBjoern A. Zeeb #include "mt76x02_mcu.h"
126c92544dSBjoern A. Zeeb #include "trace.h"
136c92544dSBjoern A. Zeeb
mt76x02_pre_tbtt_tasklet(struct tasklet_struct * t)146c92544dSBjoern A. Zeeb static void mt76x02_pre_tbtt_tasklet(struct tasklet_struct *t)
156c92544dSBjoern A. Zeeb {
166c92544dSBjoern A. Zeeb struct mt76x02_dev *dev = from_tasklet(dev, t, mt76.pre_tbtt_tasklet);
176c92544dSBjoern A. Zeeb struct mt76_dev *mdev = &dev->mt76;
186c92544dSBjoern A. Zeeb struct mt76_queue *q = dev->mphy.q_tx[MT_TXQ_PSD];
196c92544dSBjoern A. Zeeb struct beacon_bc_data data = {};
206c92544dSBjoern A. Zeeb struct sk_buff *skb;
216c92544dSBjoern A. Zeeb int i;
226c92544dSBjoern A. Zeeb
236c92544dSBjoern A. Zeeb if (mt76_hw(dev)->conf.flags & IEEE80211_CONF_OFFCHANNEL)
246c92544dSBjoern A. Zeeb return;
256c92544dSBjoern A. Zeeb
266c92544dSBjoern A. Zeeb mt76x02_resync_beacon_timer(dev);
276c92544dSBjoern A. Zeeb
286c92544dSBjoern A. Zeeb /* Prevent corrupt transmissions during update */
296c92544dSBjoern A. Zeeb mt76_set(dev, MT_BCN_BYPASS_MASK, 0xffff);
306c92544dSBjoern A. Zeeb dev->beacon_data_count = 0;
316c92544dSBjoern A. Zeeb
326c92544dSBjoern A. Zeeb ieee80211_iterate_active_interfaces_atomic(mt76_hw(dev),
336c92544dSBjoern A. Zeeb IEEE80211_IFACE_ITER_RESUME_ALL,
346c92544dSBjoern A. Zeeb mt76x02_update_beacon_iter, dev);
356c92544dSBjoern A. Zeeb
366c92544dSBjoern A. Zeeb mt76_wr(dev, MT_BCN_BYPASS_MASK,
376c92544dSBjoern A. Zeeb 0xff00 | ~(0xff00 >> dev->beacon_data_count));
386c92544dSBjoern A. Zeeb
396c92544dSBjoern A. Zeeb mt76_csa_check(mdev);
406c92544dSBjoern A. Zeeb
416c92544dSBjoern A. Zeeb if (mdev->csa_complete)
426c92544dSBjoern A. Zeeb return;
436c92544dSBjoern A. Zeeb
446c92544dSBjoern A. Zeeb mt76x02_enqueue_buffered_bc(dev, &data, 8);
456c92544dSBjoern A. Zeeb
466c92544dSBjoern A. Zeeb if (!skb_queue_len(&data.q))
476c92544dSBjoern A. Zeeb return;
486c92544dSBjoern A. Zeeb
496c92544dSBjoern A. Zeeb for (i = 0; i < ARRAY_SIZE(data.tail); i++) {
506c92544dSBjoern A. Zeeb if (!data.tail[i])
516c92544dSBjoern A. Zeeb continue;
526c92544dSBjoern A. Zeeb
536c92544dSBjoern A. Zeeb mt76_skb_set_moredata(data.tail[i], false);
546c92544dSBjoern A. Zeeb }
556c92544dSBjoern A. Zeeb
566c92544dSBjoern A. Zeeb spin_lock(&q->lock);
576c92544dSBjoern A. Zeeb while ((skb = __skb_dequeue(&data.q)) != NULL) {
586c92544dSBjoern A. Zeeb struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
596c92544dSBjoern A. Zeeb struct ieee80211_vif *vif = info->control.vif;
606c92544dSBjoern A. Zeeb struct mt76x02_vif *mvif = (struct mt76x02_vif *)vif->drv_priv;
616c92544dSBjoern A. Zeeb
626c92544dSBjoern A. Zeeb mt76_tx_queue_skb(dev, q, MT_TXQ_PSD, skb, &mvif->group_wcid,
636c92544dSBjoern A. Zeeb NULL);
646c92544dSBjoern A. Zeeb }
656c92544dSBjoern A. Zeeb spin_unlock(&q->lock);
666c92544dSBjoern A. Zeeb }
676c92544dSBjoern A. Zeeb
mt76x02e_pre_tbtt_enable(struct mt76x02_dev * dev,bool en)686c92544dSBjoern A. Zeeb static void mt76x02e_pre_tbtt_enable(struct mt76x02_dev *dev, bool en)
696c92544dSBjoern A. Zeeb {
706c92544dSBjoern A. Zeeb if (en)
716c92544dSBjoern A. Zeeb tasklet_enable(&dev->mt76.pre_tbtt_tasklet);
726c92544dSBjoern A. Zeeb else
736c92544dSBjoern A. Zeeb tasklet_disable(&dev->mt76.pre_tbtt_tasklet);
746c92544dSBjoern A. Zeeb }
756c92544dSBjoern A. Zeeb
mt76x02e_beacon_enable(struct mt76x02_dev * dev,bool en)766c92544dSBjoern A. Zeeb static void mt76x02e_beacon_enable(struct mt76x02_dev *dev, bool en)
776c92544dSBjoern A. Zeeb {
786c92544dSBjoern A. Zeeb mt76_rmw_field(dev, MT_INT_TIMER_EN, MT_INT_TIMER_EN_PRE_TBTT_EN, en);
796c92544dSBjoern A. Zeeb if (en)
806c92544dSBjoern A. Zeeb mt76x02_irq_enable(dev, MT_INT_PRE_TBTT | MT_INT_TBTT);
816c92544dSBjoern A. Zeeb else
826c92544dSBjoern A. Zeeb mt76x02_irq_disable(dev, MT_INT_PRE_TBTT | MT_INT_TBTT);
836c92544dSBjoern A. Zeeb }
846c92544dSBjoern A. Zeeb
mt76x02e_init_beacon_config(struct mt76x02_dev * dev)856c92544dSBjoern A. Zeeb void mt76x02e_init_beacon_config(struct mt76x02_dev *dev)
866c92544dSBjoern A. Zeeb {
876c92544dSBjoern A. Zeeb static const struct mt76x02_beacon_ops beacon_ops = {
886c92544dSBjoern A. Zeeb .nslots = 8,
896c92544dSBjoern A. Zeeb .slot_size = 1024,
906c92544dSBjoern A. Zeeb .pre_tbtt_enable = mt76x02e_pre_tbtt_enable,
916c92544dSBjoern A. Zeeb .beacon_enable = mt76x02e_beacon_enable,
926c92544dSBjoern A. Zeeb };
936c92544dSBjoern A. Zeeb
946c92544dSBjoern A. Zeeb dev->beacon_ops = &beacon_ops;
956c92544dSBjoern A. Zeeb
966c92544dSBjoern A. Zeeb /* Fire a pre-TBTT interrupt 8 ms before TBTT */
976c92544dSBjoern A. Zeeb mt76_rmw_field(dev, MT_INT_TIMER_CFG, MT_INT_TIMER_CFG_PRE_TBTT,
986c92544dSBjoern A. Zeeb 8 << 4);
996c92544dSBjoern A. Zeeb mt76_rmw_field(dev, MT_INT_TIMER_CFG, MT_INT_TIMER_CFG_GP_TIMER,
1006c92544dSBjoern A. Zeeb MT_DFS_GP_INTERVAL);
1016c92544dSBjoern A. Zeeb mt76_wr(dev, MT_INT_TIMER_EN, 0);
1026c92544dSBjoern A. Zeeb
1036c92544dSBjoern A. Zeeb mt76x02_init_beacon_config(dev);
1046c92544dSBjoern A. Zeeb }
1056c92544dSBjoern A. Zeeb EXPORT_SYMBOL_GPL(mt76x02e_init_beacon_config);
1066c92544dSBjoern A. Zeeb
1076c92544dSBjoern A. Zeeb static int
mt76x02_init_rx_queue(struct mt76x02_dev * dev,struct mt76_queue * q,int idx,int n_desc,int bufsize)1086c92544dSBjoern A. Zeeb mt76x02_init_rx_queue(struct mt76x02_dev *dev, struct mt76_queue *q,
1096c92544dSBjoern A. Zeeb int idx, int n_desc, int bufsize)
1106c92544dSBjoern A. Zeeb {
1116c92544dSBjoern A. Zeeb int err;
1126c92544dSBjoern A. Zeeb
1136c92544dSBjoern A. Zeeb err = mt76_queue_alloc(dev, q, idx, n_desc, bufsize,
1146c92544dSBjoern A. Zeeb MT_RX_RING_BASE);
1156c92544dSBjoern A. Zeeb if (err < 0)
1166c92544dSBjoern A. Zeeb return err;
1176c92544dSBjoern A. Zeeb
1186c92544dSBjoern A. Zeeb mt76x02_irq_enable(dev, MT_INT_RX_DONE(idx));
1196c92544dSBjoern A. Zeeb
1206c92544dSBjoern A. Zeeb return 0;
1216c92544dSBjoern A. Zeeb }
1226c92544dSBjoern A. Zeeb
mt76x02_process_tx_status_fifo(struct mt76x02_dev * dev)1236c92544dSBjoern A. Zeeb static void mt76x02_process_tx_status_fifo(struct mt76x02_dev *dev)
1246c92544dSBjoern A. Zeeb {
1256c92544dSBjoern A. Zeeb struct mt76x02_tx_status stat;
1266c92544dSBjoern A. Zeeb u8 update = 1;
1276c92544dSBjoern A. Zeeb
1286c92544dSBjoern A. Zeeb while (kfifo_get(&dev->txstatus_fifo, &stat))
1296c92544dSBjoern A. Zeeb mt76x02_send_tx_status(dev, &stat, &update);
1306c92544dSBjoern A. Zeeb }
1316c92544dSBjoern A. Zeeb
mt76x02_tx_worker(struct mt76_worker * w)1326c92544dSBjoern A. Zeeb static void mt76x02_tx_worker(struct mt76_worker *w)
1336c92544dSBjoern A. Zeeb {
1346c92544dSBjoern A. Zeeb struct mt76x02_dev *dev;
1356c92544dSBjoern A. Zeeb
1366c92544dSBjoern A. Zeeb dev = container_of(w, struct mt76x02_dev, mt76.tx_worker);
1376c92544dSBjoern A. Zeeb
1386c92544dSBjoern A. Zeeb mt76x02_mac_poll_tx_status(dev, false);
1396c92544dSBjoern A. Zeeb mt76x02_process_tx_status_fifo(dev);
1406c92544dSBjoern A. Zeeb
1416c92544dSBjoern A. Zeeb mt76_txq_schedule_all(&dev->mphy);
1426c92544dSBjoern A. Zeeb }
1436c92544dSBjoern A. Zeeb
mt76x02_poll_tx(struct napi_struct * napi,int budget)1446c92544dSBjoern A. Zeeb static int mt76x02_poll_tx(struct napi_struct *napi, int budget)
1456c92544dSBjoern A. Zeeb {
1466c92544dSBjoern A. Zeeb struct mt76x02_dev *dev = container_of(napi, struct mt76x02_dev,
1476c92544dSBjoern A. Zeeb mt76.tx_napi);
1486c92544dSBjoern A. Zeeb int i;
1496c92544dSBjoern A. Zeeb
1506c92544dSBjoern A. Zeeb mt76x02_mac_poll_tx_status(dev, false);
1516c92544dSBjoern A. Zeeb
1526c92544dSBjoern A. Zeeb mt76_queue_tx_cleanup(dev, dev->mt76.q_mcu[MT_MCUQ_WM], false);
1536c92544dSBjoern A. Zeeb for (i = MT_TXQ_PSD; i >= 0; i--)
1546c92544dSBjoern A. Zeeb mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[i], false);
1556c92544dSBjoern A. Zeeb
1566c92544dSBjoern A. Zeeb if (napi_complete_done(napi, 0))
1576c92544dSBjoern A. Zeeb mt76x02_irq_enable(dev, MT_INT_TX_DONE_ALL);
1586c92544dSBjoern A. Zeeb
1596c92544dSBjoern A. Zeeb mt76_queue_tx_cleanup(dev, dev->mt76.q_mcu[MT_MCUQ_WM], false);
1606c92544dSBjoern A. Zeeb for (i = MT_TXQ_PSD; i >= 0; i--)
1616c92544dSBjoern A. Zeeb mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[i], false);
1626c92544dSBjoern A. Zeeb
1636c92544dSBjoern A. Zeeb mt76_worker_schedule(&dev->mt76.tx_worker);
1646c92544dSBjoern A. Zeeb
1656c92544dSBjoern A. Zeeb return 0;
1666c92544dSBjoern A. Zeeb }
1676c92544dSBjoern A. Zeeb
mt76x02_dma_init(struct mt76x02_dev * dev)1686c92544dSBjoern A. Zeeb int mt76x02_dma_init(struct mt76x02_dev *dev)
1696c92544dSBjoern A. Zeeb {
1706c92544dSBjoern A. Zeeb struct mt76_txwi_cache __maybe_unused *t;
1716c92544dSBjoern A. Zeeb int i, ret, fifo_size;
1726c92544dSBjoern A. Zeeb struct mt76_queue *q;
1736c92544dSBjoern A. Zeeb void *status_fifo;
1746c92544dSBjoern A. Zeeb
1756c92544dSBjoern A. Zeeb BUILD_BUG_ON(sizeof(struct mt76x02_rxwi) > MT_RX_HEADROOM);
1766c92544dSBjoern A. Zeeb
1776c92544dSBjoern A. Zeeb fifo_size = roundup_pow_of_two(32 * sizeof(struct mt76x02_tx_status));
1786c92544dSBjoern A. Zeeb status_fifo = devm_kzalloc(dev->mt76.dev, fifo_size, GFP_KERNEL);
1796c92544dSBjoern A. Zeeb if (!status_fifo)
1806c92544dSBjoern A. Zeeb return -ENOMEM;
1816c92544dSBjoern A. Zeeb
1826c92544dSBjoern A. Zeeb dev->mt76.tx_worker.fn = mt76x02_tx_worker;
1836c92544dSBjoern A. Zeeb tasklet_setup(&dev->mt76.pre_tbtt_tasklet, mt76x02_pre_tbtt_tasklet);
1846c92544dSBjoern A. Zeeb
1856c92544dSBjoern A. Zeeb spin_lock_init(&dev->txstatus_fifo_lock);
1866c92544dSBjoern A. Zeeb kfifo_init(&dev->txstatus_fifo, status_fifo, fifo_size);
1876c92544dSBjoern A. Zeeb
1886c92544dSBjoern A. Zeeb mt76_dma_attach(&dev->mt76);
1896c92544dSBjoern A. Zeeb
1906c92544dSBjoern A. Zeeb mt76_wr(dev, MT_WPDMA_RST_IDX, ~0);
1916c92544dSBjoern A. Zeeb
1926c92544dSBjoern A. Zeeb for (i = 0; i < IEEE80211_NUM_ACS; i++) {
1936c92544dSBjoern A. Zeeb ret = mt76_init_tx_queue(&dev->mphy, i, mt76_ac_to_hwq(i),
1946c92544dSBjoern A. Zeeb MT76x02_TX_RING_SIZE,
1956c92544dSBjoern A. Zeeb MT_TX_RING_BASE, 0);
1966c92544dSBjoern A. Zeeb if (ret)
1976c92544dSBjoern A. Zeeb return ret;
1986c92544dSBjoern A. Zeeb }
1996c92544dSBjoern A. Zeeb
2006c92544dSBjoern A. Zeeb ret = mt76_init_tx_queue(&dev->mphy, MT_TXQ_PSD, MT_TX_HW_QUEUE_MGMT,
2016c92544dSBjoern A. Zeeb MT76x02_PSD_RING_SIZE, MT_TX_RING_BASE, 0);
2026c92544dSBjoern A. Zeeb if (ret)
2036c92544dSBjoern A. Zeeb return ret;
2046c92544dSBjoern A. Zeeb
2056c92544dSBjoern A. Zeeb ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_WM, MT_TX_HW_QUEUE_MCU,
2066c92544dSBjoern A. Zeeb MT_MCU_RING_SIZE, MT_TX_RING_BASE);
2076c92544dSBjoern A. Zeeb if (ret)
2086c92544dSBjoern A. Zeeb return ret;
2096c92544dSBjoern A. Zeeb
2106c92544dSBjoern A. Zeeb mt76x02_irq_enable(dev,
2116c92544dSBjoern A. Zeeb MT_INT_TX_DONE(IEEE80211_AC_VO) |
2126c92544dSBjoern A. Zeeb MT_INT_TX_DONE(IEEE80211_AC_VI) |
2136c92544dSBjoern A. Zeeb MT_INT_TX_DONE(IEEE80211_AC_BE) |
2146c92544dSBjoern A. Zeeb MT_INT_TX_DONE(IEEE80211_AC_BK) |
2156c92544dSBjoern A. Zeeb MT_INT_TX_DONE(MT_TX_HW_QUEUE_MGMT) |
2166c92544dSBjoern A. Zeeb MT_INT_TX_DONE(MT_TX_HW_QUEUE_MCU));
2176c92544dSBjoern A. Zeeb
2186c92544dSBjoern A. Zeeb ret = mt76x02_init_rx_queue(dev, &dev->mt76.q_rx[MT_RXQ_MCU], 1,
2196c92544dSBjoern A. Zeeb MT_MCU_RING_SIZE, MT_RX_BUF_SIZE);
2206c92544dSBjoern A. Zeeb if (ret)
2216c92544dSBjoern A. Zeeb return ret;
2226c92544dSBjoern A. Zeeb
2236c92544dSBjoern A. Zeeb q = &dev->mt76.q_rx[MT_RXQ_MAIN];
2246c92544dSBjoern A. Zeeb q->buf_offset = MT_RX_HEADROOM - sizeof(struct mt76x02_rxwi);
2256c92544dSBjoern A. Zeeb ret = mt76x02_init_rx_queue(dev, q, 0, MT76X02_RX_RING_SIZE,
2266c92544dSBjoern A. Zeeb MT_RX_BUF_SIZE);
2276c92544dSBjoern A. Zeeb if (ret)
2286c92544dSBjoern A. Zeeb return ret;
2296c92544dSBjoern A. Zeeb
2306c92544dSBjoern A. Zeeb ret = mt76_init_queues(dev, mt76_dma_rx_poll);
2316c92544dSBjoern A. Zeeb if (ret)
2326c92544dSBjoern A. Zeeb return ret;
2336c92544dSBjoern A. Zeeb
2346c92544dSBjoern A. Zeeb netif_napi_add_tx(&dev->mt76.tx_napi_dev, &dev->mt76.tx_napi,
2356c92544dSBjoern A. Zeeb mt76x02_poll_tx);
2366c92544dSBjoern A. Zeeb napi_enable(&dev->mt76.tx_napi);
2376c92544dSBjoern A. Zeeb
2386c92544dSBjoern A. Zeeb return 0;
2396c92544dSBjoern A. Zeeb }
2406c92544dSBjoern A. Zeeb EXPORT_SYMBOL_GPL(mt76x02_dma_init);
2416c92544dSBjoern A. Zeeb
mt76x02_rx_poll_complete(struct mt76_dev * mdev,enum mt76_rxq_id q)2426c92544dSBjoern A. Zeeb void mt76x02_rx_poll_complete(struct mt76_dev *mdev, enum mt76_rxq_id q)
2436c92544dSBjoern A. Zeeb {
2446c92544dSBjoern A. Zeeb struct mt76x02_dev *dev;
2456c92544dSBjoern A. Zeeb
2466c92544dSBjoern A. Zeeb dev = container_of(mdev, struct mt76x02_dev, mt76);
2476c92544dSBjoern A. Zeeb mt76x02_irq_enable(dev, MT_INT_RX_DONE(q));
2486c92544dSBjoern A. Zeeb }
2496c92544dSBjoern A. Zeeb EXPORT_SYMBOL_GPL(mt76x02_rx_poll_complete);
2506c92544dSBjoern A. Zeeb
mt76x02_irq_handler(int irq,void * dev_instance)2516c92544dSBjoern A. Zeeb irqreturn_t mt76x02_irq_handler(int irq, void *dev_instance)
2526c92544dSBjoern A. Zeeb {
2536c92544dSBjoern A. Zeeb struct mt76x02_dev *dev = dev_instance;
2546c92544dSBjoern A. Zeeb u32 intr, mask;
2556c92544dSBjoern A. Zeeb
2566c92544dSBjoern A. Zeeb intr = mt76_rr(dev, MT_INT_SOURCE_CSR);
2576c92544dSBjoern A. Zeeb intr &= dev->mt76.mmio.irqmask;
2586c92544dSBjoern A. Zeeb mt76_wr(dev, MT_INT_SOURCE_CSR, intr);
2596c92544dSBjoern A. Zeeb
2606c92544dSBjoern A. Zeeb if (!test_bit(MT76_STATE_INITIALIZED, &dev->mphy.state))
2616c92544dSBjoern A. Zeeb return IRQ_NONE;
2626c92544dSBjoern A. Zeeb
2636c92544dSBjoern A. Zeeb trace_dev_irq(&dev->mt76, intr, dev->mt76.mmio.irqmask);
2646c92544dSBjoern A. Zeeb
2656c92544dSBjoern A. Zeeb mask = intr & (MT_INT_RX_DONE_ALL | MT_INT_GPTIMER);
2666c92544dSBjoern A. Zeeb if (intr & (MT_INT_TX_DONE_ALL | MT_INT_TX_STAT))
2676c92544dSBjoern A. Zeeb mask |= MT_INT_TX_DONE_ALL;
2686c92544dSBjoern A. Zeeb
2696c92544dSBjoern A. Zeeb mt76x02_irq_disable(dev, mask);
2706c92544dSBjoern A. Zeeb
2716c92544dSBjoern A. Zeeb if (intr & MT_INT_RX_DONE(0))
2726c92544dSBjoern A. Zeeb napi_schedule(&dev->mt76.napi[0]);
2736c92544dSBjoern A. Zeeb
2746c92544dSBjoern A. Zeeb if (intr & MT_INT_RX_DONE(1))
2756c92544dSBjoern A. Zeeb napi_schedule(&dev->mt76.napi[1]);
2766c92544dSBjoern A. Zeeb
2776c92544dSBjoern A. Zeeb if (intr & MT_INT_PRE_TBTT)
2786c92544dSBjoern A. Zeeb tasklet_schedule(&dev->mt76.pre_tbtt_tasklet);
2796c92544dSBjoern A. Zeeb
2806c92544dSBjoern A. Zeeb /* send buffered multicast frames now */
2816c92544dSBjoern A. Zeeb if (intr & MT_INT_TBTT) {
2826c92544dSBjoern A. Zeeb if (dev->mt76.csa_complete)
2836c92544dSBjoern A. Zeeb mt76_csa_finish(&dev->mt76);
2846c92544dSBjoern A. Zeeb else
2856c92544dSBjoern A. Zeeb mt76_queue_kick(dev, dev->mphy.q_tx[MT_TXQ_PSD]);
2866c92544dSBjoern A. Zeeb }
2876c92544dSBjoern A. Zeeb
2886c92544dSBjoern A. Zeeb if (intr & MT_INT_TX_STAT)
2896c92544dSBjoern A. Zeeb mt76x02_mac_poll_tx_status(dev, true);
2906c92544dSBjoern A. Zeeb
2916c92544dSBjoern A. Zeeb if (intr & (MT_INT_TX_STAT | MT_INT_TX_DONE_ALL))
2926c92544dSBjoern A. Zeeb napi_schedule(&dev->mt76.tx_napi);
2936c92544dSBjoern A. Zeeb
2946c92544dSBjoern A. Zeeb if (intr & MT_INT_GPTIMER)
2956c92544dSBjoern A. Zeeb tasklet_schedule(&dev->dfs_pd.dfs_tasklet);
2966c92544dSBjoern A. Zeeb
2976c92544dSBjoern A. Zeeb return IRQ_HANDLED;
2986c92544dSBjoern A. Zeeb }
2996c92544dSBjoern A. Zeeb EXPORT_SYMBOL_GPL(mt76x02_irq_handler);
3006c92544dSBjoern A. Zeeb
mt76x02_dma_enable(struct mt76x02_dev * dev)3016c92544dSBjoern A. Zeeb static void mt76x02_dma_enable(struct mt76x02_dev *dev)
3026c92544dSBjoern A. Zeeb {
3036c92544dSBjoern A. Zeeb u32 val;
3046c92544dSBjoern A. Zeeb
3056c92544dSBjoern A. Zeeb mt76_wr(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_TX);
3066c92544dSBjoern A. Zeeb mt76x02_wait_for_wpdma(&dev->mt76, 1000);
3076c92544dSBjoern A. Zeeb usleep_range(50, 100);
3086c92544dSBjoern A. Zeeb
3096c92544dSBjoern A. Zeeb val = FIELD_PREP(MT_WPDMA_GLO_CFG_DMA_BURST_SIZE, 3) |
3106c92544dSBjoern A. Zeeb MT_WPDMA_GLO_CFG_TX_DMA_EN |
3116c92544dSBjoern A. Zeeb MT_WPDMA_GLO_CFG_RX_DMA_EN;
3126c92544dSBjoern A. Zeeb mt76_set(dev, MT_WPDMA_GLO_CFG, val);
3136c92544dSBjoern A. Zeeb mt76_clear(dev, MT_WPDMA_GLO_CFG,
3146c92544dSBjoern A. Zeeb MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE);
3156c92544dSBjoern A. Zeeb }
3166c92544dSBjoern A. Zeeb
mt76x02_dma_disable(struct mt76x02_dev * dev)3176c92544dSBjoern A. Zeeb void mt76x02_dma_disable(struct mt76x02_dev *dev)
3186c92544dSBjoern A. Zeeb {
3196c92544dSBjoern A. Zeeb u32 val = mt76_rr(dev, MT_WPDMA_GLO_CFG);
3206c92544dSBjoern A. Zeeb
3216c92544dSBjoern A. Zeeb val &= MT_WPDMA_GLO_CFG_DMA_BURST_SIZE |
3226c92544dSBjoern A. Zeeb MT_WPDMA_GLO_CFG_BIG_ENDIAN |
3236c92544dSBjoern A. Zeeb MT_WPDMA_GLO_CFG_HDR_SEG_LEN;
3246c92544dSBjoern A. Zeeb val |= MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE;
3256c92544dSBjoern A. Zeeb mt76_wr(dev, MT_WPDMA_GLO_CFG, val);
3266c92544dSBjoern A. Zeeb }
3276c92544dSBjoern A. Zeeb EXPORT_SYMBOL_GPL(mt76x02_dma_disable);
3286c92544dSBjoern A. Zeeb
mt76x02_mac_start(struct mt76x02_dev * dev)3296c92544dSBjoern A. Zeeb void mt76x02_mac_start(struct mt76x02_dev *dev)
3306c92544dSBjoern A. Zeeb {
3316c92544dSBjoern A. Zeeb mt76x02_mac_reset_counters(dev);
3326c92544dSBjoern A. Zeeb mt76x02_dma_enable(dev);
3336c92544dSBjoern A. Zeeb mt76_wr(dev, MT_RX_FILTR_CFG, dev->mt76.rxfilter);
3346c92544dSBjoern A. Zeeb mt76_wr(dev, MT_MAC_SYS_CTRL,
3356c92544dSBjoern A. Zeeb MT_MAC_SYS_CTRL_ENABLE_TX |
3366c92544dSBjoern A. Zeeb MT_MAC_SYS_CTRL_ENABLE_RX);
3376c92544dSBjoern A. Zeeb mt76x02_irq_enable(dev,
3386c92544dSBjoern A. Zeeb MT_INT_RX_DONE_ALL | MT_INT_TX_DONE_ALL |
3396c92544dSBjoern A. Zeeb MT_INT_TX_STAT);
3406c92544dSBjoern A. Zeeb }
3416c92544dSBjoern A. Zeeb EXPORT_SYMBOL_GPL(mt76x02_mac_start);
3426c92544dSBjoern A. Zeeb
mt76x02_tx_hang(struct mt76x02_dev * dev)3436c92544dSBjoern A. Zeeb static bool mt76x02_tx_hang(struct mt76x02_dev *dev)
3446c92544dSBjoern A. Zeeb {
3456c92544dSBjoern A. Zeeb u32 dma_idx, prev_dma_idx;
3466c92544dSBjoern A. Zeeb struct mt76_queue *q;
3476c92544dSBjoern A. Zeeb int i;
3486c92544dSBjoern A. Zeeb
3496c92544dSBjoern A. Zeeb for (i = 0; i < 4; i++) {
3506c92544dSBjoern A. Zeeb q = dev->mphy.q_tx[i];
3516c92544dSBjoern A. Zeeb
3526c92544dSBjoern A. Zeeb prev_dma_idx = dev->mt76.tx_dma_idx[i];
3536c92544dSBjoern A. Zeeb dma_idx = readl(&q->regs->dma_idx);
3546c92544dSBjoern A. Zeeb dev->mt76.tx_dma_idx[i] = dma_idx;
3556c92544dSBjoern A. Zeeb
3566c92544dSBjoern A. Zeeb if (!q->queued || prev_dma_idx != dma_idx) {
3576c92544dSBjoern A. Zeeb dev->tx_hang_check[i] = 0;
3586c92544dSBjoern A. Zeeb continue;
3596c92544dSBjoern A. Zeeb }
3606c92544dSBjoern A. Zeeb
3616c92544dSBjoern A. Zeeb if (++dev->tx_hang_check[i] >= MT_TX_HANG_TH)
3626c92544dSBjoern A. Zeeb return true;
3636c92544dSBjoern A. Zeeb }
3646c92544dSBjoern A. Zeeb
3656c92544dSBjoern A. Zeeb return false;
3666c92544dSBjoern A. Zeeb }
3676c92544dSBjoern A. Zeeb
mt76x02_key_sync(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_sta * sta,struct ieee80211_key_conf * key,void * data)3686c92544dSBjoern A. Zeeb static void mt76x02_key_sync(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
3696c92544dSBjoern A. Zeeb struct ieee80211_sta *sta,
3706c92544dSBjoern A. Zeeb struct ieee80211_key_conf *key, void *data)
3716c92544dSBjoern A. Zeeb {
3726c92544dSBjoern A. Zeeb struct mt76x02_dev *dev = hw->priv;
3736c92544dSBjoern A. Zeeb struct mt76_wcid *wcid;
3746c92544dSBjoern A. Zeeb
3756c92544dSBjoern A. Zeeb if (!sta)
3766c92544dSBjoern A. Zeeb return;
3776c92544dSBjoern A. Zeeb
3786c92544dSBjoern A. Zeeb wcid = (struct mt76_wcid *)sta->drv_priv;
3796c92544dSBjoern A. Zeeb
3806c92544dSBjoern A. Zeeb if (wcid->hw_key_idx != key->keyidx || wcid->sw_iv)
3816c92544dSBjoern A. Zeeb return;
3826c92544dSBjoern A. Zeeb
3836c92544dSBjoern A. Zeeb mt76x02_mac_wcid_sync_pn(dev, wcid->idx, key);
3846c92544dSBjoern A. Zeeb }
3856c92544dSBjoern A. Zeeb
mt76x02_reset_state(struct mt76x02_dev * dev)3866c92544dSBjoern A. Zeeb static void mt76x02_reset_state(struct mt76x02_dev *dev)
3876c92544dSBjoern A. Zeeb {
3886c92544dSBjoern A. Zeeb int i;
3896c92544dSBjoern A. Zeeb
3906c92544dSBjoern A. Zeeb lockdep_assert_held(&dev->mt76.mutex);
3916c92544dSBjoern A. Zeeb
3926c92544dSBjoern A. Zeeb clear_bit(MT76_STATE_RUNNING, &dev->mphy.state);
3936c92544dSBjoern A. Zeeb
3946c92544dSBjoern A. Zeeb rcu_read_lock();
3956c92544dSBjoern A. Zeeb ieee80211_iter_keys_rcu(dev->mt76.hw, NULL, mt76x02_key_sync, NULL);
3966c92544dSBjoern A. Zeeb rcu_read_unlock();
3976c92544dSBjoern A. Zeeb
3986c92544dSBjoern A. Zeeb for (i = 0; i < MT76x02_N_WCIDS; i++) {
3996c92544dSBjoern A. Zeeb struct ieee80211_sta *sta;
4006c92544dSBjoern A. Zeeb struct ieee80211_vif *vif;
4016c92544dSBjoern A. Zeeb struct mt76x02_sta *msta;
4026c92544dSBjoern A. Zeeb struct mt76_wcid *wcid;
4036c92544dSBjoern A. Zeeb void *priv;
4046c92544dSBjoern A. Zeeb
4056c92544dSBjoern A. Zeeb wcid = rcu_dereference_protected(dev->mt76.wcid[i],
4066c92544dSBjoern A. Zeeb lockdep_is_held(&dev->mt76.mutex));
4076c92544dSBjoern A. Zeeb if (!wcid)
4086c92544dSBjoern A. Zeeb continue;
4096c92544dSBjoern A. Zeeb
4106c92544dSBjoern A. Zeeb rcu_assign_pointer(dev->mt76.wcid[i], NULL);
4116c92544dSBjoern A. Zeeb
4126c92544dSBjoern A. Zeeb priv = msta = container_of(wcid, struct mt76x02_sta, wcid);
4136c92544dSBjoern A. Zeeb sta = container_of(priv, struct ieee80211_sta, drv_priv);
4146c92544dSBjoern A. Zeeb
4156c92544dSBjoern A. Zeeb priv = msta->vif;
4166c92544dSBjoern A. Zeeb vif = container_of(priv, struct ieee80211_vif, drv_priv);
4176c92544dSBjoern A. Zeeb
4186c92544dSBjoern A. Zeeb __mt76_sta_remove(&dev->mt76, vif, sta);
4196c92544dSBjoern A. Zeeb memset(msta, 0, sizeof(*msta));
4206c92544dSBjoern A. Zeeb }
4216c92544dSBjoern A. Zeeb
4226c92544dSBjoern A. Zeeb dev->mt76.vif_mask = 0;
4236c92544dSBjoern A. Zeeb dev->mt76.beacon_mask = 0;
4246c92544dSBjoern A. Zeeb }
4256c92544dSBjoern A. Zeeb
mt76x02_watchdog_reset(struct mt76x02_dev * dev)4266c92544dSBjoern A. Zeeb static void mt76x02_watchdog_reset(struct mt76x02_dev *dev)
4276c92544dSBjoern A. Zeeb {
4286c92544dSBjoern A. Zeeb u32 mask = dev->mt76.mmio.irqmask;
4296c92544dSBjoern A. Zeeb bool restart = dev->mt76.mcu_ops->mcu_restart;
4306c92544dSBjoern A. Zeeb int i;
4316c92544dSBjoern A. Zeeb
4326c92544dSBjoern A. Zeeb ieee80211_stop_queues(dev->mt76.hw);
4336c92544dSBjoern A. Zeeb set_bit(MT76_RESET, &dev->mphy.state);
4346c92544dSBjoern A. Zeeb
4356c92544dSBjoern A. Zeeb tasklet_disable(&dev->mt76.pre_tbtt_tasklet);
4366c92544dSBjoern A. Zeeb mt76_worker_disable(&dev->mt76.tx_worker);
4376c92544dSBjoern A. Zeeb napi_disable(&dev->mt76.tx_napi);
4386c92544dSBjoern A. Zeeb
4396c92544dSBjoern A. Zeeb mt76_for_each_q_rx(&dev->mt76, i) {
4406c92544dSBjoern A. Zeeb napi_disable(&dev->mt76.napi[i]);
4416c92544dSBjoern A. Zeeb }
4426c92544dSBjoern A. Zeeb
4436c92544dSBjoern A. Zeeb mutex_lock(&dev->mt76.mutex);
4446c92544dSBjoern A. Zeeb
4456c92544dSBjoern A. Zeeb dev->mcu_timeout = 0;
4466c92544dSBjoern A. Zeeb if (restart)
4476c92544dSBjoern A. Zeeb mt76x02_reset_state(dev);
4486c92544dSBjoern A. Zeeb
4496c92544dSBjoern A. Zeeb if (dev->mt76.beacon_mask)
4506c92544dSBjoern A. Zeeb mt76_clear(dev, MT_BEACON_TIME_CFG,
4516c92544dSBjoern A. Zeeb MT_BEACON_TIME_CFG_BEACON_TX |
4526c92544dSBjoern A. Zeeb MT_BEACON_TIME_CFG_TBTT_EN);
4536c92544dSBjoern A. Zeeb
4546c92544dSBjoern A. Zeeb mt76x02_irq_disable(dev, mask);
4556c92544dSBjoern A. Zeeb
4566c92544dSBjoern A. Zeeb /* perform device reset */
4576c92544dSBjoern A. Zeeb mt76_clear(dev, MT_TXOP_CTRL_CFG, MT_TXOP_ED_CCA_EN);
4586c92544dSBjoern A. Zeeb mt76_wr(dev, MT_MAC_SYS_CTRL, 0);
4596c92544dSBjoern A. Zeeb mt76_clear(dev, MT_WPDMA_GLO_CFG,
4606c92544dSBjoern A. Zeeb MT_WPDMA_GLO_CFG_TX_DMA_EN | MT_WPDMA_GLO_CFG_RX_DMA_EN);
4616c92544dSBjoern A. Zeeb usleep_range(5000, 10000);
4626c92544dSBjoern A. Zeeb mt76_wr(dev, MT_INT_SOURCE_CSR, 0xffffffff);
4636c92544dSBjoern A. Zeeb
4646c92544dSBjoern A. Zeeb /* let fw reset DMA */
4656c92544dSBjoern A. Zeeb mt76_set(dev, 0x734, 0x3);
4666c92544dSBjoern A. Zeeb
4676c92544dSBjoern A. Zeeb if (restart)
4686c92544dSBjoern A. Zeeb mt76_mcu_restart(dev);
4696c92544dSBjoern A. Zeeb
4706c92544dSBjoern A. Zeeb mt76_queue_tx_cleanup(dev, dev->mt76.q_mcu[MT_MCUQ_WM], true);
4716c92544dSBjoern A. Zeeb for (i = 0; i < __MT_TXQ_MAX; i++)
4726c92544dSBjoern A. Zeeb mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[i], true);
4736c92544dSBjoern A. Zeeb
4746c92544dSBjoern A. Zeeb mt76_for_each_q_rx(&dev->mt76, i) {
4756c92544dSBjoern A. Zeeb mt76_queue_rx_reset(dev, i);
4766c92544dSBjoern A. Zeeb }
4776c92544dSBjoern A. Zeeb
4786c92544dSBjoern A. Zeeb mt76_tx_status_check(&dev->mt76, true);
4796c92544dSBjoern A. Zeeb
4806c92544dSBjoern A. Zeeb mt76x02_mac_start(dev);
4816c92544dSBjoern A. Zeeb
4826c92544dSBjoern A. Zeeb if (dev->ed_monitor)
4836c92544dSBjoern A. Zeeb mt76_set(dev, MT_TXOP_CTRL_CFG, MT_TXOP_ED_CCA_EN);
4846c92544dSBjoern A. Zeeb
4856c92544dSBjoern A. Zeeb if (dev->mt76.beacon_mask && !restart)
4866c92544dSBjoern A. Zeeb mt76_set(dev, MT_BEACON_TIME_CFG,
4876c92544dSBjoern A. Zeeb MT_BEACON_TIME_CFG_BEACON_TX |
4886c92544dSBjoern A. Zeeb MT_BEACON_TIME_CFG_TBTT_EN);
4896c92544dSBjoern A. Zeeb
4906c92544dSBjoern A. Zeeb mt76x02_irq_enable(dev, mask);
4916c92544dSBjoern A. Zeeb
4926c92544dSBjoern A. Zeeb mutex_unlock(&dev->mt76.mutex);
4936c92544dSBjoern A. Zeeb
4946c92544dSBjoern A. Zeeb clear_bit(MT76_RESET, &dev->mphy.state);
4956c92544dSBjoern A. Zeeb
4966c92544dSBjoern A. Zeeb mt76_worker_enable(&dev->mt76.tx_worker);
4976c92544dSBjoern A. Zeeb tasklet_enable(&dev->mt76.pre_tbtt_tasklet);
4986c92544dSBjoern A. Zeeb
4996c92544dSBjoern A. Zeeb local_bh_disable();
5006c92544dSBjoern A. Zeeb napi_enable(&dev->mt76.tx_napi);
5016c92544dSBjoern A. Zeeb napi_schedule(&dev->mt76.tx_napi);
5026c92544dSBjoern A. Zeeb
5036c92544dSBjoern A. Zeeb mt76_for_each_q_rx(&dev->mt76, i) {
5046c92544dSBjoern A. Zeeb napi_enable(&dev->mt76.napi[i]);
5056c92544dSBjoern A. Zeeb napi_schedule(&dev->mt76.napi[i]);
5066c92544dSBjoern A. Zeeb }
5076c92544dSBjoern A. Zeeb local_bh_enable();
5086c92544dSBjoern A. Zeeb
5096c92544dSBjoern A. Zeeb if (restart) {
5106c92544dSBjoern A. Zeeb set_bit(MT76_RESTART, &dev->mphy.state);
5116c92544dSBjoern A. Zeeb mt76x02_mcu_function_select(dev, Q_SELECT, 1);
5126c92544dSBjoern A. Zeeb ieee80211_restart_hw(dev->mt76.hw);
5136c92544dSBjoern A. Zeeb } else {
5146c92544dSBjoern A. Zeeb ieee80211_wake_queues(dev->mt76.hw);
5156c92544dSBjoern A. Zeeb mt76_txq_schedule_all(&dev->mphy);
5166c92544dSBjoern A. Zeeb }
5176c92544dSBjoern A. Zeeb }
5186c92544dSBjoern A. Zeeb
mt76x02_reconfig_complete(struct ieee80211_hw * hw,enum ieee80211_reconfig_type reconfig_type)5196c92544dSBjoern A. Zeeb void mt76x02_reconfig_complete(struct ieee80211_hw *hw,
5206c92544dSBjoern A. Zeeb enum ieee80211_reconfig_type reconfig_type)
5216c92544dSBjoern A. Zeeb {
5226c92544dSBjoern A. Zeeb struct mt76x02_dev *dev = hw->priv;
5236c92544dSBjoern A. Zeeb
5246c92544dSBjoern A. Zeeb if (reconfig_type != IEEE80211_RECONFIG_TYPE_RESTART)
5256c92544dSBjoern A. Zeeb return;
5266c92544dSBjoern A. Zeeb
5276c92544dSBjoern A. Zeeb clear_bit(MT76_RESTART, &dev->mphy.state);
5286c92544dSBjoern A. Zeeb }
5296c92544dSBjoern A. Zeeb EXPORT_SYMBOL_GPL(mt76x02_reconfig_complete);
5306c92544dSBjoern A. Zeeb
mt76x02_check_tx_hang(struct mt76x02_dev * dev)5316c92544dSBjoern A. Zeeb static void mt76x02_check_tx_hang(struct mt76x02_dev *dev)
5326c92544dSBjoern A. Zeeb {
5336c92544dSBjoern A. Zeeb if (test_bit(MT76_RESTART, &dev->mphy.state))
5346c92544dSBjoern A. Zeeb return;
5356c92544dSBjoern A. Zeeb
5366c92544dSBjoern A. Zeeb if (!mt76x02_tx_hang(dev) && !dev->mcu_timeout)
5376c92544dSBjoern A. Zeeb return;
5386c92544dSBjoern A. Zeeb
5396c92544dSBjoern A. Zeeb mt76x02_watchdog_reset(dev);
5406c92544dSBjoern A. Zeeb
5416c92544dSBjoern A. Zeeb dev->tx_hang_reset++;
5426c92544dSBjoern A. Zeeb memset(dev->tx_hang_check, 0, sizeof(dev->tx_hang_check));
5436c92544dSBjoern A. Zeeb memset(dev->mt76.tx_dma_idx, 0xff,
5446c92544dSBjoern A. Zeeb sizeof(dev->mt76.tx_dma_idx));
5456c92544dSBjoern A. Zeeb }
5466c92544dSBjoern A. Zeeb
mt76x02_wdt_work(struct work_struct * work)5476c92544dSBjoern A. Zeeb void mt76x02_wdt_work(struct work_struct *work)
5486c92544dSBjoern A. Zeeb {
5496c92544dSBjoern A. Zeeb struct mt76x02_dev *dev = container_of(work, struct mt76x02_dev,
5506c92544dSBjoern A. Zeeb wdt_work.work);
5516c92544dSBjoern A. Zeeb
5526c92544dSBjoern A. Zeeb mt76x02_check_tx_hang(dev);
5536c92544dSBjoern A. Zeeb
5546c92544dSBjoern A. Zeeb ieee80211_queue_delayed_work(mt76_hw(dev), &dev->wdt_work,
5556c92544dSBjoern A. Zeeb MT_WATCHDOG_TIME);
5566c92544dSBjoern A. Zeeb }
557