16c92544dSBjoern A. Zeeb /* SPDX-License-Identifier: ISC */ 26c92544dSBjoern A. Zeeb /* 36c92544dSBjoern A. Zeeb * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name> 46c92544dSBjoern A. Zeeb */ 56c92544dSBjoern A. Zeeb 66c92544dSBjoern A. Zeeb #ifndef __MT76X02_REGS_H 76c92544dSBjoern A. Zeeb #define __MT76X02_REGS_H 86c92544dSBjoern A. Zeeb 96c92544dSBjoern A. Zeeb #define MT_ASIC_VERSION 0x0000 106c92544dSBjoern A. Zeeb 116c92544dSBjoern A. Zeeb #define MT76XX_REV_E3 0x22 126c92544dSBjoern A. Zeeb #define MT76XX_REV_E4 0x33 136c92544dSBjoern A. Zeeb 146c92544dSBjoern A. Zeeb #define MT_CMB_CTRL 0x0020 156c92544dSBjoern A. Zeeb #define MT_CMB_CTRL_XTAL_RDY BIT(22) 166c92544dSBjoern A. Zeeb #define MT_CMB_CTRL_PLL_LD BIT(23) 176c92544dSBjoern A. Zeeb 186c92544dSBjoern A. Zeeb #define MT_EFUSE_CTRL 0x0024 196c92544dSBjoern A. Zeeb #define MT_EFUSE_CTRL_AOUT GENMASK(5, 0) 206c92544dSBjoern A. Zeeb #define MT_EFUSE_CTRL_MODE GENMASK(7, 6) 216c92544dSBjoern A. Zeeb #define MT_EFUSE_CTRL_LDO_OFF_TIME GENMASK(13, 8) 226c92544dSBjoern A. Zeeb #define MT_EFUSE_CTRL_LDO_ON_TIME GENMASK(15, 14) 236c92544dSBjoern A. Zeeb #define MT_EFUSE_CTRL_AIN GENMASK(25, 16) 246c92544dSBjoern A. Zeeb #define MT_EFUSE_CTRL_KICK BIT(30) 256c92544dSBjoern A. Zeeb #define MT_EFUSE_CTRL_SEL BIT(31) 266c92544dSBjoern A. Zeeb 276c92544dSBjoern A. Zeeb #define MT_EFUSE_DATA_BASE 0x0028 286c92544dSBjoern A. Zeeb #define MT_EFUSE_DATA(_n) (MT_EFUSE_DATA_BASE + ((_n) << 2)) 296c92544dSBjoern A. Zeeb 306c92544dSBjoern A. Zeeb #define MT_COEXCFG0 0x0040 316c92544dSBjoern A. Zeeb #define MT_COEXCFG0_COEX_EN BIT(0) 326c92544dSBjoern A. Zeeb 336c92544dSBjoern A. Zeeb #define MT_WLAN_FUN_CTRL 0x0080 346c92544dSBjoern A. Zeeb #define MT_WLAN_FUN_CTRL_WLAN_EN BIT(0) 356c92544dSBjoern A. Zeeb #define MT_WLAN_FUN_CTRL_WLAN_CLK_EN BIT(1) 366c92544dSBjoern A. Zeeb #define MT_WLAN_FUN_CTRL_WLAN_RESET_RF BIT(2) 376c92544dSBjoern A. Zeeb 386c92544dSBjoern A. Zeeb #define MT_COEXCFG3 0x004c 396c92544dSBjoern A. Zeeb 406c92544dSBjoern A. Zeeb #define MT_LDO_CTRL_0 0x006c 416c92544dSBjoern A. Zeeb #define MT_LDO_CTRL_1 0x0070 426c92544dSBjoern A. Zeeb 436c92544dSBjoern A. Zeeb #define MT_WLAN_FUN_CTRL_WLAN_RESET BIT(3) /* MT76x0 */ 446c92544dSBjoern A. Zeeb #define MT_WLAN_FUN_CTRL_CSR_F20M_CKEN BIT(3) /* MT76x2 */ 456c92544dSBjoern A. Zeeb 466c92544dSBjoern A. Zeeb #define MT_WLAN_FUN_CTRL_PCIE_CLK_REQ BIT(4) 476c92544dSBjoern A. Zeeb #define MT_WLAN_FUN_CTRL_FRC_WL_ANT_SEL BIT(5) 486c92544dSBjoern A. Zeeb #define MT_WLAN_FUN_CTRL_INV_ANT_SEL BIT(6) 496c92544dSBjoern A. Zeeb #define MT_WLAN_FUN_CTRL_WAKE_HOST BIT(7) 506c92544dSBjoern A. Zeeb 516c92544dSBjoern A. Zeeb #define MT_WLAN_FUN_CTRL_THERM_RST BIT(8) /* MT76x2 */ 526c92544dSBjoern A. Zeeb #define MT_WLAN_FUN_CTRL_THERM_CKEN BIT(9) /* MT76x2 */ 536c92544dSBjoern A. Zeeb 546c92544dSBjoern A. Zeeb #define MT_WLAN_FUN_CTRL_GPIO_IN GENMASK(15, 8) /* MT76x0 */ 556c92544dSBjoern A. Zeeb #define MT_WLAN_FUN_CTRL_GPIO_OUT GENMASK(23, 16) /* MT76x0 */ 566c92544dSBjoern A. Zeeb #define MT_WLAN_FUN_CTRL_GPIO_OUT_EN GENMASK(31, 24) /* MT76x0 */ 576c92544dSBjoern A. Zeeb 586c92544dSBjoern A. Zeeb /* MT76x0 */ 596c92544dSBjoern A. Zeeb #define MT_CSR_EE_CFG1 0x0104 606c92544dSBjoern A. Zeeb 616c92544dSBjoern A. Zeeb #define MT_XO_CTRL0 0x0100 626c92544dSBjoern A. Zeeb #define MT_XO_CTRL1 0x0104 636c92544dSBjoern A. Zeeb #define MT_XO_CTRL2 0x0108 646c92544dSBjoern A. Zeeb #define MT_XO_CTRL3 0x010c 656c92544dSBjoern A. Zeeb #define MT_XO_CTRL4 0x0110 666c92544dSBjoern A. Zeeb 676c92544dSBjoern A. Zeeb #define MT_XO_CTRL5 0x0114 686c92544dSBjoern A. Zeeb #define MT_XO_CTRL5_C2_VAL GENMASK(14, 8) 696c92544dSBjoern A. Zeeb 706c92544dSBjoern A. Zeeb #define MT_XO_CTRL6 0x0118 716c92544dSBjoern A. Zeeb #define MT_XO_CTRL6_C2_CTRL GENMASK(14, 8) 726c92544dSBjoern A. Zeeb 736c92544dSBjoern A. Zeeb #define MT_XO_CTRL7 0x011c 746c92544dSBjoern A. Zeeb 756c92544dSBjoern A. Zeeb #define MT_IOCFG_6 0x0124 766c92544dSBjoern A. Zeeb 776c92544dSBjoern A. Zeeb #define MT_USB_U3DMA_CFG 0x9018 786c92544dSBjoern A. Zeeb #define MT_USB_DMA_CFG_RX_BULK_AGG_TOUT GENMASK(7, 0) 796c92544dSBjoern A. Zeeb #define MT_USB_DMA_CFG_RX_BULK_AGG_LMT GENMASK(15, 8) 806c92544dSBjoern A. Zeeb #define MT_USB_DMA_CFG_UDMA_TX_WL_DROP BIT(16) 816c92544dSBjoern A. Zeeb #define MT_USB_DMA_CFG_WAKE_UP_EN BIT(17) 826c92544dSBjoern A. Zeeb #define MT_USB_DMA_CFG_RX_DROP_OR_PAD BIT(18) 836c92544dSBjoern A. Zeeb #define MT_USB_DMA_CFG_TX_CLR BIT(19) 846c92544dSBjoern A. Zeeb #define MT_USB_DMA_CFG_TXOP_HALT BIT(20) 856c92544dSBjoern A. Zeeb #define MT_USB_DMA_CFG_RX_BULK_AGG_EN BIT(21) 866c92544dSBjoern A. Zeeb #define MT_USB_DMA_CFG_RX_BULK_EN BIT(22) 876c92544dSBjoern A. Zeeb #define MT_USB_DMA_CFG_TX_BULK_EN BIT(23) 886c92544dSBjoern A. Zeeb #define MT_USB_DMA_CFG_EP_OUT_VALID GENMASK(29, 24) 896c92544dSBjoern A. Zeeb #define MT_USB_DMA_CFG_RX_BUSY BIT(30) 906c92544dSBjoern A. Zeeb #define MT_USB_DMA_CFG_TX_BUSY BIT(31) 916c92544dSBjoern A. Zeeb 926c92544dSBjoern A. Zeeb #define MT_WLAN_MTC_CTRL 0x10148 936c92544dSBjoern A. Zeeb #define MT_WLAN_MTC_CTRL_MTCMOS_PWR_UP BIT(0) 946c92544dSBjoern A. Zeeb #define MT_WLAN_MTC_CTRL_PWR_ACK BIT(12) 956c92544dSBjoern A. Zeeb #define MT_WLAN_MTC_CTRL_PWR_ACK_S BIT(13) 966c92544dSBjoern A. Zeeb #define MT_WLAN_MTC_CTRL_BBP_MEM_PD GENMASK(19, 16) 976c92544dSBjoern A. Zeeb #define MT_WLAN_MTC_CTRL_PBF_MEM_PD BIT(20) 986c92544dSBjoern A. Zeeb #define MT_WLAN_MTC_CTRL_FCE_MEM_PD BIT(21) 996c92544dSBjoern A. Zeeb #define MT_WLAN_MTC_CTRL_TSO_MEM_PD BIT(22) 1006c92544dSBjoern A. Zeeb #define MT_WLAN_MTC_CTRL_BBP_MEM_RB BIT(24) 1016c92544dSBjoern A. Zeeb #define MT_WLAN_MTC_CTRL_PBF_MEM_RB BIT(25) 1026c92544dSBjoern A. Zeeb #define MT_WLAN_MTC_CTRL_FCE_MEM_RB BIT(26) 1036c92544dSBjoern A. Zeeb #define MT_WLAN_MTC_CTRL_TSO_MEM_RB BIT(27) 1046c92544dSBjoern A. Zeeb #define MT_WLAN_MTC_CTRL_STATE_UP BIT(28) 1056c92544dSBjoern A. Zeeb 1066c92544dSBjoern A. Zeeb #define MT_INT_SOURCE_CSR 0x0200 1076c92544dSBjoern A. Zeeb #define MT_INT_MASK_CSR 0x0204 1086c92544dSBjoern A. Zeeb 1096c92544dSBjoern A. Zeeb #define MT_INT_RX_DONE(_n) BIT(_n) 1106c92544dSBjoern A. Zeeb #define MT_INT_RX_DONE_ALL GENMASK(1, 0) 1116c92544dSBjoern A. Zeeb #define MT_INT_TX_DONE_ALL GENMASK(13, 4) 1126c92544dSBjoern A. Zeeb #define MT_INT_TX_DONE(_n) BIT((_n) + 4) 1136c92544dSBjoern A. Zeeb #define MT_INT_RX_COHERENT BIT(16) 1146c92544dSBjoern A. Zeeb #define MT_INT_TX_COHERENT BIT(17) 1156c92544dSBjoern A. Zeeb #define MT_INT_ANY_COHERENT BIT(18) 1166c92544dSBjoern A. Zeeb #define MT_INT_MCU_CMD BIT(19) 1176c92544dSBjoern A. Zeeb #define MT_INT_TBTT BIT(20) 1186c92544dSBjoern A. Zeeb #define MT_INT_PRE_TBTT BIT(21) 1196c92544dSBjoern A. Zeeb #define MT_INT_TX_STAT BIT(22) 1206c92544dSBjoern A. Zeeb #define MT_INT_AUTO_WAKEUP BIT(23) 1216c92544dSBjoern A. Zeeb #define MT_INT_GPTIMER BIT(24) 1226c92544dSBjoern A. Zeeb #define MT_INT_RXDELAYINT BIT(26) 1236c92544dSBjoern A. Zeeb #define MT_INT_TXDELAYINT BIT(27) 1246c92544dSBjoern A. Zeeb 1256c92544dSBjoern A. Zeeb #define MT_WPDMA_GLO_CFG 0x0208 1266c92544dSBjoern A. Zeeb #define MT_WPDMA_GLO_CFG_TX_DMA_EN BIT(0) 1276c92544dSBjoern A. Zeeb #define MT_WPDMA_GLO_CFG_TX_DMA_BUSY BIT(1) 1286c92544dSBjoern A. Zeeb #define MT_WPDMA_GLO_CFG_RX_DMA_EN BIT(2) 1296c92544dSBjoern A. Zeeb #define MT_WPDMA_GLO_CFG_RX_DMA_BUSY BIT(3) 1306c92544dSBjoern A. Zeeb #define MT_WPDMA_GLO_CFG_DMA_BURST_SIZE GENMASK(5, 4) 1316c92544dSBjoern A. Zeeb #define MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE BIT(6) 1326c92544dSBjoern A. Zeeb #define MT_WPDMA_GLO_CFG_BIG_ENDIAN BIT(7) 1336c92544dSBjoern A. Zeeb #define MT_WPDMA_GLO_CFG_HDR_SEG_LEN GENMASK(15, 8) 1346c92544dSBjoern A. Zeeb #define MT_WPDMA_GLO_CFG_CLK_GATE_DIS BIT(30) 1356c92544dSBjoern A. Zeeb #define MT_WPDMA_GLO_CFG_RX_2B_OFFSET BIT(31) 1366c92544dSBjoern A. Zeeb 1376c92544dSBjoern A. Zeeb #define MT_WPDMA_RST_IDX 0x020c 1386c92544dSBjoern A. Zeeb 1396c92544dSBjoern A. Zeeb #define MT_WPDMA_DELAY_INT_CFG 0x0210 1406c92544dSBjoern A. Zeeb 1416c92544dSBjoern A. Zeeb #define MT_WMM_AIFSN 0x0214 1426c92544dSBjoern A. Zeeb #define MT_WMM_AIFSN_MASK GENMASK(3, 0) 1436c92544dSBjoern A. Zeeb #define MT_WMM_AIFSN_SHIFT(_n) ((_n) * 4) 1446c92544dSBjoern A. Zeeb 1456c92544dSBjoern A. Zeeb #define MT_WMM_CWMIN 0x0218 1466c92544dSBjoern A. Zeeb #define MT_WMM_CWMIN_MASK GENMASK(3, 0) 1476c92544dSBjoern A. Zeeb #define MT_WMM_CWMIN_SHIFT(_n) ((_n) * 4) 1486c92544dSBjoern A. Zeeb 1496c92544dSBjoern A. Zeeb #define MT_WMM_CWMAX 0x021c 1506c92544dSBjoern A. Zeeb #define MT_WMM_CWMAX_MASK GENMASK(3, 0) 1516c92544dSBjoern A. Zeeb #define MT_WMM_CWMAX_SHIFT(_n) ((_n) * 4) 1526c92544dSBjoern A. Zeeb 1536c92544dSBjoern A. Zeeb #define MT_WMM_TXOP_BASE 0x0220 1546c92544dSBjoern A. Zeeb #define MT_WMM_TXOP(_n) (MT_WMM_TXOP_BASE + (((_n) / 2) << 2)) 1556c92544dSBjoern A. Zeeb #define MT_WMM_TXOP_SHIFT(_n) (((_n) & 1) * 16) 1566c92544dSBjoern A. Zeeb #define MT_WMM_TXOP_MASK GENMASK(15, 0) 1576c92544dSBjoern A. Zeeb 1586c92544dSBjoern A. Zeeb #define MT_WMM_CTRL 0x0230 /* MT76x0 */ 1596c92544dSBjoern A. Zeeb #define MT_FCE_DMA_ADDR 0x0230 1606c92544dSBjoern A. Zeeb #define MT_FCE_DMA_LEN 0x0234 1616c92544dSBjoern A. Zeeb #define MT_USB_DMA_CFG 0x0238 1626c92544dSBjoern A. Zeeb 1636c92544dSBjoern A. Zeeb #define MT_TSO_CTRL 0x0250 1646c92544dSBjoern A. Zeeb #define MT_HEADER_TRANS_CTRL_REG 0x0260 1656c92544dSBjoern A. Zeeb 1666c92544dSBjoern A. Zeeb #define MT_US_CYC_CFG 0x02a4 1676c92544dSBjoern A. Zeeb #define MT_US_CYC_CNT GENMASK(7, 0) 1686c92544dSBjoern A. Zeeb 1696c92544dSBjoern A. Zeeb #define MT_TX_RING_BASE 0x0300 1706c92544dSBjoern A. Zeeb #define MT_RX_RING_BASE 0x03c0 1716c92544dSBjoern A. Zeeb 1726c92544dSBjoern A. Zeeb #define MT_TX_HW_QUEUE_MCU 8 1736c92544dSBjoern A. Zeeb #define MT_TX_HW_QUEUE_MGMT 9 1746c92544dSBjoern A. Zeeb 1756c92544dSBjoern A. Zeeb #define MT_PBF_SYS_CTRL 0x0400 1766c92544dSBjoern A. Zeeb #define MT_PBF_SYS_CTRL_MCU_RESET BIT(0) 1776c92544dSBjoern A. Zeeb #define MT_PBF_SYS_CTRL_DMA_RESET BIT(1) 1786c92544dSBjoern A. Zeeb #define MT_PBF_SYS_CTRL_MAC_RESET BIT(2) 1796c92544dSBjoern A. Zeeb #define MT_PBF_SYS_CTRL_PBF_RESET BIT(3) 1806c92544dSBjoern A. Zeeb #define MT_PBF_SYS_CTRL_ASY_RESET BIT(4) 1816c92544dSBjoern A. Zeeb 1826c92544dSBjoern A. Zeeb #define MT_PBF_CFG 0x0404 1836c92544dSBjoern A. Zeeb #define MT_PBF_CFG_TX0Q_EN BIT(0) 1846c92544dSBjoern A. Zeeb #define MT_PBF_CFG_TX1Q_EN BIT(1) 1856c92544dSBjoern A. Zeeb #define MT_PBF_CFG_TX2Q_EN BIT(2) 1866c92544dSBjoern A. Zeeb #define MT_PBF_CFG_TX3Q_EN BIT(3) 1876c92544dSBjoern A. Zeeb #define MT_PBF_CFG_RX0Q_EN BIT(4) 1886c92544dSBjoern A. Zeeb #define MT_PBF_CFG_RX_DROP_EN BIT(8) 1896c92544dSBjoern A. Zeeb 1906c92544dSBjoern A. Zeeb #define MT_PBF_TX_MAX_PCNT 0x0408 1916c92544dSBjoern A. Zeeb #define MT_PBF_RX_MAX_PCNT 0x040c 1926c92544dSBjoern A. Zeeb 1936c92544dSBjoern A. Zeeb #define MT_BCN_OFFSET_BASE 0x041c 1946c92544dSBjoern A. Zeeb #define MT_BCN_OFFSET(_n) (MT_BCN_OFFSET_BASE + ((_n) << 2)) 1956c92544dSBjoern A. Zeeb 1966c92544dSBjoern A. Zeeb #define MT_RXQ_STA 0x0430 1976c92544dSBjoern A. Zeeb #define MT_TXQ_STA 0x0434 1986c92544dSBjoern A. Zeeb #define MT_RF_CSR_CFG 0x0500 1996c92544dSBjoern A. Zeeb #define MT_RF_CSR_CFG_DATA GENMASK(7, 0) 2006c92544dSBjoern A. Zeeb #define MT_RF_CSR_CFG_REG_ID GENMASK(14, 8) 2016c92544dSBjoern A. Zeeb #define MT_RF_CSR_CFG_REG_BANK GENMASK(17, 15) 2026c92544dSBjoern A. Zeeb #define MT_RF_CSR_CFG_WR BIT(30) 2036c92544dSBjoern A. Zeeb #define MT_RF_CSR_CFG_KICK BIT(31) 2046c92544dSBjoern A. Zeeb 2056c92544dSBjoern A. Zeeb #define MT_RF_BYPASS_0 0x0504 2066c92544dSBjoern A. Zeeb #define MT_RF_BYPASS_1 0x0508 2076c92544dSBjoern A. Zeeb #define MT_RF_SETTING_0 0x050c 2086c92544dSBjoern A. Zeeb 2096c92544dSBjoern A. Zeeb #define MT_RF_MISC 0x0518 2106c92544dSBjoern A. Zeeb #define MT_RF_DATA_WRITE 0x0524 2116c92544dSBjoern A. Zeeb 2126c92544dSBjoern A. Zeeb #define MT_RF_CTRL 0x0528 2136c92544dSBjoern A. Zeeb #define MT_RF_CTRL_ADDR GENMASK(11, 0) 2146c92544dSBjoern A. Zeeb #define MT_RF_CTRL_WRITE BIT(12) 2156c92544dSBjoern A. Zeeb #define MT_RF_CTRL_BUSY BIT(13) 2166c92544dSBjoern A. Zeeb #define MT_RF_CTRL_IDX BIT(16) 2176c92544dSBjoern A. Zeeb 2186c92544dSBjoern A. Zeeb #define MT_RF_DATA_READ 0x052c 2196c92544dSBjoern A. Zeeb 2206c92544dSBjoern A. Zeeb #define MT_COM_REG0 0x0730 2216c92544dSBjoern A. Zeeb #define MT_COM_REG1 0x0734 2226c92544dSBjoern A. Zeeb #define MT_COM_REG2 0x0738 2236c92544dSBjoern A. Zeeb #define MT_COM_REG3 0x073C 2246c92544dSBjoern A. Zeeb 2256c92544dSBjoern A. Zeeb #define MT_LED_CTRL 0x0770 2266c92544dSBjoern A. Zeeb #define MT_LED_CTRL_REPLAY(_n) BIT(0 + (8 * (_n))) 2276c92544dSBjoern A. Zeeb #define MT_LED_CTRL_POLARITY(_n) BIT(1 + (8 * (_n))) 2286c92544dSBjoern A. Zeeb #define MT_LED_CTRL_TX_BLINK_MODE(_n) BIT(2 + (8 * (_n))) 2296c92544dSBjoern A. Zeeb #define MT_LED_CTRL_KICK(_n) BIT(7 + (8 * (_n))) 2306c92544dSBjoern A. Zeeb 2316c92544dSBjoern A. Zeeb #define MT_LED_TX_BLINK_0 0x0774 2326c92544dSBjoern A. Zeeb #define MT_LED_TX_BLINK_1 0x0778 2336c92544dSBjoern A. Zeeb 2346c92544dSBjoern A. Zeeb #define MT_LED_S0_BASE 0x077C 2356c92544dSBjoern A. Zeeb #define MT_LED_S0(_n) (MT_LED_S0_BASE + 8 * (_n)) 2366c92544dSBjoern A. Zeeb #define MT_LED_S1_BASE 0x0780 2376c92544dSBjoern A. Zeeb #define MT_LED_S1(_n) (MT_LED_S1_BASE + 8 * (_n)) 2386c92544dSBjoern A. Zeeb #define MT_LED_STATUS_OFF GENMASK(31, 24) 2396c92544dSBjoern A. Zeeb #define MT_LED_STATUS_ON GENMASK(23, 16) 2406c92544dSBjoern A. Zeeb #define MT_LED_STATUS_DURATION GENMASK(15, 8) 2416c92544dSBjoern A. Zeeb 2426c92544dSBjoern A. Zeeb #define MT_FCE_PSE_CTRL 0x0800 2436c92544dSBjoern A. Zeeb #define MT_FCE_PARAMETERS 0x0804 2446c92544dSBjoern A. Zeeb #define MT_FCE_CSO 0x0808 2456c92544dSBjoern A. Zeeb 2466c92544dSBjoern A. Zeeb #define MT_FCE_L2_STUFF 0x080c 2476c92544dSBjoern A. Zeeb #define MT_FCE_L2_STUFF_HT_L2_EN BIT(0) 2486c92544dSBjoern A. Zeeb #define MT_FCE_L2_STUFF_QOS_L2_EN BIT(1) 2496c92544dSBjoern A. Zeeb #define MT_FCE_L2_STUFF_RX_STUFF_EN BIT(2) 2506c92544dSBjoern A. Zeeb #define MT_FCE_L2_STUFF_TX_STUFF_EN BIT(3) 2516c92544dSBjoern A. Zeeb #define MT_FCE_L2_STUFF_WR_MPDU_LEN_EN BIT(4) 2526c92544dSBjoern A. Zeeb #define MT_FCE_L2_STUFF_MVINV_BSWAP BIT(5) 2536c92544dSBjoern A. Zeeb #define MT_FCE_L2_STUFF_TS_CMD_QSEL_EN GENMASK(15, 8) 2546c92544dSBjoern A. Zeeb #define MT_FCE_L2_STUFF_TS_LEN_EN GENMASK(23, 16) 2556c92544dSBjoern A. Zeeb #define MT_FCE_L2_STUFF_OTHER_PORT GENMASK(25, 24) 2566c92544dSBjoern A. Zeeb 2576c92544dSBjoern A. Zeeb #define MT_FCE_WLAN_FLOW_CONTROL1 0x0824 2586c92544dSBjoern A. Zeeb 2596c92544dSBjoern A. Zeeb #define MT_TX_CPU_FROM_FCE_BASE_PTR 0x09a0 2606c92544dSBjoern A. Zeeb #define MT_TX_CPU_FROM_FCE_MAX_COUNT 0x09a4 2616c92544dSBjoern A. Zeeb #define MT_TX_CPU_FROM_FCE_CPU_DESC_IDX 0x09a8 2626c92544dSBjoern A. Zeeb #define MT_FCE_PDMA_GLOBAL_CONF 0x09c4 2636c92544dSBjoern A. Zeeb #define MT_FCE_SKIP_FS 0x0a6c 2646c92544dSBjoern A. Zeeb 2656c92544dSBjoern A. Zeeb #define MT_PAUSE_ENABLE_CONTROL1 0x0a38 2666c92544dSBjoern A. Zeeb 2676c92544dSBjoern A. Zeeb #define MT_MAC_CSR0 0x1000 2686c92544dSBjoern A. Zeeb 2696c92544dSBjoern A. Zeeb #define MT_MAC_SYS_CTRL 0x1004 2706c92544dSBjoern A. Zeeb #define MT_MAC_SYS_CTRL_RESET_CSR BIT(0) 2716c92544dSBjoern A. Zeeb #define MT_MAC_SYS_CTRL_RESET_BBP BIT(1) 2726c92544dSBjoern A. Zeeb #define MT_MAC_SYS_CTRL_ENABLE_TX BIT(2) 2736c92544dSBjoern A. Zeeb #define MT_MAC_SYS_CTRL_ENABLE_RX BIT(3) 2746c92544dSBjoern A. Zeeb 2756c92544dSBjoern A. Zeeb #define MT_MAC_ADDR_DW0 0x1008 2766c92544dSBjoern A. Zeeb #define MT_MAC_ADDR_DW1 0x100c 2776c92544dSBjoern A. Zeeb #define MT_MAC_ADDR_DW1_U2ME_MASK GENMASK(23, 16) 2786c92544dSBjoern A. Zeeb 2796c92544dSBjoern A. Zeeb #define MT_MAC_BSSID_DW0 0x1010 2806c92544dSBjoern A. Zeeb #define MT_MAC_BSSID_DW1 0x1014 2816c92544dSBjoern A. Zeeb #define MT_MAC_BSSID_DW1_ADDR GENMASK(15, 0) 2826c92544dSBjoern A. Zeeb #define MT_MAC_BSSID_DW1_MBSS_MODE GENMASK(17, 16) 2836c92544dSBjoern A. Zeeb #define MT_MAC_BSSID_DW1_MBEACON_N GENMASK(20, 18) 2846c92544dSBjoern A. Zeeb #define MT_MAC_BSSID_DW1_MBSS_LOCAL_BIT BIT(21) 2856c92544dSBjoern A. Zeeb #define MT_MAC_BSSID_DW1_MBSS_MODE_B2 BIT(22) 2866c92544dSBjoern A. Zeeb #define MT_MAC_BSSID_DW1_MBEACON_N_B3 BIT(23) 2876c92544dSBjoern A. Zeeb #define MT_MAC_BSSID_DW1_MBSS_IDX_BYTE GENMASK(26, 24) 2886c92544dSBjoern A. Zeeb 2896c92544dSBjoern A. Zeeb #define MT_MAX_LEN_CFG 0x1018 2906c92544dSBjoern A. Zeeb #define MT_MAX_LEN_CFG_AMPDU GENMASK(13, 12) 2916c92544dSBjoern A. Zeeb 2926c92544dSBjoern A. Zeeb #define MT_LED_CFG 0x102c 2936c92544dSBjoern A. Zeeb 2946c92544dSBjoern A. Zeeb #define MT_AMPDU_MAX_LEN_20M1S 0x1030 2956c92544dSBjoern A. Zeeb #define MT_AMPDU_MAX_LEN_20M2S 0x1034 2966c92544dSBjoern A. Zeeb #define MT_AMPDU_MAX_LEN_40M1S 0x1038 2976c92544dSBjoern A. Zeeb #define MT_AMPDU_MAX_LEN_40M2S 0x103c 2986c92544dSBjoern A. Zeeb #define MT_AMPDU_MAX_LEN 0x1040 2996c92544dSBjoern A. Zeeb 3006c92544dSBjoern A. Zeeb #define MT_WCID_DROP_BASE 0x106c 3016c92544dSBjoern A. Zeeb #define MT_WCID_DROP(_n) (MT_WCID_DROP_BASE + ((_n) >> 5) * 4) 3026c92544dSBjoern A. Zeeb #define MT_WCID_DROP_MASK(_n) BIT((_n) % 32) 3036c92544dSBjoern A. Zeeb 3046c92544dSBjoern A. Zeeb #define MT_BCN_BYPASS_MASK 0x108c 3056c92544dSBjoern A. Zeeb 3066c92544dSBjoern A. Zeeb #define MT_MAC_APC_BSSID_BASE 0x1090 3076c92544dSBjoern A. Zeeb #define MT_MAC_APC_BSSID_L(_n) (MT_MAC_APC_BSSID_BASE + ((_n) * 8)) 3086c92544dSBjoern A. Zeeb #define MT_MAC_APC_BSSID_H(_n) (MT_MAC_APC_BSSID_BASE + ((_n) * 8 + 4)) 3096c92544dSBjoern A. Zeeb #define MT_MAC_APC_BSSID_H_ADDR GENMASK(15, 0) 3106c92544dSBjoern A. Zeeb #define MT_MAC_APC_BSSID0_H_EN BIT(16) 3116c92544dSBjoern A. Zeeb 3126c92544dSBjoern A. Zeeb #define MT_XIFS_TIME_CFG 0x1100 3136c92544dSBjoern A. Zeeb #define MT_XIFS_TIME_CFG_CCK_SIFS GENMASK(7, 0) 3146c92544dSBjoern A. Zeeb #define MT_XIFS_TIME_CFG_OFDM_SIFS GENMASK(15, 8) 3156c92544dSBjoern A. Zeeb #define MT_XIFS_TIME_CFG_OFDM_XIFS GENMASK(19, 16) 3166c92544dSBjoern A. Zeeb #define MT_XIFS_TIME_CFG_EIFS GENMASK(28, 20) 3176c92544dSBjoern A. Zeeb #define MT_XIFS_TIME_CFG_BB_RXEND_EN BIT(29) 3186c92544dSBjoern A. Zeeb 3196c92544dSBjoern A. Zeeb #define MT_BKOFF_SLOT_CFG 0x1104 3206c92544dSBjoern A. Zeeb #define MT_BKOFF_SLOT_CFG_SLOTTIME GENMASK(7, 0) 3216c92544dSBjoern A. Zeeb #define MT_BKOFF_SLOT_CFG_CC_DELAY GENMASK(11, 8) 3226c92544dSBjoern A. Zeeb 3236c92544dSBjoern A. Zeeb #define MT_CH_TIME_CFG 0x110c 3246c92544dSBjoern A. Zeeb #define MT_CH_TIME_CFG_TIMER_EN BIT(0) 3256c92544dSBjoern A. Zeeb #define MT_CH_TIME_CFG_TX_AS_BUSY BIT(1) 3266c92544dSBjoern A. Zeeb #define MT_CH_TIME_CFG_RX_AS_BUSY BIT(2) 3276c92544dSBjoern A. Zeeb #define MT_CH_TIME_CFG_NAV_AS_BUSY BIT(3) 3286c92544dSBjoern A. Zeeb #define MT_CH_TIME_CFG_EIFS_AS_BUSY BIT(4) 3296c92544dSBjoern A. Zeeb #define MT_CH_TIME_CFG_MDRDY_CNT_EN BIT(5) 3306c92544dSBjoern A. Zeeb #define MT_CH_CCA_RC_EN BIT(6) 3316c92544dSBjoern A. Zeeb #define MT_CH_TIME_CFG_CH_TIMER_CLR GENMASK(9, 8) 3326c92544dSBjoern A. Zeeb #define MT_CH_TIME_CFG_MDRDY_CLR GENMASK(11, 10) 3336c92544dSBjoern A. Zeeb 3346c92544dSBjoern A. Zeeb #define MT_PBF_LIFE_TIMER 0x1110 3356c92544dSBjoern A. Zeeb 3366c92544dSBjoern A. Zeeb #define MT_BEACON_TIME_CFG 0x1114 3376c92544dSBjoern A. Zeeb #define MT_BEACON_TIME_CFG_INTVAL GENMASK(15, 0) 3386c92544dSBjoern A. Zeeb #define MT_BEACON_TIME_CFG_TIMER_EN BIT(16) 3396c92544dSBjoern A. Zeeb #define MT_BEACON_TIME_CFG_SYNC_MODE GENMASK(18, 17) 3406c92544dSBjoern A. Zeeb #define MT_BEACON_TIME_CFG_TBTT_EN BIT(19) 3416c92544dSBjoern A. Zeeb #define MT_BEACON_TIME_CFG_BEACON_TX BIT(20) 3426c92544dSBjoern A. Zeeb #define MT_BEACON_TIME_CFG_TSF_COMP GENMASK(31, 24) 3436c92544dSBjoern A. Zeeb 3446c92544dSBjoern A. Zeeb #define MT_TBTT_SYNC_CFG 0x1118 3456c92544dSBjoern A. Zeeb #define MT_TSF_TIMER_DW0 0x111c 3466c92544dSBjoern A. Zeeb #define MT_TSF_TIMER_DW1 0x1120 3476c92544dSBjoern A. Zeeb #define MT_TBTT_TIMER 0x1124 3486c92544dSBjoern A. Zeeb #define MT_TBTT_TIMER_VAL GENMASK(16, 0) 3496c92544dSBjoern A. Zeeb 3506c92544dSBjoern A. Zeeb #define MT_INT_TIMER_CFG 0x1128 3516c92544dSBjoern A. Zeeb #define MT_INT_TIMER_CFG_PRE_TBTT GENMASK(15, 0) 3526c92544dSBjoern A. Zeeb #define MT_INT_TIMER_CFG_GP_TIMER GENMASK(31, 16) 3536c92544dSBjoern A. Zeeb 3546c92544dSBjoern A. Zeeb #define MT_INT_TIMER_EN 0x112c 3556c92544dSBjoern A. Zeeb #define MT_INT_TIMER_EN_PRE_TBTT_EN BIT(0) 3566c92544dSBjoern A. Zeeb #define MT_INT_TIMER_EN_GP_TIMER_EN BIT(1) 3576c92544dSBjoern A. Zeeb 3586c92544dSBjoern A. Zeeb #define MT_CH_IDLE 0x1130 3596c92544dSBjoern A. Zeeb #define MT_CH_BUSY 0x1134 3606c92544dSBjoern A. Zeeb #define MT_EXT_CH_BUSY 0x1138 3616c92544dSBjoern A. Zeeb #define MT_ED_CCA_TIMER 0x1140 3626c92544dSBjoern A. Zeeb 3636c92544dSBjoern A. Zeeb #define MT_MAC_STATUS 0x1200 3646c92544dSBjoern A. Zeeb #define MT_MAC_STATUS_TX BIT(0) 3656c92544dSBjoern A. Zeeb #define MT_MAC_STATUS_RX BIT(1) 3666c92544dSBjoern A. Zeeb 3676c92544dSBjoern A. Zeeb #define MT_PWR_PIN_CFG 0x1204 3686c92544dSBjoern A. Zeeb #define MT_AUX_CLK_CFG 0x120c 3696c92544dSBjoern A. Zeeb 3706c92544dSBjoern A. Zeeb #define MT_BB_PA_MODE_CFG0 0x1214 3716c92544dSBjoern A. Zeeb #define MT_BB_PA_MODE_CFG1 0x1218 3726c92544dSBjoern A. Zeeb #define MT_RF_PA_MODE_CFG0 0x121c 3736c92544dSBjoern A. Zeeb #define MT_RF_PA_MODE_CFG1 0x1220 3746c92544dSBjoern A. Zeeb 3756c92544dSBjoern A. Zeeb #define MT_RF_PA_MODE_ADJ0 0x1228 3766c92544dSBjoern A. Zeeb #define MT_RF_PA_MODE_ADJ1 0x122c 3776c92544dSBjoern A. Zeeb 3786c92544dSBjoern A. Zeeb #define MT_DACCLK_EN_DLY_CFG 0x1264 3796c92544dSBjoern A. Zeeb 3806c92544dSBjoern A. Zeeb #define MT_EDCA_CFG_BASE 0x1300 3816c92544dSBjoern A. Zeeb #define MT_EDCA_CFG_AC(_n) (MT_EDCA_CFG_BASE + ((_n) << 2)) 3826c92544dSBjoern A. Zeeb #define MT_EDCA_CFG_TXOP GENMASK(7, 0) 3836c92544dSBjoern A. Zeeb #define MT_EDCA_CFG_AIFSN GENMASK(11, 8) 3846c92544dSBjoern A. Zeeb #define MT_EDCA_CFG_CWMIN GENMASK(15, 12) 3856c92544dSBjoern A. Zeeb #define MT_EDCA_CFG_CWMAX GENMASK(19, 16) 3866c92544dSBjoern A. Zeeb 3876c92544dSBjoern A. Zeeb #define MT_TX_PWR_CFG_0 0x1314 3886c92544dSBjoern A. Zeeb #define MT_TX_PWR_CFG_1 0x1318 3896c92544dSBjoern A. Zeeb #define MT_TX_PWR_CFG_2 0x131c 3906c92544dSBjoern A. Zeeb #define MT_TX_PWR_CFG_3 0x1320 3916c92544dSBjoern A. Zeeb #define MT_TX_PWR_CFG_4 0x1324 3926c92544dSBjoern A. Zeeb #define MT_TX_PIN_CFG 0x1328 3936c92544dSBjoern A. Zeeb #define MT_TX_PIN_CFG_TXANT GENMASK(3, 0) 3946c92544dSBjoern A. Zeeb #define MT_TX_PIN_CFG_RXANT GENMASK(11, 8) 3956c92544dSBjoern A. Zeeb #define MT_TX_PIN_RFTR_EN BIT(16) 3966c92544dSBjoern A. Zeeb #define MT_TX_PIN_TRSW_EN BIT(18) 3976c92544dSBjoern A. Zeeb 3986c92544dSBjoern A. Zeeb #define MT_TX_BAND_CFG 0x132c 3996c92544dSBjoern A. Zeeb #define MT_TX_BAND_CFG_UPPER_40M BIT(0) 4006c92544dSBjoern A. Zeeb #define MT_TX_BAND_CFG_5G BIT(1) 4016c92544dSBjoern A. Zeeb #define MT_TX_BAND_CFG_2G BIT(2) 4026c92544dSBjoern A. Zeeb 4036c92544dSBjoern A. Zeeb #define MT_HT_FBK_TO_LEGACY 0x1384 4046c92544dSBjoern A. Zeeb #define MT_TX_MPDU_ADJ_INT 0x1388 4056c92544dSBjoern A. Zeeb 4066c92544dSBjoern A. Zeeb #define MT_TX_PWR_CFG_7 0x13d4 4076c92544dSBjoern A. Zeeb #define MT_TX_PWR_CFG_8 0x13d8 4086c92544dSBjoern A. Zeeb #define MT_TX_PWR_CFG_9 0x13dc 4096c92544dSBjoern A. Zeeb 4106c92544dSBjoern A. Zeeb #define MT_TX_SW_CFG0 0x1330 4116c92544dSBjoern A. Zeeb #define MT_TX_SW_CFG1 0x1334 4126c92544dSBjoern A. Zeeb #define MT_TX_SW_CFG2 0x1338 4136c92544dSBjoern A. Zeeb 4146c92544dSBjoern A. Zeeb #define MT_TXOP_CTRL_CFG 0x1340 4156c92544dSBjoern A. Zeeb #define MT_TXOP_TRUN_EN GENMASK(5, 0) 4166c92544dSBjoern A. Zeeb #define MT_TXOP_EXT_CCA_DLY GENMASK(15, 8) 4176c92544dSBjoern A. Zeeb #define MT_TXOP_ED_CCA_EN BIT(20) 4186c92544dSBjoern A. Zeeb 4196c92544dSBjoern A. Zeeb #define MT_TX_RTS_CFG 0x1344 4206c92544dSBjoern A. Zeeb #define MT_TX_RTS_CFG_RETRY_LIMIT GENMASK(7, 0) 4216c92544dSBjoern A. Zeeb #define MT_TX_RTS_CFG_THRESH GENMASK(23, 8) 4226c92544dSBjoern A. Zeeb #define MT_TX_RTS_FALLBACK BIT(24) 4236c92544dSBjoern A. Zeeb 4246c92544dSBjoern A. Zeeb #define MT_TX_TIMEOUT_CFG 0x1348 4256c92544dSBjoern A. Zeeb #define MT_TX_TIMEOUT_CFG_ACKTO GENMASK(15, 8) 4266c92544dSBjoern A. Zeeb 4276c92544dSBjoern A. Zeeb #define MT_TX_RETRY_CFG 0x134c 4286c92544dSBjoern A. Zeeb #define MT_TX_LINK_CFG 0x1350 4296c92544dSBjoern A. Zeeb #define MT_TX_CFACK_EN BIT(12) 4306c92544dSBjoern A. Zeeb #define MT_VHT_HT_FBK_CFG0 0x1354 4316c92544dSBjoern A. Zeeb #define MT_VHT_HT_FBK_CFG1 0x1358 4326c92544dSBjoern A. Zeeb #define MT_LG_FBK_CFG0 0x135c 4336c92544dSBjoern A. Zeeb #define MT_LG_FBK_CFG1 0x1360 4346c92544dSBjoern A. Zeeb 4356c92544dSBjoern A. Zeeb #define MT_PROT_CFG_RATE GENMASK(15, 0) 4366c92544dSBjoern A. Zeeb #define MT_PROT_CFG_CTRL GENMASK(17, 16) 4376c92544dSBjoern A. Zeeb #define MT_PROT_CFG_NAV GENMASK(19, 18) 4386c92544dSBjoern A. Zeeb #define MT_PROT_CFG_TXOP_ALLOW GENMASK(25, 20) 4396c92544dSBjoern A. Zeeb #define MT_PROT_CFG_RTS_THRESH BIT(26) 4406c92544dSBjoern A. Zeeb 4416c92544dSBjoern A. Zeeb #define MT_CCK_PROT_CFG 0x1364 4426c92544dSBjoern A. Zeeb #define MT_OFDM_PROT_CFG 0x1368 4436c92544dSBjoern A. Zeeb #define MT_MM20_PROT_CFG 0x136c 4446c92544dSBjoern A. Zeeb #define MT_MM40_PROT_CFG 0x1370 4456c92544dSBjoern A. Zeeb #define MT_GF20_PROT_CFG 0x1374 4466c92544dSBjoern A. Zeeb #define MT_GF40_PROT_CFG 0x1378 4476c92544dSBjoern A. Zeeb 4486c92544dSBjoern A. Zeeb #define MT_PROT_RATE GENMASK(15, 0) 4496c92544dSBjoern A. Zeeb #define MT_PROT_CTRL_RTS_CTS BIT(16) 4506c92544dSBjoern A. Zeeb #define MT_PROT_CTRL_CTS2SELF BIT(17) 4516c92544dSBjoern A. Zeeb #define MT_PROT_NAV_SHORT BIT(18) 4526c92544dSBjoern A. Zeeb #define MT_PROT_NAV_LONG BIT(19) 4536c92544dSBjoern A. Zeeb #define MT_PROT_TXOP_ALLOW_CCK BIT(20) 4546c92544dSBjoern A. Zeeb #define MT_PROT_TXOP_ALLOW_OFDM BIT(21) 4556c92544dSBjoern A. Zeeb #define MT_PROT_TXOP_ALLOW_MM20 BIT(22) 4566c92544dSBjoern A. Zeeb #define MT_PROT_TXOP_ALLOW_MM40 BIT(23) 4576c92544dSBjoern A. Zeeb #define MT_PROT_TXOP_ALLOW_GF20 BIT(24) 4586c92544dSBjoern A. Zeeb #define MT_PROT_TXOP_ALLOW_GF40 BIT(25) 4596c92544dSBjoern A. Zeeb #define MT_PROT_RTS_THR_EN BIT(26) 4606c92544dSBjoern A. Zeeb #define MT_PROT_RATE_CCK_11 0x0003 4616c92544dSBjoern A. Zeeb #define MT_PROT_RATE_OFDM_6 0x2000 4626c92544dSBjoern A. Zeeb #define MT_PROT_RATE_OFDM_24 0x2004 4636c92544dSBjoern A. Zeeb #define MT_PROT_RATE_DUP_OFDM_24 0x2084 4646c92544dSBjoern A. Zeeb #define MT_PROT_RATE_SGI_OFDM_24 0x2104 4656c92544dSBjoern A. Zeeb #define MT_PROT_TXOP_ALLOW_ALL GENMASK(25, 20) 4666c92544dSBjoern A. Zeeb #define MT_PROT_TXOP_ALLOW_BW20 (MT_PROT_TXOP_ALLOW_ALL & \ 4676c92544dSBjoern A. Zeeb ~MT_PROT_TXOP_ALLOW_MM40 & \ 4686c92544dSBjoern A. Zeeb ~MT_PROT_TXOP_ALLOW_GF40) 4696c92544dSBjoern A. Zeeb 4706c92544dSBjoern A. Zeeb #define MT_EXP_ACK_TIME 0x1380 4716c92544dSBjoern A. Zeeb 4726c92544dSBjoern A. Zeeb #define MT_TX_PWR_CFG_0_EXT 0x1390 4736c92544dSBjoern A. Zeeb #define MT_TX_PWR_CFG_1_EXT 0x1394 4746c92544dSBjoern A. Zeeb 4756c92544dSBjoern A. Zeeb #define MT_TX_FBK_LIMIT 0x1398 4766c92544dSBjoern A. Zeeb #define MT_TX_FBK_LIMIT_MPDU_FBK GENMASK(7, 0) 4776c92544dSBjoern A. Zeeb #define MT_TX_FBK_LIMIT_AMPDU_FBK GENMASK(15, 8) 4786c92544dSBjoern A. Zeeb #define MT_TX_FBK_LIMIT_MPDU_UP_CLEAR BIT(16) 4796c92544dSBjoern A. Zeeb #define MT_TX_FBK_LIMIT_AMPDU_UP_CLEAR BIT(17) 4806c92544dSBjoern A. Zeeb #define MT_TX_FBK_LIMIT_RATE_LUT BIT(18) 4816c92544dSBjoern A. Zeeb 4826c92544dSBjoern A. Zeeb #define MT_TX0_RF_GAIN_CORR 0x13a0 4836c92544dSBjoern A. Zeeb #define MT_TX1_RF_GAIN_CORR 0x13a4 4846c92544dSBjoern A. Zeeb #define MT_TX0_RF_GAIN_ATTEN 0x13a8 4856c92544dSBjoern A. Zeeb #define MT_TX0_RF_GAIN_ATTEN 0x13a8 /* MT76x0 */ 4866c92544dSBjoern A. Zeeb 4876c92544dSBjoern A. Zeeb #define MT_TX_ALC_CFG_0 0x13b0 4886c92544dSBjoern A. Zeeb #define MT_TX_ALC_CFG_0_CH_INIT_0 GENMASK(5, 0) 4896c92544dSBjoern A. Zeeb #define MT_TX_ALC_CFG_0_CH_INIT_1 GENMASK(13, 8) 4906c92544dSBjoern A. Zeeb #define MT_TX_ALC_CFG_0_LIMIT_0 GENMASK(21, 16) 4916c92544dSBjoern A. Zeeb #define MT_TX_ALC_CFG_0_LIMIT_1 GENMASK(29, 24) 4926c92544dSBjoern A. Zeeb 4936c92544dSBjoern A. Zeeb #define MT_TX_ALC_CFG_1 0x13b4 4946c92544dSBjoern A. Zeeb #define MT_TX_ALC_CFG_1_TEMP_COMP GENMASK(5, 0) 4956c92544dSBjoern A. Zeeb 4966c92544dSBjoern A. Zeeb #define MT_TX_ALC_CFG_2 0x13a8 4976c92544dSBjoern A. Zeeb #define MT_TX_ALC_CFG_2_TEMP_COMP GENMASK(5, 0) 4986c92544dSBjoern A. Zeeb 4996c92544dSBjoern A. Zeeb #define MT_TX_ALC_CFG_3 0x13ac 5006c92544dSBjoern A. Zeeb #define MT_TX_ALC_CFG_4 0x13c0 5016c92544dSBjoern A. Zeeb #define MT_TX_ALC_CFG_4_LOWGAIN_CH_EN BIT(31) 5026c92544dSBjoern A. Zeeb #define MT_TX0_BB_GAIN_ATTEN 0x13c0 /* MT76x0 */ 5036c92544dSBjoern A. Zeeb 5046c92544dSBjoern A. Zeeb #define MT_TX_ALC_VGA3 0x13c8 5056c92544dSBjoern A. Zeeb 5066c92544dSBjoern A. Zeeb #define MT_TX_PROT_CFG6 0x13e0 5076c92544dSBjoern A. Zeeb #define MT_TX_PROT_CFG7 0x13e4 5086c92544dSBjoern A. Zeeb #define MT_TX_PROT_CFG8 0x13e8 5096c92544dSBjoern A. Zeeb 5106c92544dSBjoern A. Zeeb #define MT_PIFS_TX_CFG 0x13ec 5116c92544dSBjoern A. Zeeb 5126c92544dSBjoern A. Zeeb #define MT_RX_FILTR_CFG 0x1400 5136c92544dSBjoern A. Zeeb 5146c92544dSBjoern A. Zeeb #define MT_RX_FILTR_CFG_CRC_ERR BIT(0) 5156c92544dSBjoern A. Zeeb #define MT_RX_FILTR_CFG_PHY_ERR BIT(1) 5166c92544dSBjoern A. Zeeb #define MT_RX_FILTR_CFG_PROMISC BIT(2) 5176c92544dSBjoern A. Zeeb #define MT_RX_FILTR_CFG_OTHER_BSS BIT(3) 5186c92544dSBjoern A. Zeeb #define MT_RX_FILTR_CFG_VER_ERR BIT(4) 5196c92544dSBjoern A. Zeeb #define MT_RX_FILTR_CFG_MCAST BIT(5) 5206c92544dSBjoern A. Zeeb #define MT_RX_FILTR_CFG_BCAST BIT(6) 5216c92544dSBjoern A. Zeeb #define MT_RX_FILTR_CFG_DUP BIT(7) 5226c92544dSBjoern A. Zeeb #define MT_RX_FILTR_CFG_CFACK BIT(8) 5236c92544dSBjoern A. Zeeb #define MT_RX_FILTR_CFG_CFEND BIT(9) 5246c92544dSBjoern A. Zeeb #define MT_RX_FILTR_CFG_ACK BIT(10) 5256c92544dSBjoern A. Zeeb #define MT_RX_FILTR_CFG_CTS BIT(11) 5266c92544dSBjoern A. Zeeb #define MT_RX_FILTR_CFG_RTS BIT(12) 5276c92544dSBjoern A. Zeeb #define MT_RX_FILTR_CFG_PSPOLL BIT(13) 5286c92544dSBjoern A. Zeeb #define MT_RX_FILTR_CFG_BA BIT(14) 5296c92544dSBjoern A. Zeeb #define MT_RX_FILTR_CFG_BAR BIT(15) 5306c92544dSBjoern A. Zeeb #define MT_RX_FILTR_CFG_CTRL_RSV BIT(16) 5316c92544dSBjoern A. Zeeb 5326c92544dSBjoern A. Zeeb #define MT_AUTO_RSP_CFG 0x1404 5336c92544dSBjoern A. Zeeb #define MT_AUTO_RSP_EN BIT(0) 5346c92544dSBjoern A. Zeeb #define MT_AUTO_RSP_PREAMB_SHORT BIT(4) 5356c92544dSBjoern A. Zeeb #define MT_LEGACY_BASIC_RATE 0x1408 5366c92544dSBjoern A. Zeeb #define MT_HT_BASIC_RATE 0x140c 5376c92544dSBjoern A. Zeeb 5386c92544dSBjoern A. Zeeb #define MT_HT_CTRL_CFG 0x1410 5396c92544dSBjoern A. Zeeb #define MT_RX_PARSER_CFG 0x1418 5406c92544dSBjoern A. Zeeb #define MT_RX_PARSER_RX_SET_NAV_ALL BIT(0) 5416c92544dSBjoern A. Zeeb 5426c92544dSBjoern A. Zeeb #define MT_EXT_CCA_CFG 0x141c 5436c92544dSBjoern A. Zeeb #define MT_EXT_CCA_CFG_CCA0 GENMASK(1, 0) 5446c92544dSBjoern A. Zeeb #define MT_EXT_CCA_CFG_CCA1 GENMASK(3, 2) 5456c92544dSBjoern A. Zeeb #define MT_EXT_CCA_CFG_CCA2 GENMASK(5, 4) 5466c92544dSBjoern A. Zeeb #define MT_EXT_CCA_CFG_CCA3 GENMASK(7, 6) 5476c92544dSBjoern A. Zeeb #define MT_EXT_CCA_CFG_CCA_MASK GENMASK(11, 8) 5486c92544dSBjoern A. Zeeb #define MT_EXT_CCA_CFG_ED_CCA_MASK GENMASK(15, 12) 5496c92544dSBjoern A. Zeeb 5506c92544dSBjoern A. Zeeb #define MT_TX_SW_CFG3 0x1478 5516c92544dSBjoern A. Zeeb 5526c92544dSBjoern A. Zeeb #define MT_PN_PAD_MODE 0x150c 5536c92544dSBjoern A. Zeeb 5546c92544dSBjoern A. Zeeb #define MT_TXOP_HLDR_ET 0x1608 5556c92544dSBjoern A. Zeeb #define MT_TXOP_HLDR_TX40M_BLK_EN BIT(1) 5566c92544dSBjoern A. Zeeb 5576c92544dSBjoern A. Zeeb #define MT_PROT_AUTO_TX_CFG 0x1648 5586c92544dSBjoern A. Zeeb #define MT_PROT_AUTO_TX_CFG_PROT_PADJ GENMASK(11, 8) 5596c92544dSBjoern A. Zeeb #define MT_PROT_AUTO_TX_CFG_AUTO_PADJ GENMASK(27, 24) 5606c92544dSBjoern A. Zeeb 5616c92544dSBjoern A. Zeeb #define MT_RX_STAT_0 0x1700 5626c92544dSBjoern A. Zeeb #define MT_RX_STAT_0_CRC_ERRORS GENMASK(15, 0) 5636c92544dSBjoern A. Zeeb #define MT_RX_STAT_0_PHY_ERRORS GENMASK(31, 16) 5646c92544dSBjoern A. Zeeb 5656c92544dSBjoern A. Zeeb #define MT_RX_STAT_1 0x1704 5666c92544dSBjoern A. Zeeb #define MT_RX_STAT_1_CCA_ERRORS GENMASK(15, 0) 5676c92544dSBjoern A. Zeeb #define MT_RX_STAT_1_PLCP_ERRORS GENMASK(31, 16) 5686c92544dSBjoern A. Zeeb 5696c92544dSBjoern A. Zeeb #define MT_RX_STAT_2 0x1708 5706c92544dSBjoern A. Zeeb #define MT_RX_STAT_2_DUP_ERRORS GENMASK(15, 0) 5716c92544dSBjoern A. Zeeb #define MT_RX_STAT_2_OVERFLOW_ERRORS GENMASK(31, 16) 5726c92544dSBjoern A. Zeeb 5736c92544dSBjoern A. Zeeb #define MT_TX_STA_0 0x170c 5746c92544dSBjoern A. Zeeb #define MT_TX_STA_0_BEACONS GENMASK(31, 16) 5756c92544dSBjoern A. Zeeb 5766c92544dSBjoern A. Zeeb #define MT_TX_STA_1 0x1710 5776c92544dSBjoern A. Zeeb #define MT_TX_STA_2 0x1714 5786c92544dSBjoern A. Zeeb 5796c92544dSBjoern A. Zeeb #define MT_TX_STAT_FIFO 0x1718 5806c92544dSBjoern A. Zeeb #define MT_TX_STAT_FIFO_VALID BIT(0) 5816c92544dSBjoern A. Zeeb #define MT_TX_STAT_FIFO_SUCCESS BIT(5) 5826c92544dSBjoern A. Zeeb #define MT_TX_STAT_FIFO_AGGR BIT(6) 5836c92544dSBjoern A. Zeeb #define MT_TX_STAT_FIFO_ACKREQ BIT(7) 5846c92544dSBjoern A. Zeeb #define MT_TX_STAT_FIFO_WCID GENMASK(15, 8) 5856c92544dSBjoern A. Zeeb #define MT_TX_STAT_FIFO_RATE GENMASK(31, 16) 5866c92544dSBjoern A. Zeeb 5876c92544dSBjoern A. Zeeb #define MT_TX_AGG_STAT 0x171c 5886c92544dSBjoern A. Zeeb 5896c92544dSBjoern A. Zeeb #define MT_TX_AGG_CNT_BASE0 0x1720 5906c92544dSBjoern A. Zeeb #define MT_MPDU_DENSITY_CNT 0x1740 5916c92544dSBjoern A. Zeeb #define MT_TX_AGG_CNT_BASE1 0x174c 5926c92544dSBjoern A. Zeeb 5936c92544dSBjoern A. Zeeb #define MT_TX_AGG_CNT(_id) ((_id) < 8 ? \ 5946c92544dSBjoern A. Zeeb MT_TX_AGG_CNT_BASE0 + ((_id) << 2) : \ 5956c92544dSBjoern A. Zeeb MT_TX_AGG_CNT_BASE1 + (((_id) - 8) << 2)) 5966c92544dSBjoern A. Zeeb 5976c92544dSBjoern A. Zeeb #define MT_TX_STAT_FIFO_EXT 0x1798 5986c92544dSBjoern A. Zeeb #define MT_TX_STAT_FIFO_EXT_RETRY GENMASK(7, 0) 5996c92544dSBjoern A. Zeeb #define MT_TX_STAT_FIFO_EXT_PKTID GENMASK(15, 8) 6006c92544dSBjoern A. Zeeb 6016c92544dSBjoern A. Zeeb #define MT_WCID_TX_RATE_BASE 0x1c00 6026c92544dSBjoern A. Zeeb #define MT_WCID_TX_RATE(_i) (MT_WCID_TX_RATE_BASE + ((_i) << 3)) 6036c92544dSBjoern A. Zeeb 6046c92544dSBjoern A. Zeeb #define MT_BBP_CORE_BASE 0x2000 6056c92544dSBjoern A. Zeeb #define MT_BBP_IBI_BASE 0x2100 6066c92544dSBjoern A. Zeeb #define MT_BBP_AGC_BASE 0x2300 6076c92544dSBjoern A. Zeeb #define MT_BBP_TXC_BASE 0x2400 6086c92544dSBjoern A. Zeeb #define MT_BBP_RXC_BASE 0x2500 6096c92544dSBjoern A. Zeeb #define MT_BBP_TXO_BASE 0x2600 6106c92544dSBjoern A. Zeeb #define MT_BBP_TXBE_BASE 0x2700 6116c92544dSBjoern A. Zeeb #define MT_BBP_RXFE_BASE 0x2800 6126c92544dSBjoern A. Zeeb #define MT_BBP_RXO_BASE 0x2900 6136c92544dSBjoern A. Zeeb #define MT_BBP_DFS_BASE 0x2a00 6146c92544dSBjoern A. Zeeb #define MT_BBP_TR_BASE 0x2b00 6156c92544dSBjoern A. Zeeb #define MT_BBP_CAL_BASE 0x2c00 6166c92544dSBjoern A. Zeeb #define MT_BBP_DSC_BASE 0x2e00 6176c92544dSBjoern A. Zeeb #define MT_BBP_PFMU_BASE 0x2f00 6186c92544dSBjoern A. Zeeb 6196c92544dSBjoern A. Zeeb #define MT_BBP(_type, _n) (MT_BBP_##_type##_BASE + ((_n) << 2)) 6206c92544dSBjoern A. Zeeb 6216c92544dSBjoern A. Zeeb #define MT_BBP_CORE_R1_BW GENMASK(4, 3) 6226c92544dSBjoern A. Zeeb 6236c92544dSBjoern A. Zeeb #define MT_BBP_AGC_R0_CTRL_CHAN GENMASK(9, 8) 6246c92544dSBjoern A. Zeeb #define MT_BBP_AGC_R0_BW GENMASK(14, 12) 6256c92544dSBjoern A. Zeeb 6266c92544dSBjoern A. Zeeb /* AGC, R4/R5 */ 6276c92544dSBjoern A. Zeeb #define MT_BBP_AGC_LNA_HIGH_GAIN GENMASK(21, 16) 6286c92544dSBjoern A. Zeeb #define MT_BBP_AGC_LNA_MID_GAIN GENMASK(13, 8) 6296c92544dSBjoern A. Zeeb #define MT_BBP_AGC_LNA_LOW_GAIN GENMASK(5, 0) 6306c92544dSBjoern A. Zeeb 6316c92544dSBjoern A. Zeeb /* AGC, R6/R7 */ 6326c92544dSBjoern A. Zeeb #define MT_BBP_AGC_LNA_ULOW_GAIN GENMASK(5, 0) 6336c92544dSBjoern A. Zeeb 6346c92544dSBjoern A. Zeeb /* AGC, R8/R9 */ 6356c92544dSBjoern A. Zeeb #define MT_BBP_AGC_LNA_GAIN_MODE GENMASK(7, 6) 6366c92544dSBjoern A. Zeeb #define MT_BBP_AGC_GAIN GENMASK(14, 8) 6376c92544dSBjoern A. Zeeb 6386c92544dSBjoern A. Zeeb #define MT_BBP_AGC20_RSSI0 GENMASK(7, 0) 6396c92544dSBjoern A. Zeeb #define MT_BBP_AGC20_RSSI1 GENMASK(15, 8) 6406c92544dSBjoern A. Zeeb 6416c92544dSBjoern A. Zeeb #define MT_BBP_TXBE_R0_CTRL_CHAN GENMASK(1, 0) 6426c92544dSBjoern A. Zeeb 6436c92544dSBjoern A. Zeeb #define MT_WCID_ADDR_BASE 0x1800 6446c92544dSBjoern A. Zeeb #define MT_WCID_ADDR(_n) (MT_WCID_ADDR_BASE + (_n) * 8) 6456c92544dSBjoern A. Zeeb 6466c92544dSBjoern A. Zeeb #define MT_SRAM_BASE 0x4000 6476c92544dSBjoern A. Zeeb 6486c92544dSBjoern A. Zeeb #define MT_WCID_KEY_BASE 0x8000 6496c92544dSBjoern A. Zeeb #define MT_WCID_KEY(_n) (MT_WCID_KEY_BASE + (_n) * 32) 6506c92544dSBjoern A. Zeeb 6516c92544dSBjoern A. Zeeb #define MT_WCID_IV_BASE 0xa000 6526c92544dSBjoern A. Zeeb #define MT_WCID_IV(_n) (MT_WCID_IV_BASE + (_n) * 8) 6536c92544dSBjoern A. Zeeb 6546c92544dSBjoern A. Zeeb #define MT_WCID_ATTR_BASE 0xa800 6556c92544dSBjoern A. Zeeb #define MT_WCID_ATTR(_n) (MT_WCID_ATTR_BASE + (_n) * 4) 6566c92544dSBjoern A. Zeeb 6576c92544dSBjoern A. Zeeb #define MT_WCID_ATTR_PAIRWISE BIT(0) 6586c92544dSBjoern A. Zeeb #define MT_WCID_ATTR_PKEY_MODE GENMASK(3, 1) 6596c92544dSBjoern A. Zeeb #define MT_WCID_ATTR_BSS_IDX GENMASK(6, 4) 6606c92544dSBjoern A. Zeeb #define MT_WCID_ATTR_RXWI_UDF GENMASK(9, 7) 6616c92544dSBjoern A. Zeeb #define MT_WCID_ATTR_PKEY_MODE_EXT BIT(10) 6626c92544dSBjoern A. Zeeb #define MT_WCID_ATTR_BSS_IDX_EXT BIT(11) 6636c92544dSBjoern A. Zeeb #define MT_WCID_ATTR_WAPI_MCBC BIT(15) 6646c92544dSBjoern A. Zeeb #define MT_WCID_ATTR_WAPI_KEYID GENMASK(31, 24) 6656c92544dSBjoern A. Zeeb 6666c92544dSBjoern A. Zeeb #define MT_SKEY_BASE_0 0xac00 6676c92544dSBjoern A. Zeeb #define MT_SKEY_BASE_1 0xb400 6686c92544dSBjoern A. Zeeb #define MT_SKEY_0(_bss, _idx) (MT_SKEY_BASE_0 + (4 * (_bss) + (_idx)) * 32) 6696c92544dSBjoern A. Zeeb #define MT_SKEY_1(_bss, _idx) (MT_SKEY_BASE_1 + (4 * ((_bss) & 7) + (_idx)) * 32) 6706c92544dSBjoern A. Zeeb #define MT_SKEY(_bss, _idx) (((_bss) & 8) ? MT_SKEY_1(_bss, _idx) : MT_SKEY_0(_bss, _idx)) 6716c92544dSBjoern A. Zeeb 6726c92544dSBjoern A. Zeeb #define MT_SKEY_MODE_BASE_0 0xb000 6736c92544dSBjoern A. Zeeb #define MT_SKEY_MODE_BASE_1 0xb3f0 6746c92544dSBjoern A. Zeeb #define MT_SKEY_MODE_0(_bss) (MT_SKEY_MODE_BASE_0 + (((_bss) / 2) << 2)) 6756c92544dSBjoern A. Zeeb #define MT_SKEY_MODE_1(_bss) (MT_SKEY_MODE_BASE_1 + ((((_bss) & 7) / 2) << 2)) 6766c92544dSBjoern A. Zeeb #define MT_SKEY_MODE(_bss) (((_bss) & 8) ? MT_SKEY_MODE_1(_bss) : MT_SKEY_MODE_0(_bss)) 6776c92544dSBjoern A. Zeeb #define MT_SKEY_MODE_MASK GENMASK(3, 0) 6786c92544dSBjoern A. Zeeb #define MT_SKEY_MODE_SHIFT(_bss, _idx) (4 * ((_idx) + 4 * ((_bss) & 1))) 6796c92544dSBjoern A. Zeeb 6806c92544dSBjoern A. Zeeb #define MT_BEACON_BASE 0xc000 6816c92544dSBjoern A. Zeeb 6826c92544dSBjoern A. Zeeb #define MT_TEMP_SENSOR 0x1d000 6836c92544dSBjoern A. Zeeb #define MT_TEMP_SENSOR_VAL GENMASK(6, 0) 6846c92544dSBjoern A. Zeeb 6856c92544dSBjoern A. Zeeb struct mt76_wcid_addr { 6866c92544dSBjoern A. Zeeb u8 macaddr[6]; 6876c92544dSBjoern A. Zeeb __le16 ba_mask; 6886c92544dSBjoern A. Zeeb } __packed __aligned(4); 6896c92544dSBjoern A. Zeeb 6906c92544dSBjoern A. Zeeb struct mt76_wcid_key { 6916c92544dSBjoern A. Zeeb u8 key[16]; 6926c92544dSBjoern A. Zeeb u8 tx_mic[8]; 6936c92544dSBjoern A. Zeeb u8 rx_mic[8]; 6946c92544dSBjoern A. Zeeb } __packed __aligned(4); 6956c92544dSBjoern A. Zeeb 6966c92544dSBjoern A. Zeeb enum mt76x02_cipher_type { 6976c92544dSBjoern A. Zeeb MT76X02_CIPHER_NONE, 6986c92544dSBjoern A. Zeeb MT76X02_CIPHER_WEP40, 6996c92544dSBjoern A. Zeeb MT76X02_CIPHER_WEP104, 7006c92544dSBjoern A. Zeeb MT76X02_CIPHER_TKIP, 7016c92544dSBjoern A. Zeeb MT76X02_CIPHER_AES_CCMP, 7026c92544dSBjoern A. Zeeb MT76X02_CIPHER_CKIP40, 7036c92544dSBjoern A. Zeeb MT76X02_CIPHER_CKIP104, 7046c92544dSBjoern A. Zeeb MT76X02_CIPHER_CKIP128, 7056c92544dSBjoern A. Zeeb MT76X02_CIPHER_WAPI, 7066c92544dSBjoern A. Zeeb }; 7076c92544dSBjoern A. Zeeb 7086c92544dSBjoern A. Zeeb #endif 709