1 // SPDX-License-Identifier: ISC 2 /* Copyright (C) 2020 MediaTek Inc. 3 * 4 */ 5 6 #if defined(__FreeBSD__) 7 #define LINUXKPI_PARAM_PREFIX mt7921_pci_ 8 #endif 9 10 #include <linux/kernel.h> 11 #include <linux/module.h> 12 #include <linux/pci.h> 13 14 #include "mt7921.h" 15 #include "mac.h" 16 #include "mcu.h" 17 #include "../trace.h" 18 19 static const struct pci_device_id mt7921_pci_device_table[] = { 20 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7961) }, 21 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7922) }, 22 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x0608) }, 23 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x0616) }, 24 { }, 25 }; 26 27 static bool mt7921_disable_aspm; 28 module_param_named(disable_aspm, mt7921_disable_aspm, bool, 0644); 29 MODULE_PARM_DESC(disable_aspm, "disable PCI ASPM support"); 30 31 static void 32 mt7921_rx_poll_complete(struct mt76_dev *mdev, enum mt76_rxq_id q) 33 { 34 struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76); 35 36 if (q == MT_RXQ_MAIN) 37 mt7921_irq_enable(dev, MT_INT_RX_DONE_DATA); 38 else if (q == MT_RXQ_MCU_WA) 39 mt7921_irq_enable(dev, MT_INT_RX_DONE_WM2); 40 else 41 mt7921_irq_enable(dev, MT_INT_RX_DONE_WM); 42 } 43 44 static irqreturn_t mt7921_irq_handler(int irq, void *dev_instance) 45 { 46 struct mt7921_dev *dev = dev_instance; 47 48 mt76_wr(dev, MT_WFDMA0_HOST_INT_ENA, 0); 49 50 if (!test_bit(MT76_STATE_INITIALIZED, &dev->mphy.state)) 51 return IRQ_NONE; 52 53 tasklet_schedule(&dev->irq_tasklet); 54 55 return IRQ_HANDLED; 56 } 57 58 static void mt7921_irq_tasklet(unsigned long data) 59 { 60 struct mt7921_dev *dev = (struct mt7921_dev *)data; 61 u32 intr, mask = 0; 62 63 mt76_wr(dev, MT_WFDMA0_HOST_INT_ENA, 0); 64 65 intr = mt76_rr(dev, MT_WFDMA0_HOST_INT_STA); 66 intr &= dev->mt76.mmio.irqmask; 67 mt76_wr(dev, MT_WFDMA0_HOST_INT_STA, intr); 68 69 trace_dev_irq(&dev->mt76, intr, dev->mt76.mmio.irqmask); 70 71 mask |= intr & MT_INT_RX_DONE_ALL; 72 if (intr & MT_INT_TX_DONE_MCU) 73 mask |= MT_INT_TX_DONE_MCU; 74 75 if (intr & MT_INT_MCU_CMD) { 76 u32 intr_sw; 77 78 intr_sw = mt76_rr(dev, MT_MCU_CMD); 79 /* ack MCU2HOST_SW_INT_STA */ 80 mt76_wr(dev, MT_MCU_CMD, intr_sw); 81 if (intr_sw & MT_MCU_CMD_WAKE_RX_PCIE) { 82 mask |= MT_INT_RX_DONE_DATA; 83 intr |= MT_INT_RX_DONE_DATA; 84 } 85 } 86 87 mt76_set_irq_mask(&dev->mt76, MT_WFDMA0_HOST_INT_ENA, mask, 0); 88 89 if (intr & MT_INT_TX_DONE_ALL) 90 napi_schedule(&dev->mt76.tx_napi); 91 92 if (intr & MT_INT_RX_DONE_WM) 93 napi_schedule(&dev->mt76.napi[MT_RXQ_MCU]); 94 95 if (intr & MT_INT_RX_DONE_WM2) 96 napi_schedule(&dev->mt76.napi[MT_RXQ_MCU_WA]); 97 98 if (intr & MT_INT_RX_DONE_DATA) 99 napi_schedule(&dev->mt76.napi[MT_RXQ_MAIN]); 100 } 101 102 static int mt7921e_init_reset(struct mt7921_dev *dev) 103 { 104 return mt7921_wpdma_reset(dev, true); 105 } 106 107 static void mt7921e_unregister_device(struct mt7921_dev *dev) 108 { 109 int i; 110 struct mt76_connac_pm *pm = &dev->pm; 111 112 cancel_work_sync(&dev->init_work); 113 mt76_unregister_device(&dev->mt76); 114 mt76_for_each_q_rx(&dev->mt76, i) 115 napi_disable(&dev->mt76.napi[i]); 116 cancel_delayed_work_sync(&pm->ps_work); 117 cancel_work_sync(&pm->wake_work); 118 119 mt7921_tx_token_put(dev); 120 mt7921_mcu_drv_pmctrl(dev); 121 mt7921_dma_cleanup(dev); 122 mt7921_wfsys_reset(dev); 123 skb_queue_purge(&dev->mt76.mcu.res_q); 124 125 tasklet_disable(&dev->irq_tasklet); 126 } 127 128 static u32 __mt7921_reg_addr(struct mt7921_dev *dev, u32 addr) 129 { 130 static const struct mt76_connac_reg_map fixed_map[] = { 131 { 0x820d0000, 0x30000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */ 132 { 0x820ed000, 0x24800, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */ 133 { 0x820e4000, 0x21000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */ 134 { 0x820e7000, 0x21e00, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */ 135 { 0x820eb000, 0x24200, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */ 136 { 0x820e2000, 0x20800, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */ 137 { 0x820e3000, 0x20c00, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */ 138 { 0x820e5000, 0x21400, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */ 139 { 0x00400000, 0x80000, 0x10000 }, /* WF_MCU_SYSRAM */ 140 { 0x00410000, 0x90000, 0x10000 }, /* WF_MCU_SYSRAM (configure register) */ 141 { 0x40000000, 0x70000, 0x10000 }, /* WF_UMAC_SYSRAM */ 142 { 0x54000000, 0x02000, 0x01000 }, /* WFDMA PCIE0 MCU DMA0 */ 143 { 0x55000000, 0x03000, 0x01000 }, /* WFDMA PCIE0 MCU DMA1 */ 144 { 0x58000000, 0x06000, 0x01000 }, /* WFDMA PCIE1 MCU DMA0 (MEM_DMA) */ 145 { 0x59000000, 0x07000, 0x01000 }, /* WFDMA PCIE1 MCU DMA1 */ 146 { 0x7c000000, 0xf0000, 0x10000 }, /* CONN_INFRA */ 147 { 0x7c020000, 0xd0000, 0x10000 }, /* CONN_INFRA, WFDMA */ 148 { 0x7c060000, 0xe0000, 0x10000 }, /* CONN_INFRA, conn_host_csr_top */ 149 { 0x80020000, 0xb0000, 0x10000 }, /* WF_TOP_MISC_OFF */ 150 { 0x81020000, 0xc0000, 0x10000 }, /* WF_TOP_MISC_ON */ 151 { 0x820c0000, 0x08000, 0x04000 }, /* WF_UMAC_TOP (PLE) */ 152 { 0x820c8000, 0x0c000, 0x02000 }, /* WF_UMAC_TOP (PSE) */ 153 { 0x820cc000, 0x0e000, 0x01000 }, /* WF_UMAC_TOP (PP) */ 154 { 0x820cd000, 0x0f000, 0x01000 }, /* WF_MDP_TOP */ 155 { 0x74030000, 0x10000, 0x10000 }, /* PCIE_MAC_IREG */ 156 { 0x820ce000, 0x21c00, 0x00200 }, /* WF_LMAC_TOP (WF_SEC) */ 157 { 0x820cf000, 0x22000, 0x01000 }, /* WF_LMAC_TOP (WF_PF) */ 158 { 0x820e0000, 0x20000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */ 159 { 0x820e1000, 0x20400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */ 160 { 0x820e9000, 0x23400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */ 161 { 0x820ea000, 0x24000, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */ 162 { 0x820ec000, 0x24600, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_INT) */ 163 { 0x820f0000, 0xa0000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */ 164 { 0x820f1000, 0xa0600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */ 165 { 0x820f2000, 0xa0800, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */ 166 { 0x820f3000, 0xa0c00, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */ 167 { 0x820f4000, 0xa1000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */ 168 { 0x820f5000, 0xa1400, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */ 169 { 0x820f7000, 0xa1e00, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */ 170 { 0x820f9000, 0xa3400, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */ 171 { 0x820fa000, 0xa4000, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */ 172 { 0x820fb000, 0xa4200, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */ 173 { 0x820fc000, 0xa4600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_INT) */ 174 { 0x820fd000, 0xa4800, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */ 175 }; 176 int i; 177 178 if (addr < 0x100000) 179 return addr; 180 181 for (i = 0; i < ARRAY_SIZE(fixed_map); i++) { 182 u32 ofs; 183 184 if (addr < fixed_map[i].phys) 185 continue; 186 187 ofs = addr - fixed_map[i].phys; 188 if (ofs > fixed_map[i].size) 189 continue; 190 191 return fixed_map[i].maps + ofs; 192 } 193 194 if ((addr >= 0x18000000 && addr < 0x18c00000) || 195 (addr >= 0x70000000 && addr < 0x78000000) || 196 (addr >= 0x7c000000 && addr < 0x7c400000)) 197 return mt7921_reg_map_l1(dev, addr); 198 199 dev_err(dev->mt76.dev, "Access currently unsupported address %08x\n", 200 addr); 201 202 return 0; 203 } 204 205 static u32 mt7921_rr(struct mt76_dev *mdev, u32 offset) 206 { 207 struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76); 208 u32 addr = __mt7921_reg_addr(dev, offset); 209 210 return dev->bus_ops->rr(mdev, addr); 211 } 212 213 static void mt7921_wr(struct mt76_dev *mdev, u32 offset, u32 val) 214 { 215 struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76); 216 u32 addr = __mt7921_reg_addr(dev, offset); 217 218 dev->bus_ops->wr(mdev, addr, val); 219 } 220 221 static u32 mt7921_rmw(struct mt76_dev *mdev, u32 offset, u32 mask, u32 val) 222 { 223 struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76); 224 u32 addr = __mt7921_reg_addr(dev, offset); 225 226 return dev->bus_ops->rmw(mdev, addr, mask, val); 227 } 228 229 static int mt7921_pci_probe(struct pci_dev *pdev, 230 const struct pci_device_id *id) 231 { 232 static const struct mt76_driver_ops drv_ops = { 233 /* txwi_size = txd size + txp size */ 234 .txwi_size = MT_TXD_SIZE + sizeof(struct mt76_connac_hw_txp), 235 .drv_flags = MT_DRV_TXWI_NO_FREE | MT_DRV_HW_MGMT_TXQ, 236 .survey_flags = SURVEY_INFO_TIME_TX | 237 SURVEY_INFO_TIME_RX | 238 SURVEY_INFO_TIME_BSS_RX, 239 .token_size = MT7921_TOKEN_SIZE, 240 .tx_prepare_skb = mt7921e_tx_prepare_skb, 241 .tx_complete_skb = mt76_connac_tx_complete_skb, 242 .rx_check = mt7921_rx_check, 243 .rx_skb = mt7921_queue_rx_skb, 244 .rx_poll_complete = mt7921_rx_poll_complete, 245 .sta_ps = mt7921_sta_ps, 246 .sta_add = mt7921_mac_sta_add, 247 .sta_assoc = mt7921_mac_sta_assoc, 248 .sta_remove = mt7921_mac_sta_remove, 249 .update_survey = mt7921_update_channel, 250 }; 251 static const struct mt7921_hif_ops mt7921_pcie_ops = { 252 .init_reset = mt7921e_init_reset, 253 .reset = mt7921e_mac_reset, 254 .mcu_init = mt7921e_mcu_init, 255 .drv_own = mt7921e_mcu_drv_pmctrl, 256 .fw_own = mt7921e_mcu_fw_pmctrl, 257 }; 258 259 struct mt76_bus_ops *bus_ops; 260 struct mt7921_dev *dev; 261 struct mt76_dev *mdev; 262 int ret; 263 264 ret = pcim_enable_device(pdev); 265 if (ret) 266 return ret; 267 268 ret = pcim_iomap_regions(pdev, BIT(0), pci_name(pdev)); 269 if (ret) 270 return ret; 271 272 pci_set_master(pdev); 273 274 ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); 275 if (ret < 0) 276 return ret; 277 278 ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); 279 if (ret) 280 goto err_free_pci_vec; 281 282 if (mt7921_disable_aspm) 283 mt76_pci_disable_aspm(pdev); 284 285 mdev = mt76_alloc_device(&pdev->dev, sizeof(*dev), &mt7921_ops, 286 &drv_ops); 287 if (!mdev) { 288 ret = -ENOMEM; 289 goto err_free_pci_vec; 290 } 291 292 pci_set_drvdata(pdev, mdev); 293 294 dev = container_of(mdev, struct mt7921_dev, mt76); 295 dev->hif_ops = &mt7921_pcie_ops; 296 297 mt76_mmio_init(&dev->mt76, pcim_iomap_table(pdev)[0]); 298 tasklet_init(&dev->irq_tasklet, mt7921_irq_tasklet, (unsigned long)dev); 299 300 dev->phy.dev = dev; 301 dev->phy.mt76 = &dev->mt76.phy; 302 dev->mt76.phy.priv = &dev->phy; 303 dev->bus_ops = dev->mt76.bus; 304 bus_ops = devm_kmemdup(dev->mt76.dev, dev->bus_ops, sizeof(*bus_ops), 305 GFP_KERNEL); 306 if (!bus_ops) { 307 ret = -ENOMEM; 308 goto err_free_dev; 309 } 310 311 bus_ops->rr = mt7921_rr; 312 bus_ops->wr = mt7921_wr; 313 bus_ops->rmw = mt7921_rmw; 314 dev->mt76.bus = bus_ops; 315 316 ret = __mt7921e_mcu_drv_pmctrl(dev); 317 if (ret) 318 goto err_free_dev; 319 320 mdev->rev = (mt7921_l1_rr(dev, MT_HW_CHIPID) << 16) | 321 (mt7921_l1_rr(dev, MT_HW_REV) & 0xff); 322 dev_info(mdev->dev, "ASIC revision: %04x\n", mdev->rev); 323 324 mt76_wr(dev, MT_WFDMA0_HOST_INT_ENA, 0); 325 326 mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0xff); 327 328 ret = devm_request_irq(mdev->dev, pdev->irq, mt7921_irq_handler, 329 IRQF_SHARED, KBUILD_MODNAME, dev); 330 if (ret) 331 goto err_free_dev; 332 333 ret = mt7921_dma_init(dev); 334 if (ret) 335 goto err_free_irq; 336 337 ret = mt7921_register_device(dev); 338 if (ret) 339 goto err_free_irq; 340 341 return 0; 342 343 err_free_irq: 344 devm_free_irq(&pdev->dev, pdev->irq, dev); 345 err_free_dev: 346 mt76_free_device(&dev->mt76); 347 err_free_pci_vec: 348 pci_free_irq_vectors(pdev); 349 350 return ret; 351 } 352 353 static void mt7921_pci_remove(struct pci_dev *pdev) 354 { 355 struct mt76_dev *mdev = pci_get_drvdata(pdev); 356 struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76); 357 358 mt7921e_unregister_device(dev); 359 devm_free_irq(&pdev->dev, pdev->irq, dev); 360 mt76_free_device(&dev->mt76); 361 pci_free_irq_vectors(pdev); 362 } 363 364 #if !defined(__FreeBSD__) || defined(CONFIG_PM_SLEEP) 365 static int mt7921_pci_suspend(struct device *device) 366 { 367 struct pci_dev *pdev = to_pci_dev(device); 368 struct mt76_dev *mdev = pci_get_drvdata(pdev); 369 struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76); 370 struct mt76_connac_pm *pm = &dev->pm; 371 int i, err; 372 373 pm->suspended = true; 374 flush_work(&dev->reset_work); 375 cancel_delayed_work_sync(&pm->ps_work); 376 cancel_work_sync(&pm->wake_work); 377 378 err = mt7921_mcu_drv_pmctrl(dev); 379 if (err < 0) 380 goto restore_suspend; 381 382 err = mt76_connac_mcu_set_hif_suspend(mdev, true); 383 if (err) 384 goto restore_suspend; 385 386 /* always enable deep sleep during suspend to reduce 387 * power consumption 388 */ 389 mt76_connac_mcu_set_deep_sleep(&dev->mt76, true); 390 391 napi_disable(&mdev->tx_napi); 392 mt76_worker_disable(&mdev->tx_worker); 393 394 mt76_for_each_q_rx(mdev, i) { 395 napi_disable(&mdev->napi[i]); 396 } 397 398 /* wait until dma is idle */ 399 mt76_poll(dev, MT_WFDMA0_GLO_CFG, 400 MT_WFDMA0_GLO_CFG_TX_DMA_BUSY | 401 MT_WFDMA0_GLO_CFG_RX_DMA_BUSY, 0, 1000); 402 403 /* put dma disabled */ 404 mt76_clear(dev, MT_WFDMA0_GLO_CFG, 405 MT_WFDMA0_GLO_CFG_TX_DMA_EN | MT_WFDMA0_GLO_CFG_RX_DMA_EN); 406 407 /* disable interrupt */ 408 mt76_wr(dev, MT_WFDMA0_HOST_INT_ENA, 0); 409 mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0x0); 410 synchronize_irq(pdev->irq); 411 tasklet_kill(&dev->irq_tasklet); 412 413 err = mt7921_mcu_fw_pmctrl(dev); 414 if (err) 415 goto restore_napi; 416 417 return 0; 418 419 restore_napi: 420 mt76_for_each_q_rx(mdev, i) { 421 napi_enable(&mdev->napi[i]); 422 } 423 napi_enable(&mdev->tx_napi); 424 425 if (!pm->ds_enable) 426 mt76_connac_mcu_set_deep_sleep(&dev->mt76, false); 427 428 mt76_connac_mcu_set_hif_suspend(mdev, false); 429 430 restore_suspend: 431 pm->suspended = false; 432 433 if (err < 0) 434 mt7921_reset(&dev->mt76); 435 436 return err; 437 } 438 439 static int mt7921_pci_resume(struct device *device) 440 { 441 struct pci_dev *pdev = to_pci_dev(device); 442 struct mt76_dev *mdev = pci_get_drvdata(pdev); 443 struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76); 444 struct mt76_connac_pm *pm = &dev->pm; 445 int i, err; 446 447 err = mt7921_mcu_drv_pmctrl(dev); 448 if (err < 0) 449 goto failed; 450 451 mt7921_wpdma_reinit_cond(dev); 452 453 /* enable interrupt */ 454 mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0xff); 455 mt7921_irq_enable(dev, MT_INT_RX_DONE_ALL | MT_INT_TX_DONE_ALL | 456 MT_INT_MCU_CMD); 457 mt76_set(dev, MT_MCU2HOST_SW_INT_ENA, MT_MCU_CMD_WAKE_RX_PCIE); 458 459 /* put dma enabled */ 460 mt76_set(dev, MT_WFDMA0_GLO_CFG, 461 MT_WFDMA0_GLO_CFG_TX_DMA_EN | MT_WFDMA0_GLO_CFG_RX_DMA_EN); 462 463 mt76_worker_enable(&mdev->tx_worker); 464 465 local_bh_disable(); 466 mt76_for_each_q_rx(mdev, i) { 467 napi_enable(&mdev->napi[i]); 468 napi_schedule(&mdev->napi[i]); 469 } 470 napi_enable(&mdev->tx_napi); 471 napi_schedule(&mdev->tx_napi); 472 local_bh_enable(); 473 474 /* restore previous ds setting */ 475 if (!pm->ds_enable) 476 mt76_connac_mcu_set_deep_sleep(&dev->mt76, false); 477 478 err = mt76_connac_mcu_set_hif_suspend(mdev, false); 479 failed: 480 pm->suspended = false; 481 482 if (err < 0) 483 mt7921_reset(&dev->mt76); 484 485 return err; 486 } 487 #endif 488 489 static DEFINE_SIMPLE_DEV_PM_OPS(mt7921_pm_ops, mt7921_pci_suspend, mt7921_pci_resume); 490 491 static struct pci_driver mt7921_pci_driver = { 492 .name = KBUILD_MODNAME, 493 .id_table = mt7921_pci_device_table, 494 .probe = mt7921_pci_probe, 495 .remove = mt7921_pci_remove, 496 .driver.pm = pm_sleep_ptr(&mt7921_pm_ops), 497 }; 498 499 module_pci_driver(mt7921_pci_driver); 500 501 MODULE_DEVICE_TABLE(pci, mt7921_pci_device_table); 502 MODULE_FIRMWARE(MT7921_FIRMWARE_WM); 503 MODULE_FIRMWARE(MT7921_ROM_PATCH); 504 MODULE_FIRMWARE(MT7922_FIRMWARE_WM); 505 MODULE_FIRMWARE(MT7922_ROM_PATCH); 506 MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>"); 507 MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>"); 508 MODULE_LICENSE("Dual BSD/GPL"); 509 #if defined(__FreeBSD__) 510 MODULE_VERSION(mt7921_pci, 1); 511 MODULE_DEPEND(mt7921_pci, linuxkpi, 1, 1, 1); 512 MODULE_DEPEND(mt7921_pci, linuxkpi_wlan, 1, 1, 1); 513 MODULE_DEPEND(mt7921_pci, mt76_core, 1, 1, 1); 514 #endif 515