1 // SPDX-License-Identifier: ISC 2 /* 3 * Copyright (C) 2022 MediaTek Inc. 4 */ 5 6 #include <linux/relay.h> 7 #include "mt7996.h" 8 #include "eeprom.h" 9 #include "mcu.h" 10 #include "mac.h" 11 12 #define FW_BIN_LOG_MAGIC 0x44d9c99a 13 14 /** global debugfs **/ 15 16 struct hw_queue_map { 17 const char *name; 18 u8 index; 19 u8 pid; 20 u8 qid; 21 }; 22 23 static int 24 mt7996_implicit_txbf_set(void *data, u64 val) 25 { 26 struct mt7996_dev *dev = data; 27 28 /* The existing connected stations shall reconnect to apply 29 * new implicit txbf configuration. 30 */ 31 dev->ibf = !!val; 32 33 return mt7996_mcu_set_txbf(dev, BF_HW_EN_UPDATE); 34 } 35 36 static int 37 mt7996_implicit_txbf_get(void *data, u64 *val) 38 { 39 struct mt7996_dev *dev = data; 40 41 *val = dev->ibf; 42 43 return 0; 44 } 45 46 DEFINE_DEBUGFS_ATTRIBUTE(fops_implicit_txbf, mt7996_implicit_txbf_get, 47 mt7996_implicit_txbf_set, "%lld\n"); 48 49 /* test knob of system error recovery */ 50 static ssize_t 51 mt7996_sys_recovery_set(struct file *file, const char __user *user_buf, 52 size_t count, loff_t *ppos) 53 { 54 struct mt7996_phy *phy = file->private_data; 55 struct mt7996_dev *dev = phy->dev; 56 bool band = phy->mt76->band_idx; 57 char buf[16]; 58 int ret = 0; 59 u16 val; 60 61 if (count >= sizeof(buf)) 62 return -EINVAL; 63 64 if (copy_from_user(buf, user_buf, count)) 65 return -EFAULT; 66 67 if (count && buf[count - 1] == '\n') 68 buf[count - 1] = '\0'; 69 else 70 buf[count] = '\0'; 71 72 if (kstrtou16(buf, 0, &val)) 73 return -EINVAL; 74 75 switch (val) { 76 /* 77 * 0: grab firmware current SER state. 78 * 1: trigger & enable system error L1 recovery. 79 * 2: trigger & enable system error L2 recovery. 80 * 3: trigger & enable system error L3 rx abort. 81 * 4: trigger & enable system error L3 tx abort 82 * 5: trigger & enable system error L3 tx disable. 83 * 6: trigger & enable system error L3 bf recovery. 84 * 7: trigger & enable system error L4 mdp recovery. 85 * 8: trigger & enable system error full recovery. 86 * 9: trigger firmware crash. 87 */ 88 case UNI_CMD_SER_QUERY: 89 ret = mt7996_mcu_set_ser(dev, UNI_CMD_SER_QUERY, 0, band); 90 break; 91 case UNI_CMD_SER_SET_RECOVER_L1: 92 case UNI_CMD_SER_SET_RECOVER_L2: 93 case UNI_CMD_SER_SET_RECOVER_L3_RX_ABORT: 94 case UNI_CMD_SER_SET_RECOVER_L3_TX_ABORT: 95 case UNI_CMD_SER_SET_RECOVER_L3_TX_DISABLE: 96 case UNI_CMD_SER_SET_RECOVER_L3_BF: 97 case UNI_CMD_SER_SET_RECOVER_L4_MDP: 98 ret = mt7996_mcu_set_ser(dev, UNI_CMD_SER_SET, BIT(val), band); 99 if (ret) 100 return ret; 101 102 ret = mt7996_mcu_set_ser(dev, UNI_CMD_SER_TRIGGER, val, band); 103 break; 104 105 /* enable full chip reset */ 106 case UNI_CMD_SER_SET_RECOVER_FULL: 107 mt76_set(dev, MT_WFDMA0_MCU_HOST_INT_ENA, MT_MCU_CMD_WDT_MASK); 108 dev->recovery.state |= MT_MCU_CMD_WDT_MASK; 109 mt7996_reset(dev); 110 break; 111 112 /* WARNING: trigger firmware crash */ 113 case UNI_CMD_SER_SET_SYSTEM_ASSERT: 114 ret = mt7996_mcu_trigger_assert(dev); 115 if (ret) 116 return ret; 117 break; 118 default: 119 break; 120 } 121 122 return ret ? ret : count; 123 } 124 125 static ssize_t 126 mt7996_sys_recovery_get(struct file *file, char __user *user_buf, 127 size_t count, loff_t *ppos) 128 { 129 struct mt7996_phy *phy = file->private_data; 130 struct mt7996_dev *dev = phy->dev; 131 char *buff; 132 int desc = 0; 133 ssize_t ret; 134 static const size_t bufsz = 1024; 135 136 buff = kmalloc(bufsz, GFP_KERNEL); 137 if (!buff) 138 return -ENOMEM; 139 140 /* HELP */ 141 desc += scnprintf(buff + desc, bufsz - desc, 142 "Please echo the correct value ...\n"); 143 desc += scnprintf(buff + desc, bufsz - desc, 144 "0: grab firmware transient SER state\n"); 145 desc += scnprintf(buff + desc, bufsz - desc, 146 "1: trigger system error L1 recovery\n"); 147 desc += scnprintf(buff + desc, bufsz - desc, 148 "2: trigger system error L2 recovery\n"); 149 desc += scnprintf(buff + desc, bufsz - desc, 150 "3: trigger system error L3 rx abort\n"); 151 desc += scnprintf(buff + desc, bufsz - desc, 152 "4: trigger system error L3 tx abort\n"); 153 desc += scnprintf(buff + desc, bufsz - desc, 154 "5: trigger system error L3 tx disable\n"); 155 desc += scnprintf(buff + desc, bufsz - desc, 156 "6: trigger system error L3 bf recovery\n"); 157 desc += scnprintf(buff + desc, bufsz - desc, 158 "7: trigger system error L4 mdp recovery\n"); 159 desc += scnprintf(buff + desc, bufsz - desc, 160 "8: trigger system error full recovery\n"); 161 desc += scnprintf(buff + desc, bufsz - desc, 162 "9: trigger firmware crash\n"); 163 164 /* SER statistics */ 165 desc += scnprintf(buff + desc, bufsz - desc, 166 "\nlet's dump firmware SER statistics...\n"); 167 desc += scnprintf(buff + desc, bufsz - desc, 168 "::E R , SER_STATUS = 0x%08x\n", 169 mt76_rr(dev, MT_SWDEF_SER_STATS)); 170 desc += scnprintf(buff + desc, bufsz - desc, 171 "::E R , SER_PLE_ERR = 0x%08x\n", 172 mt76_rr(dev, MT_SWDEF_PLE_STATS)); 173 desc += scnprintf(buff + desc, bufsz - desc, 174 "::E R , SER_PLE_ERR_1 = 0x%08x\n", 175 mt76_rr(dev, MT_SWDEF_PLE1_STATS)); 176 desc += scnprintf(buff + desc, bufsz - desc, 177 "::E R , SER_PLE_ERR_AMSDU = 0x%08x\n", 178 mt76_rr(dev, MT_SWDEF_PLE_AMSDU_STATS)); 179 desc += scnprintf(buff + desc, bufsz - desc, 180 "::E R , SER_PSE_ERR = 0x%08x\n", 181 mt76_rr(dev, MT_SWDEF_PSE_STATS)); 182 desc += scnprintf(buff + desc, bufsz - desc, 183 "::E R , SER_PSE_ERR_1 = 0x%08x\n", 184 mt76_rr(dev, MT_SWDEF_PSE1_STATS)); 185 desc += scnprintf(buff + desc, bufsz - desc, 186 "::E R , SER_LMAC_WISR6_B0 = 0x%08x\n", 187 mt76_rr(dev, MT_SWDEF_LAMC_WISR6_BN0_STATS)); 188 desc += scnprintf(buff + desc, bufsz - desc, 189 "::E R , SER_LMAC_WISR6_B1 = 0x%08x\n", 190 mt76_rr(dev, MT_SWDEF_LAMC_WISR6_BN1_STATS)); 191 desc += scnprintf(buff + desc, bufsz - desc, 192 "::E R , SER_LMAC_WISR6_B2 = 0x%08x\n", 193 mt76_rr(dev, MT_SWDEF_LAMC_WISR6_BN2_STATS)); 194 desc += scnprintf(buff + desc, bufsz - desc, 195 "::E R , SER_LMAC_WISR7_B0 = 0x%08x\n", 196 mt76_rr(dev, MT_SWDEF_LAMC_WISR7_BN0_STATS)); 197 desc += scnprintf(buff + desc, bufsz - desc, 198 "::E R , SER_LMAC_WISR7_B1 = 0x%08x\n", 199 mt76_rr(dev, MT_SWDEF_LAMC_WISR7_BN1_STATS)); 200 desc += scnprintf(buff + desc, bufsz - desc, 201 "::E R , SER_LMAC_WISR7_B2 = 0x%08x\n", 202 mt76_rr(dev, MT_SWDEF_LAMC_WISR7_BN2_STATS)); 203 desc += scnprintf(buff + desc, bufsz - desc, 204 "\nSYS_RESET_COUNT: WM %d, WA %d\n", 205 dev->recovery.wm_reset_count, 206 dev->recovery.wa_reset_count); 207 208 ret = simple_read_from_buffer(user_buf, count, ppos, buff, desc); 209 kfree(buff); 210 return ret; 211 } 212 213 static const struct file_operations mt7996_sys_recovery_ops = { 214 .write = mt7996_sys_recovery_set, 215 .read = mt7996_sys_recovery_get, 216 .open = simple_open, 217 .llseek = default_llseek, 218 }; 219 220 static int 221 mt7996_radar_trigger(void *data, u64 val) 222 { 223 struct mt7996_dev *dev = data; 224 225 if (val > MT_RX_SEL2) 226 return -EINVAL; 227 228 return mt7996_mcu_rdd_cmd(dev, RDD_RADAR_EMULATE, 229 val, 0, 0); 230 } 231 232 DEFINE_DEBUGFS_ATTRIBUTE(fops_radar_trigger, NULL, 233 mt7996_radar_trigger, "%lld\n"); 234 235 static int 236 mt7996_rdd_monitor(struct seq_file *s, void *data) 237 { 238 struct mt7996_dev *dev = dev_get_drvdata(s->private); 239 struct cfg80211_chan_def *chandef = &dev->rdd2_chandef; 240 const char *bw; 241 int ret = 0; 242 243 mutex_lock(&dev->mt76.mutex); 244 245 if (!cfg80211_chandef_valid(chandef)) { 246 ret = -EINVAL; 247 goto out; 248 } 249 250 if (!dev->rdd2_phy) { 251 seq_puts(s, "not running\n"); 252 goto out; 253 } 254 255 switch (chandef->width) { 256 case NL80211_CHAN_WIDTH_40: 257 bw = "40"; 258 break; 259 case NL80211_CHAN_WIDTH_80: 260 bw = "80"; 261 break; 262 case NL80211_CHAN_WIDTH_160: 263 bw = "160"; 264 break; 265 case NL80211_CHAN_WIDTH_80P80: 266 bw = "80P80"; 267 break; 268 default: 269 bw = "20"; 270 break; 271 } 272 273 seq_printf(s, "channel %d (%d MHz) width %s MHz center1: %d MHz\n", 274 chandef->chan->hw_value, chandef->chan->center_freq, 275 bw, chandef->center_freq1); 276 out: 277 mutex_unlock(&dev->mt76.mutex); 278 279 return ret; 280 } 281 282 static int 283 mt7996_fw_debug_wm_set(void *data, u64 val) 284 { 285 struct mt7996_dev *dev = data; 286 enum { 287 DEBUG_TXCMD = 62, 288 DEBUG_CMD_RPT_TX, 289 DEBUG_CMD_RPT_TRIG, 290 DEBUG_SPL, 291 DEBUG_RPT_RX, 292 DEBUG_RPT_RA = 68, 293 } debug; 294 bool tx, rx, en; 295 int ret; 296 297 dev->fw_debug_wm = val ? MCU_FW_LOG_TO_HOST : 0; 298 299 if (dev->fw_debug_bin) 300 val = MCU_FW_LOG_RELAY; 301 else 302 val = dev->fw_debug_wm; 303 304 tx = dev->fw_debug_wm || (dev->fw_debug_bin & BIT(1)); 305 rx = dev->fw_debug_wm || (dev->fw_debug_bin & BIT(2)); 306 en = dev->fw_debug_wm || (dev->fw_debug_bin & BIT(0)); 307 308 ret = mt7996_mcu_fw_log_2_host(dev, MCU_FW_LOG_WM, val); 309 if (ret) 310 return ret; 311 312 for (debug = DEBUG_TXCMD; debug <= DEBUG_RPT_RA; debug++) { 313 if (debug == 67) 314 continue; 315 316 if (debug == DEBUG_RPT_RX) 317 val = en && rx; 318 else 319 val = en && tx; 320 321 ret = mt7996_mcu_fw_dbg_ctrl(dev, debug, val); 322 if (ret) 323 return ret; 324 } 325 326 return 0; 327 } 328 329 static int 330 mt7996_fw_debug_wm_get(void *data, u64 *val) 331 { 332 struct mt7996_dev *dev = data; 333 334 *val = dev->fw_debug_wm; 335 336 return 0; 337 } 338 339 DEFINE_DEBUGFS_ATTRIBUTE(fops_fw_debug_wm, mt7996_fw_debug_wm_get, 340 mt7996_fw_debug_wm_set, "%lld\n"); 341 342 static int 343 mt7996_fw_debug_wa_set(void *data, u64 val) 344 { 345 struct mt7996_dev *dev = data; 346 int ret; 347 348 dev->fw_debug_wa = val ? MCU_FW_LOG_TO_HOST : 0; 349 350 ret = mt7996_mcu_fw_log_2_host(dev, MCU_FW_LOG_WA, dev->fw_debug_wa); 351 if (ret) 352 return ret; 353 354 return mt7996_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(SET), MCU_WA_PARAM_PDMA_RX, 355 !!dev->fw_debug_wa, 0); 356 } 357 358 static int 359 mt7996_fw_debug_wa_get(void *data, u64 *val) 360 { 361 struct mt7996_dev *dev = data; 362 363 *val = dev->fw_debug_wa; 364 365 return 0; 366 } 367 368 DEFINE_DEBUGFS_ATTRIBUTE(fops_fw_debug_wa, mt7996_fw_debug_wa_get, 369 mt7996_fw_debug_wa_set, "%lld\n"); 370 371 static struct dentry * 372 create_buf_file_cb(const char *filename, struct dentry *parent, umode_t mode, 373 struct rchan_buf *buf, int *is_global) 374 { 375 struct dentry *f; 376 377 f = debugfs_create_file("fwlog_data", mode, parent, buf, 378 &relay_file_operations); 379 if (IS_ERR(f)) 380 return NULL; 381 382 *is_global = 1; 383 384 return f; 385 } 386 387 static int 388 remove_buf_file_cb(struct dentry *f) 389 { 390 debugfs_remove(f); 391 392 return 0; 393 } 394 395 static int 396 mt7996_fw_debug_bin_set(void *data, u64 val) 397 { 398 static struct rchan_callbacks relay_cb = { 399 .create_buf_file = create_buf_file_cb, 400 .remove_buf_file = remove_buf_file_cb, 401 }; 402 struct mt7996_dev *dev = data; 403 404 if (!dev->relay_fwlog) 405 dev->relay_fwlog = relay_open("fwlog_data", dev->debugfs_dir, 406 1500, 512, &relay_cb, NULL); 407 if (!dev->relay_fwlog) 408 return -ENOMEM; 409 410 dev->fw_debug_bin = val; 411 412 relay_reset(dev->relay_fwlog); 413 414 return mt7996_fw_debug_wm_set(dev, dev->fw_debug_wm); 415 } 416 417 static int 418 mt7996_fw_debug_bin_get(void *data, u64 *val) 419 { 420 struct mt7996_dev *dev = data; 421 422 *val = dev->fw_debug_bin; 423 424 return 0; 425 } 426 427 DEFINE_DEBUGFS_ATTRIBUTE(fops_fw_debug_bin, mt7996_fw_debug_bin_get, 428 mt7996_fw_debug_bin_set, "%lld\n"); 429 430 static int 431 mt7996_fw_util_wa_show(struct seq_file *file, void *data) 432 { 433 struct mt7996_dev *dev = file->private; 434 435 if (dev->fw_debug_wa) 436 return mt7996_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(QUERY), 437 MCU_WA_PARAM_CPU_UTIL, 0, 0); 438 439 return 0; 440 } 441 442 DEFINE_SHOW_ATTRIBUTE(mt7996_fw_util_wa); 443 444 static void 445 mt7996_ampdu_stat_read_phy(struct mt7996_phy *phy, struct seq_file *file) 446 { 447 struct mt7996_dev *dev = phy->dev; 448 int bound[15], range[8], i; 449 u8 band_idx = phy->mt76->band_idx; 450 451 /* Tx ampdu stat */ 452 for (i = 0; i < ARRAY_SIZE(range); i++) 453 range[i] = mt76_rr(dev, MT_MIB_ARNG(band_idx, i)); 454 455 for (i = 0; i < ARRAY_SIZE(bound); i++) 456 bound[i] = MT_MIB_ARNCR_RANGE(range[i / 2], i % 2) + 1; 457 458 seq_printf(file, "\nPhy %s, Phy band %d\n", 459 wiphy_name(phy->mt76->hw->wiphy), band_idx); 460 461 seq_printf(file, "Length: %8d | ", bound[0]); 462 for (i = 0; i < ARRAY_SIZE(bound) - 1; i++) 463 seq_printf(file, "%3d -%3d | ", 464 bound[i] + 1, bound[i + 1]); 465 466 seq_puts(file, "\nCount: "); 467 for (i = 0; i < ARRAY_SIZE(bound); i++) 468 seq_printf(file, "%8d | ", phy->mt76->aggr_stats[i]); 469 seq_puts(file, "\n"); 470 471 seq_printf(file, "BA miss count: %d\n", phy->mib.ba_miss_cnt); 472 } 473 474 static void 475 mt7996_txbf_stat_read_phy(struct mt7996_phy *phy, struct seq_file *s) 476 { 477 struct mt76_mib_stats *mib = &phy->mib; 478 static const char * const bw[] = { 479 "BW20", "BW40", "BW80", "BW160" 480 }; 481 482 /* Tx Beamformer monitor */ 483 seq_puts(s, "\nTx Beamformer applied PPDU counts: "); 484 485 seq_printf(s, "iBF: %d, eBF: %d\n", 486 mib->tx_bf_ibf_ppdu_cnt, 487 mib->tx_bf_ebf_ppdu_cnt); 488 489 /* Tx Beamformer Rx feedback monitor */ 490 seq_puts(s, "Tx Beamformer Rx feedback statistics: "); 491 492 seq_printf(s, "All: %d, HE: %d, VHT: %d, HT: %d, ", 493 mib->tx_bf_rx_fb_all_cnt, 494 mib->tx_bf_rx_fb_he_cnt, 495 mib->tx_bf_rx_fb_vht_cnt, 496 mib->tx_bf_rx_fb_ht_cnt); 497 498 seq_printf(s, "%s, NC: %d, NR: %d\n", 499 bw[mib->tx_bf_rx_fb_bw], 500 mib->tx_bf_rx_fb_nc_cnt, 501 mib->tx_bf_rx_fb_nr_cnt); 502 503 /* Tx Beamformee Rx NDPA & Tx feedback report */ 504 seq_printf(s, "Tx Beamformee successful feedback frames: %d\n", 505 mib->tx_bf_fb_cpl_cnt); 506 seq_printf(s, "Tx Beamformee feedback triggered counts: %d\n", 507 mib->tx_bf_fb_trig_cnt); 508 509 /* Tx SU & MU counters */ 510 seq_printf(s, "Tx multi-user Beamforming counts: %d\n", 511 mib->tx_mu_bf_cnt); 512 seq_printf(s, "Tx multi-user MPDU counts: %d\n", mib->tx_mu_mpdu_cnt); 513 seq_printf(s, "Tx multi-user successful MPDU counts: %d\n", 514 mib->tx_mu_acked_mpdu_cnt); 515 seq_printf(s, "Tx single-user successful MPDU counts: %d\n", 516 mib->tx_su_acked_mpdu_cnt); 517 518 seq_puts(s, "\n"); 519 } 520 521 static int 522 mt7996_tx_stats_show(struct seq_file *file, void *data) 523 { 524 struct mt7996_phy *phy = file->private; 525 struct mt7996_dev *dev = phy->dev; 526 struct mt76_mib_stats *mib = &phy->mib; 527 int i; 528 u32 attempts, success, per; 529 530 mutex_lock(&dev->mt76.mutex); 531 532 mt7996_mac_update_stats(phy); 533 mt7996_ampdu_stat_read_phy(phy, file); 534 535 attempts = mib->tx_mpdu_attempts_cnt; 536 success = mib->tx_mpdu_success_cnt; 537 per = attempts ? 100 - success * 100 / attempts : 100; 538 seq_printf(file, "Tx attempts: %8u (MPDUs)\n", attempts); 539 seq_printf(file, "Tx success: %8u (MPDUs)\n", success); 540 seq_printf(file, "Tx PER: %u%%\n", per); 541 542 mt7996_txbf_stat_read_phy(phy, file); 543 544 /* Tx amsdu info */ 545 seq_puts(file, "Tx MSDU statistics:\n"); 546 for (i = 0; i < ARRAY_SIZE(mib->tx_amsdu); i++) { 547 seq_printf(file, "AMSDU pack count of %d MSDU in TXD: %8d ", 548 i + 1, mib->tx_amsdu[i]); 549 if (mib->tx_amsdu_cnt) 550 seq_printf(file, "(%3d%%)\n", 551 mib->tx_amsdu[i] * 100 / mib->tx_amsdu_cnt); 552 else 553 seq_puts(file, "\n"); 554 } 555 556 mutex_unlock(&dev->mt76.mutex); 557 558 return 0; 559 } 560 561 DEFINE_SHOW_ATTRIBUTE(mt7996_tx_stats); 562 563 static void 564 mt7996_hw_queue_read(struct seq_file *s, u32 size, 565 const struct hw_queue_map *map) 566 { 567 struct mt7996_phy *phy = s->private; 568 struct mt7996_dev *dev = phy->dev; 569 u32 i, val; 570 571 val = mt76_rr(dev, MT_FL_Q_EMPTY); 572 for (i = 0; i < size; i++) { 573 u32 ctrl, head, tail, queued; 574 575 if (val & BIT(map[i].index)) 576 continue; 577 578 ctrl = BIT(31) | (map[i].pid << 10) | ((u32)map[i].qid << 24); 579 mt76_wr(dev, MT_FL_Q0_CTRL, ctrl); 580 581 head = mt76_get_field(dev, MT_FL_Q2_CTRL, 582 GENMASK(11, 0)); 583 tail = mt76_get_field(dev, MT_FL_Q2_CTRL, 584 GENMASK(27, 16)); 585 queued = mt76_get_field(dev, MT_FL_Q3_CTRL, 586 GENMASK(11, 0)); 587 588 seq_printf(s, "\t%s: ", map[i].name); 589 seq_printf(s, "queued:0x%03x head:0x%03x tail:0x%03x\n", 590 queued, head, tail); 591 } 592 } 593 594 static void 595 mt7996_sta_hw_queue_read(void *data, struct ieee80211_sta *sta) 596 { 597 struct mt7996_sta *msta = (struct mt7996_sta *)sta->drv_priv; 598 struct mt7996_dev *dev = msta->vif->phy->dev; 599 struct seq_file *s = data; 600 u8 ac; 601 602 for (ac = 0; ac < 4; ac++) { 603 u32 qlen, ctrl, val; 604 u32 idx = msta->wcid.idx >> 5; 605 u8 offs = msta->wcid.idx & GENMASK(4, 0); 606 607 ctrl = BIT(31) | BIT(11) | (ac << 24); 608 val = mt76_rr(dev, MT_PLE_AC_QEMPTY(ac, idx)); 609 610 if (val & BIT(offs)) 611 continue; 612 613 mt76_wr(dev, MT_FL_Q0_CTRL, ctrl | msta->wcid.idx); 614 qlen = mt76_get_field(dev, MT_FL_Q3_CTRL, 615 GENMASK(11, 0)); 616 seq_printf(s, "\tSTA %pM wcid %d: AC%d%d queued:%d\n", 617 sta->addr, msta->wcid.idx, 618 msta->vif->mt76.wmm_idx, ac, qlen); 619 } 620 } 621 622 static int 623 mt7996_hw_queues_show(struct seq_file *file, void *data) 624 { 625 struct mt7996_phy *phy = file->private; 626 struct mt7996_dev *dev = phy->dev; 627 static const struct hw_queue_map ple_queue_map[] = { 628 { "CPU_Q0", 0, 1, MT_CTX0 }, 629 { "CPU_Q1", 1, 1, MT_CTX0 + 1 }, 630 { "CPU_Q2", 2, 1, MT_CTX0 + 2 }, 631 { "CPU_Q3", 3, 1, MT_CTX0 + 3 }, 632 { "ALTX_Q0", 8, 2, MT_LMAC_ALTX0 }, 633 { "BMC_Q0", 9, 2, MT_LMAC_BMC0 }, 634 { "BCN_Q0", 10, 2, MT_LMAC_BCN0 }, 635 { "PSMP_Q0", 11, 2, MT_LMAC_PSMP0 }, 636 { "ALTX_Q1", 12, 2, MT_LMAC_ALTX0 + 4 }, 637 { "BMC_Q1", 13, 2, MT_LMAC_BMC0 + 4 }, 638 { "BCN_Q1", 14, 2, MT_LMAC_BCN0 + 4 }, 639 { "PSMP_Q1", 15, 2, MT_LMAC_PSMP0 + 4 }, 640 }; 641 static const struct hw_queue_map pse_queue_map[] = { 642 { "CPU Q0", 0, 1, MT_CTX0 }, 643 { "CPU Q1", 1, 1, MT_CTX0 + 1 }, 644 { "CPU Q2", 2, 1, MT_CTX0 + 2 }, 645 { "CPU Q3", 3, 1, MT_CTX0 + 3 }, 646 { "HIF_Q0", 8, 0, MT_HIF0 }, 647 { "HIF_Q1", 9, 0, MT_HIF0 + 1 }, 648 { "HIF_Q2", 10, 0, MT_HIF0 + 2 }, 649 { "HIF_Q3", 11, 0, MT_HIF0 + 3 }, 650 { "HIF_Q4", 12, 0, MT_HIF0 + 4 }, 651 { "HIF_Q5", 13, 0, MT_HIF0 + 5 }, 652 { "LMAC_Q", 16, 2, 0 }, 653 { "MDP_TXQ", 17, 2, 1 }, 654 { "MDP_RXQ", 18, 2, 2 }, 655 { "SEC_TXQ", 19, 2, 3 }, 656 { "SEC_RXQ", 20, 2, 4 }, 657 }; 658 u32 val, head, tail; 659 660 /* ple queue */ 661 val = mt76_rr(dev, MT_PLE_FREEPG_CNT); 662 head = mt76_get_field(dev, MT_PLE_FREEPG_HEAD_TAIL, GENMASK(11, 0)); 663 tail = mt76_get_field(dev, MT_PLE_FREEPG_HEAD_TAIL, GENMASK(27, 16)); 664 seq_puts(file, "PLE page info:\n"); 665 seq_printf(file, 666 "\tTotal free page: 0x%08x head: 0x%03x tail: 0x%03x\n", 667 val, head, tail); 668 669 val = mt76_rr(dev, MT_PLE_PG_HIF_GROUP); 670 head = mt76_get_field(dev, MT_PLE_HIF_PG_INFO, GENMASK(11, 0)); 671 tail = mt76_get_field(dev, MT_PLE_HIF_PG_INFO, GENMASK(27, 16)); 672 seq_printf(file, "\tHIF free page: 0x%03x res: 0x%03x used: 0x%03x\n", 673 val, head, tail); 674 675 seq_puts(file, "PLE non-empty queue info:\n"); 676 mt7996_hw_queue_read(file, ARRAY_SIZE(ple_queue_map), 677 &ple_queue_map[0]); 678 679 /* iterate per-sta ple queue */ 680 ieee80211_iterate_stations_atomic(phy->mt76->hw, 681 mt7996_sta_hw_queue_read, file); 682 /* pse queue */ 683 seq_puts(file, "PSE non-empty queue info:\n"); 684 mt7996_hw_queue_read(file, ARRAY_SIZE(pse_queue_map), 685 &pse_queue_map[0]); 686 687 return 0; 688 } 689 690 DEFINE_SHOW_ATTRIBUTE(mt7996_hw_queues); 691 692 static int 693 mt7996_xmit_queues_show(struct seq_file *file, void *data) 694 { 695 struct mt7996_phy *phy = file->private; 696 struct mt7996_dev *dev = phy->dev; 697 struct { 698 struct mt76_queue *q; 699 char *queue; 700 } queue_map[] = { 701 { phy->mt76->q_tx[MT_TXQ_BE], " MAIN" }, 702 { dev->mt76.q_mcu[MT_MCUQ_WM], " MCUWM" }, 703 { dev->mt76.q_mcu[MT_MCUQ_WA], " MCUWA" }, 704 { dev->mt76.q_mcu[MT_MCUQ_FWDL], "MCUFWDL" }, 705 }; 706 int i; 707 708 seq_puts(file, " queue | hw-queued | head | tail |\n"); 709 for (i = 0; i < ARRAY_SIZE(queue_map); i++) { 710 struct mt76_queue *q = queue_map[i].q; 711 712 if (!q) 713 continue; 714 715 seq_printf(file, " %s | %9d | %9d | %9d |\n", 716 queue_map[i].queue, q->queued, q->head, 717 q->tail); 718 } 719 720 return 0; 721 } 722 723 DEFINE_SHOW_ATTRIBUTE(mt7996_xmit_queues); 724 725 static int 726 mt7996_twt_stats(struct seq_file *s, void *data) 727 { 728 struct mt7996_dev *dev = dev_get_drvdata(s->private); 729 struct mt7996_twt_flow *iter; 730 731 rcu_read_lock(); 732 733 seq_puts(s, " wcid | id | flags | exp | mantissa"); 734 seq_puts(s, " | duration | tsf |\n"); 735 list_for_each_entry_rcu(iter, &dev->twt_list, list) 736 seq_printf(s, 737 "%9d | %8d | %5c%c%c%c | %8d | %8d | %8d | %14lld |\n", 738 iter->wcid, iter->id, 739 iter->sched ? 's' : 'u', 740 iter->protection ? 'p' : '-', 741 iter->trigger ? 't' : '-', 742 iter->flowtype ? '-' : 'a', 743 iter->exp, iter->mantissa, 744 iter->duration, iter->tsf); 745 746 rcu_read_unlock(); 747 748 return 0; 749 } 750 751 /* The index of RF registers use the generic regidx, combined with two parts: 752 * WF selection [31:24] and offset [23:0]. 753 */ 754 static int 755 mt7996_rf_regval_get(void *data, u64 *val) 756 { 757 struct mt7996_dev *dev = data; 758 u32 regval; 759 int ret; 760 761 ret = mt7996_mcu_rf_regval(dev, dev->mt76.debugfs_reg, ®val, false); 762 if (ret) 763 return ret; 764 765 *val = regval; 766 767 return 0; 768 } 769 770 static int 771 mt7996_rf_regval_set(void *data, u64 val) 772 { 773 struct mt7996_dev *dev = data; 774 u32 val32 = val; 775 776 return mt7996_mcu_rf_regval(dev, dev->mt76.debugfs_reg, &val32, true); 777 } 778 779 DEFINE_DEBUGFS_ATTRIBUTE(fops_rf_regval, mt7996_rf_regval_get, 780 mt7996_rf_regval_set, "0x%08llx\n"); 781 782 int mt7996_init_debugfs(struct mt7996_phy *phy) 783 { 784 struct mt7996_dev *dev = phy->dev; 785 struct dentry *dir; 786 787 dir = mt76_register_debugfs_fops(phy->mt76, NULL); 788 if (!dir) 789 return -ENOMEM; 790 debugfs_create_file("hw-queues", 0400, dir, phy, 791 &mt7996_hw_queues_fops); 792 debugfs_create_file("xmit-queues", 0400, dir, phy, 793 &mt7996_xmit_queues_fops); 794 debugfs_create_file("tx_stats", 0400, dir, phy, &mt7996_tx_stats_fops); 795 debugfs_create_file("sys_recovery", 0600, dir, phy, 796 &mt7996_sys_recovery_ops); 797 debugfs_create_file("fw_debug_wm", 0600, dir, dev, &fops_fw_debug_wm); 798 debugfs_create_file("fw_debug_wa", 0600, dir, dev, &fops_fw_debug_wa); 799 debugfs_create_file("fw_debug_bin", 0600, dir, dev, &fops_fw_debug_bin); 800 /* TODO: wm fw cpu utilization */ 801 debugfs_create_file("fw_util_wa", 0400, dir, dev, 802 &mt7996_fw_util_wa_fops); 803 debugfs_create_file("implicit_txbf", 0600, dir, dev, 804 &fops_implicit_txbf); 805 debugfs_create_devm_seqfile(dev->mt76.dev, "twt_stats", dir, 806 mt7996_twt_stats); 807 debugfs_create_file("rf_regval", 0600, dir, dev, &fops_rf_regval); 808 809 if (phy->mt76->cap.has_5ghz) { 810 debugfs_create_u32("dfs_hw_pattern", 0400, dir, 811 &dev->hw_pattern); 812 debugfs_create_file("radar_trigger", 0200, dir, dev, 813 &fops_radar_trigger); 814 debugfs_create_devm_seqfile(dev->mt76.dev, "rdd_monitor", dir, 815 mt7996_rdd_monitor); 816 } 817 818 if (phy == &dev->phy) 819 dev->debugfs_dir = dir; 820 821 return 0; 822 } 823 824 static void 825 mt7996_debugfs_write_fwlog(struct mt7996_dev *dev, const void *hdr, int hdrlen, 826 const void *data, int len) 827 { 828 static DEFINE_SPINLOCK(lock); 829 unsigned long flags; 830 void *dest; 831 832 spin_lock_irqsave(&lock, flags); 833 dest = relay_reserve(dev->relay_fwlog, hdrlen + len + 4); 834 if (dest) { 835 *(u32 *)dest = hdrlen + len; 836 dest += 4; 837 838 if (hdrlen) { 839 memcpy(dest, hdr, hdrlen); 840 dest += hdrlen; 841 } 842 843 memcpy(dest, data, len); 844 relay_flush(dev->relay_fwlog); 845 } 846 spin_unlock_irqrestore(&lock, flags); 847 } 848 849 void mt7996_debugfs_rx_fw_monitor(struct mt7996_dev *dev, const void *data, int len) 850 { 851 struct { 852 __le32 magic; 853 u8 version; 854 u8 _rsv; 855 __le16 serial_id; 856 __le32 timestamp; 857 __le16 msg_type; 858 __le16 len; 859 } hdr = { 860 .version = 0x1, 861 .magic = cpu_to_le32(FW_BIN_LOG_MAGIC), 862 .msg_type = cpu_to_le16(PKT_TYPE_RX_FW_MONITOR), 863 }; 864 865 if (!dev->relay_fwlog) 866 return; 867 868 hdr.serial_id = cpu_to_le16(dev->fw_debug_seq++); 869 hdr.timestamp = cpu_to_le32(mt76_rr(dev, MT_LPON_FRCR(0))); 870 hdr.len = *(__le16 *)data; 871 mt7996_debugfs_write_fwlog(dev, &hdr, sizeof(hdr), data, len); 872 } 873 874 bool mt7996_debugfs_rx_log(struct mt7996_dev *dev, const void *data, int len) 875 { 876 if (get_unaligned_le32(data) != FW_BIN_LOG_MAGIC) 877 return false; 878 879 if (dev->relay_fwlog) 880 mt7996_debugfs_write_fwlog(dev, NULL, 0, data, len); 881 882 return true; 883 } 884 885 #ifdef CONFIG_MAC80211_DEBUGFS 886 /** per-station debugfs **/ 887 888 static ssize_t mt7996_sta_fixed_rate_set(struct file *file, 889 const char __user *user_buf, 890 size_t count, loff_t *ppos) 891 { 892 #define SHORT_PREAMBLE 0 893 #define LONG_PREAMBLE 1 894 struct ieee80211_sta *sta = file->private_data; 895 struct mt7996_sta *msta = (struct mt7996_sta *)sta->drv_priv; 896 struct mt7996_dev *dev = msta->vif->phy->dev; 897 struct ra_rate phy = {}; 898 char buf[100]; 899 int ret; 900 u16 gi, ltf; 901 902 if (count >= sizeof(buf)) 903 return -EINVAL; 904 905 if (copy_from_user(buf, user_buf, count)) 906 return -EFAULT; 907 908 if (count && buf[count - 1] == '\n') 909 buf[count - 1] = '\0'; 910 else 911 buf[count] = '\0'; 912 913 /* mode - cck: 0, ofdm: 1, ht: 2, gf: 3, vht: 4, he_su: 8, he_er: 9 EHT: 15 914 * bw - bw20: 0, bw40: 1, bw80: 2, bw160: 3, BW320: 4 915 * nss - vht: 1~4, he: 1~4, eht: 1~4, others: ignore 916 * mcs - cck: 0~4, ofdm: 0~7, ht: 0~32, vht: 0~9, he_su: 0~11, he_er: 0~2, eht: 0~13 917 * gi - (ht/vht) lgi: 0, sgi: 1; (he) 0.8us: 0, 1.6us: 1, 3.2us: 2 918 * preamble - short: 1, long: 0 919 * ldpc - off: 0, on: 1 920 * stbc - off: 0, on: 1 921 * ltf - 1xltf: 0, 2xltf: 1, 4xltf: 2 922 */ 923 if (sscanf(buf, "%hhu %hhu %hhu %hhu %hu %hhu %hhu %hhu %hhu %hu", 924 &phy.mode, &phy.bw, &phy.mcs, &phy.nss, &gi, 925 &phy.preamble, &phy.stbc, &phy.ldpc, &phy.spe, <f) != 10) { 926 dev_warn(dev->mt76.dev, 927 "format: Mode BW MCS NSS GI Preamble STBC LDPC SPE ltf\n"); 928 goto out; 929 } 930 931 phy.wlan_idx = cpu_to_le16(msta->wcid.idx); 932 phy.gi = cpu_to_le16(gi); 933 phy.ltf = cpu_to_le16(ltf); 934 phy.ldpc = phy.ldpc ? 7 : 0; 935 phy.preamble = phy.preamble ? SHORT_PREAMBLE : LONG_PREAMBLE; 936 937 ret = mt7996_mcu_set_fixed_rate_ctrl(dev, &phy, 0); 938 if (ret) 939 return -EFAULT; 940 941 out: 942 return count; 943 } 944 945 static const struct file_operations fops_fixed_rate = { 946 .write = mt7996_sta_fixed_rate_set, 947 .open = simple_open, 948 .owner = THIS_MODULE, 949 .llseek = default_llseek, 950 }; 951 952 static int 953 mt7996_queues_show(struct seq_file *s, void *data) 954 { 955 struct ieee80211_sta *sta = s->private; 956 957 mt7996_sta_hw_queue_read(s, sta); 958 959 return 0; 960 } 961 962 DEFINE_SHOW_ATTRIBUTE(mt7996_queues); 963 964 void mt7996_sta_add_debugfs(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 965 struct ieee80211_sta *sta, struct dentry *dir) 966 { 967 debugfs_create_file("fixed_rate", 0600, dir, sta, &fops_fixed_rate); 968 debugfs_create_file("hw-queues", 0400, dir, sta, &mt7996_queues_fops); 969 } 970 971 #endif 972