12774f206SBjoern A. Zeeb /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
22774f206SBjoern A. Zeeb /* Copyright(c) 2018-2019 Realtek Corporation
32774f206SBjoern A. Zeeb */
42774f206SBjoern A. Zeeb
52774f206SBjoern A. Zeeb #ifndef __RTK_MAIN_H_
62774f206SBjoern A. Zeeb #define __RTK_MAIN_H_
72774f206SBjoern A. Zeeb
82774f206SBjoern A. Zeeb #include <net/mac80211.h>
92774f206SBjoern A. Zeeb #include <linux/vmalloc.h>
102774f206SBjoern A. Zeeb #include <linux/firmware.h>
112774f206SBjoern A. Zeeb #include <linux/average.h>
122774f206SBjoern A. Zeeb #include <linux/bitops.h>
132774f206SBjoern A. Zeeb #include <linux/bitfield.h>
142774f206SBjoern A. Zeeb #include <linux/iopoll.h>
152774f206SBjoern A. Zeeb #include <linux/interrupt.h>
162774f206SBjoern A. Zeeb #include <linux/workqueue.h>
172774f206SBjoern A. Zeeb #if defined(__FreeBSD__)
182774f206SBjoern A. Zeeb #include <linux/kernel.h>
192774f206SBjoern A. Zeeb #include <linux/delay.h>
202774f206SBjoern A. Zeeb #include <linux/etherdevice.h>
212774f206SBjoern A. Zeeb #include <linux/rcupdate.h>
222774f206SBjoern A. Zeeb #include <linux/lockdep.h>
232774f206SBjoern A. Zeeb #include <linux/seq_file.h>
242774f206SBjoern A. Zeeb #endif
252774f206SBjoern A. Zeeb
262774f206SBjoern A. Zeeb #include "util.h"
272774f206SBjoern A. Zeeb
282774f206SBjoern A. Zeeb #define RTW_MAX_MAC_ID_NUM 32
292774f206SBjoern A. Zeeb #define RTW_MAX_SEC_CAM_NUM 32
302774f206SBjoern A. Zeeb #define MAX_PG_CAM_BACKUP_NUM 8
312774f206SBjoern A. Zeeb
322774f206SBjoern A. Zeeb #define RTW_SCAN_MAX_SSIDS 4
332774f206SBjoern A. Zeeb
342774f206SBjoern A. Zeeb #define RTW_MAX_PATTERN_NUM 12
352774f206SBjoern A. Zeeb #define RTW_MAX_PATTERN_MASK_SIZE 16
362774f206SBjoern A. Zeeb #define RTW_MAX_PATTERN_SIZE 128
372774f206SBjoern A. Zeeb
382774f206SBjoern A. Zeeb #define RTW_WATCH_DOG_DELAY_TIME round_jiffies_relative(HZ * 2)
392774f206SBjoern A. Zeeb
402774f206SBjoern A. Zeeb #define RFREG_MASK 0xfffff
412774f206SBjoern A. Zeeb #define INV_RF_DATA 0xffffffff
422774f206SBjoern A. Zeeb #define TX_PAGE_SIZE_SHIFT 7
4390aac0d8SBjoern A. Zeeb #define TX_PAGE_SIZE (1 << TX_PAGE_SIZE_SHIFT)
442774f206SBjoern A. Zeeb
452774f206SBjoern A. Zeeb #define RTW_CHANNEL_WIDTH_MAX 3
462774f206SBjoern A. Zeeb #define RTW_RF_PATH_MAX 4
472774f206SBjoern A. Zeeb #define HW_FEATURE_LEN 13
482774f206SBjoern A. Zeeb
492774f206SBjoern A. Zeeb #define RTW_TP_SHIFT 18 /* bytes/2s --> Mbps */
502774f206SBjoern A. Zeeb
512774f206SBjoern A. Zeeb extern bool rtw_bf_support;
522774f206SBjoern A. Zeeb extern bool rtw_disable_lps_deep_mode;
532774f206SBjoern A. Zeeb extern unsigned int rtw_debug_mask;
542774f206SBjoern A. Zeeb extern bool rtw_edcca_enabled;
552774f206SBjoern A. Zeeb extern const struct ieee80211_ops rtw_ops;
562774f206SBjoern A. Zeeb
572774f206SBjoern A. Zeeb #define RTW_MAX_CHANNEL_NUM_2G 14
582774f206SBjoern A. Zeeb #define RTW_MAX_CHANNEL_NUM_5G 49
592774f206SBjoern A. Zeeb
602774f206SBjoern A. Zeeb struct rtw_dev;
612774f206SBjoern A. Zeeb
622774f206SBjoern A. Zeeb enum rtw_hci_type {
632774f206SBjoern A. Zeeb RTW_HCI_TYPE_PCIE,
642774f206SBjoern A. Zeeb RTW_HCI_TYPE_USB,
652774f206SBjoern A. Zeeb RTW_HCI_TYPE_SDIO,
662774f206SBjoern A. Zeeb
672774f206SBjoern A. Zeeb RTW_HCI_TYPE_UNDEFINE,
682774f206SBjoern A. Zeeb };
692774f206SBjoern A. Zeeb
702774f206SBjoern A. Zeeb struct rtw_hci {
712774f206SBjoern A. Zeeb struct rtw_hci_ops *ops;
722774f206SBjoern A. Zeeb enum rtw_hci_type type;
732774f206SBjoern A. Zeeb
742774f206SBjoern A. Zeeb u32 rpwm_addr;
752774f206SBjoern A. Zeeb u32 cpwm_addr;
762774f206SBjoern A. Zeeb
772774f206SBjoern A. Zeeb u8 bulkout_num;
782774f206SBjoern A. Zeeb };
792774f206SBjoern A. Zeeb
802774f206SBjoern A. Zeeb #define IS_CH_5G_BAND_1(channel) ((channel) >= 36 && (channel <= 48))
812774f206SBjoern A. Zeeb #define IS_CH_5G_BAND_2(channel) ((channel) >= 52 && (channel <= 64))
822774f206SBjoern A. Zeeb #define IS_CH_5G_BAND_3(channel) ((channel) >= 100 && (channel <= 144))
832774f206SBjoern A. Zeeb #define IS_CH_5G_BAND_4(channel) ((channel) >= 149 && (channel <= 177))
842774f206SBjoern A. Zeeb
852774f206SBjoern A. Zeeb #define IS_CH_5G_BAND_MID(channel) \
862774f206SBjoern A. Zeeb (IS_CH_5G_BAND_2(channel) || IS_CH_5G_BAND_3(channel))
872774f206SBjoern A. Zeeb
882774f206SBjoern A. Zeeb #define IS_CH_2G_BAND(channel) ((channel) <= 14)
892774f206SBjoern A. Zeeb #define IS_CH_5G_BAND(channel) \
902774f206SBjoern A. Zeeb (IS_CH_5G_BAND_1(channel) || IS_CH_5G_BAND_2(channel) || \
912774f206SBjoern A. Zeeb IS_CH_5G_BAND_3(channel) || IS_CH_5G_BAND_4(channel))
922774f206SBjoern A. Zeeb
932774f206SBjoern A. Zeeb enum rtw_supported_band {
942774f206SBjoern A. Zeeb RTW_BAND_2G = BIT(NL80211_BAND_2GHZ),
952774f206SBjoern A. Zeeb RTW_BAND_5G = BIT(NL80211_BAND_5GHZ),
962774f206SBjoern A. Zeeb RTW_BAND_60G = BIT(NL80211_BAND_60GHZ),
972774f206SBjoern A. Zeeb };
982774f206SBjoern A. Zeeb
992774f206SBjoern A. Zeeb /* now, support up to 80M bw */
1002774f206SBjoern A. Zeeb #define RTW_MAX_CHANNEL_WIDTH RTW_CHANNEL_WIDTH_80
1012774f206SBjoern A. Zeeb
1022774f206SBjoern A. Zeeb enum rtw_bandwidth {
1032774f206SBjoern A. Zeeb RTW_CHANNEL_WIDTH_20 = 0,
1042774f206SBjoern A. Zeeb RTW_CHANNEL_WIDTH_40 = 1,
1052774f206SBjoern A. Zeeb RTW_CHANNEL_WIDTH_80 = 2,
1062774f206SBjoern A. Zeeb RTW_CHANNEL_WIDTH_160 = 3,
1072774f206SBjoern A. Zeeb RTW_CHANNEL_WIDTH_80_80 = 4,
1082774f206SBjoern A. Zeeb RTW_CHANNEL_WIDTH_5 = 5,
1092774f206SBjoern A. Zeeb RTW_CHANNEL_WIDTH_10 = 6,
1102774f206SBjoern A. Zeeb };
1112774f206SBjoern A. Zeeb
1122774f206SBjoern A. Zeeb enum rtw_sc_offset {
1132774f206SBjoern A. Zeeb RTW_SC_DONT_CARE = 0,
1142774f206SBjoern A. Zeeb RTW_SC_20_UPPER = 1,
1152774f206SBjoern A. Zeeb RTW_SC_20_LOWER = 2,
1162774f206SBjoern A. Zeeb RTW_SC_20_UPMOST = 3,
1172774f206SBjoern A. Zeeb RTW_SC_20_LOWEST = 4,
1182774f206SBjoern A. Zeeb RTW_SC_40_UPPER = 9,
1192774f206SBjoern A. Zeeb RTW_SC_40_LOWER = 10,
1202774f206SBjoern A. Zeeb };
1212774f206SBjoern A. Zeeb
1222774f206SBjoern A. Zeeb enum rtw_net_type {
1232774f206SBjoern A. Zeeb RTW_NET_NO_LINK = 0,
1242774f206SBjoern A. Zeeb RTW_NET_AD_HOC = 1,
1252774f206SBjoern A. Zeeb RTW_NET_MGD_LINKED = 2,
1262774f206SBjoern A. Zeeb RTW_NET_AP_MODE = 3,
1272774f206SBjoern A. Zeeb };
1282774f206SBjoern A. Zeeb
1292774f206SBjoern A. Zeeb enum rtw_rf_type {
1302774f206SBjoern A. Zeeb RF_1T1R = 0,
1312774f206SBjoern A. Zeeb RF_1T2R = 1,
1322774f206SBjoern A. Zeeb RF_2T2R = 2,
1332774f206SBjoern A. Zeeb RF_2T3R = 3,
1342774f206SBjoern A. Zeeb RF_2T4R = 4,
1352774f206SBjoern A. Zeeb RF_3T3R = 5,
1362774f206SBjoern A. Zeeb RF_3T4R = 6,
1372774f206SBjoern A. Zeeb RF_4T4R = 7,
1382774f206SBjoern A. Zeeb RF_TYPE_MAX,
1392774f206SBjoern A. Zeeb };
1402774f206SBjoern A. Zeeb
1412774f206SBjoern A. Zeeb enum rtw_rf_path {
1422774f206SBjoern A. Zeeb RF_PATH_A = 0,
1432774f206SBjoern A. Zeeb RF_PATH_B = 1,
1442774f206SBjoern A. Zeeb RF_PATH_C = 2,
1452774f206SBjoern A. Zeeb RF_PATH_D = 3,
1462774f206SBjoern A. Zeeb };
1472774f206SBjoern A. Zeeb
1482774f206SBjoern A. Zeeb enum rtw_bb_path {
1492774f206SBjoern A. Zeeb BB_PATH_A = BIT(0),
1502774f206SBjoern A. Zeeb BB_PATH_B = BIT(1),
1512774f206SBjoern A. Zeeb BB_PATH_C = BIT(2),
1522774f206SBjoern A. Zeeb BB_PATH_D = BIT(3),
1532774f206SBjoern A. Zeeb
1542774f206SBjoern A. Zeeb BB_PATH_AB = (BB_PATH_A | BB_PATH_B),
1552774f206SBjoern A. Zeeb BB_PATH_AC = (BB_PATH_A | BB_PATH_C),
1562774f206SBjoern A. Zeeb BB_PATH_AD = (BB_PATH_A | BB_PATH_D),
1572774f206SBjoern A. Zeeb BB_PATH_BC = (BB_PATH_B | BB_PATH_C),
1582774f206SBjoern A. Zeeb BB_PATH_BD = (BB_PATH_B | BB_PATH_D),
1592774f206SBjoern A. Zeeb BB_PATH_CD = (BB_PATH_C | BB_PATH_D),
1602774f206SBjoern A. Zeeb
1612774f206SBjoern A. Zeeb BB_PATH_ABC = (BB_PATH_A | BB_PATH_B | BB_PATH_C),
1622774f206SBjoern A. Zeeb BB_PATH_ABD = (BB_PATH_A | BB_PATH_B | BB_PATH_D),
1632774f206SBjoern A. Zeeb BB_PATH_ACD = (BB_PATH_A | BB_PATH_C | BB_PATH_D),
1642774f206SBjoern A. Zeeb BB_PATH_BCD = (BB_PATH_B | BB_PATH_C | BB_PATH_D),
1652774f206SBjoern A. Zeeb
1662774f206SBjoern A. Zeeb BB_PATH_ABCD = (BB_PATH_A | BB_PATH_B | BB_PATH_C | BB_PATH_D),
1672774f206SBjoern A. Zeeb };
1682774f206SBjoern A. Zeeb
1692774f206SBjoern A. Zeeb enum rtw_rate_section {
1702774f206SBjoern A. Zeeb RTW_RATE_SECTION_CCK = 0,
1712774f206SBjoern A. Zeeb RTW_RATE_SECTION_OFDM,
1722774f206SBjoern A. Zeeb RTW_RATE_SECTION_HT_1S,
1732774f206SBjoern A. Zeeb RTW_RATE_SECTION_HT_2S,
1742774f206SBjoern A. Zeeb RTW_RATE_SECTION_VHT_1S,
1752774f206SBjoern A. Zeeb RTW_RATE_SECTION_VHT_2S,
1762774f206SBjoern A. Zeeb
1772774f206SBjoern A. Zeeb /* keep last */
1782774f206SBjoern A. Zeeb RTW_RATE_SECTION_MAX,
1792774f206SBjoern A. Zeeb };
1802774f206SBjoern A. Zeeb
1812774f206SBjoern A. Zeeb enum rtw_wireless_set {
1822774f206SBjoern A. Zeeb WIRELESS_CCK = 0x00000001,
1832774f206SBjoern A. Zeeb WIRELESS_OFDM = 0x00000002,
1842774f206SBjoern A. Zeeb WIRELESS_HT = 0x00000004,
1852774f206SBjoern A. Zeeb WIRELESS_VHT = 0x00000008,
1862774f206SBjoern A. Zeeb };
1872774f206SBjoern A. Zeeb
1882774f206SBjoern A. Zeeb #define HT_STBC_EN BIT(0)
1892774f206SBjoern A. Zeeb #define VHT_STBC_EN BIT(1)
1902774f206SBjoern A. Zeeb #define HT_LDPC_EN BIT(0)
1912774f206SBjoern A. Zeeb #define VHT_LDPC_EN BIT(1)
1922774f206SBjoern A. Zeeb
1932774f206SBjoern A. Zeeb enum rtw_chip_type {
1942774f206SBjoern A. Zeeb RTW_CHIP_TYPE_8822B,
1952774f206SBjoern A. Zeeb RTW_CHIP_TYPE_8822C,
1962774f206SBjoern A. Zeeb RTW_CHIP_TYPE_8723D,
1972774f206SBjoern A. Zeeb RTW_CHIP_TYPE_8821C,
1982774f206SBjoern A. Zeeb };
1992774f206SBjoern A. Zeeb
2002774f206SBjoern A. Zeeb enum rtw_tx_queue_type {
2012774f206SBjoern A. Zeeb /* the order of AC queues matters */
2022774f206SBjoern A. Zeeb RTW_TX_QUEUE_BK = 0x0,
2032774f206SBjoern A. Zeeb RTW_TX_QUEUE_BE = 0x1,
2042774f206SBjoern A. Zeeb RTW_TX_QUEUE_VI = 0x2,
2052774f206SBjoern A. Zeeb RTW_TX_QUEUE_VO = 0x3,
2062774f206SBjoern A. Zeeb
2072774f206SBjoern A. Zeeb RTW_TX_QUEUE_BCN = 0x4,
2082774f206SBjoern A. Zeeb RTW_TX_QUEUE_MGMT = 0x5,
2092774f206SBjoern A. Zeeb RTW_TX_QUEUE_HI0 = 0x6,
2102774f206SBjoern A. Zeeb RTW_TX_QUEUE_H2C = 0x7,
2112774f206SBjoern A. Zeeb /* keep it last */
2122774f206SBjoern A. Zeeb RTK_MAX_TX_QUEUE_NUM
2132774f206SBjoern A. Zeeb };
2142774f206SBjoern A. Zeeb
2152774f206SBjoern A. Zeeb enum rtw_rx_queue_type {
2162774f206SBjoern A. Zeeb RTW_RX_QUEUE_MPDU = 0x0,
2172774f206SBjoern A. Zeeb RTW_RX_QUEUE_C2H = 0x1,
2182774f206SBjoern A. Zeeb /* keep it last */
2192774f206SBjoern A. Zeeb RTK_MAX_RX_QUEUE_NUM
2202774f206SBjoern A. Zeeb };
2212774f206SBjoern A. Zeeb
2222774f206SBjoern A. Zeeb enum rtw_fw_type {
2232774f206SBjoern A. Zeeb RTW_NORMAL_FW = 0x0,
2242774f206SBjoern A. Zeeb RTW_WOWLAN_FW = 0x1,
2252774f206SBjoern A. Zeeb };
2262774f206SBjoern A. Zeeb
2272774f206SBjoern A. Zeeb enum rtw_rate_index {
2282774f206SBjoern A. Zeeb RTW_RATEID_BGN_40M_2SS = 0,
2292774f206SBjoern A. Zeeb RTW_RATEID_BGN_40M_1SS = 1,
2302774f206SBjoern A. Zeeb RTW_RATEID_BGN_20M_2SS = 2,
2312774f206SBjoern A. Zeeb RTW_RATEID_BGN_20M_1SS = 3,
2322774f206SBjoern A. Zeeb RTW_RATEID_GN_N2SS = 4,
2332774f206SBjoern A. Zeeb RTW_RATEID_GN_N1SS = 5,
2342774f206SBjoern A. Zeeb RTW_RATEID_BG = 6,
2352774f206SBjoern A. Zeeb RTW_RATEID_G = 7,
2362774f206SBjoern A. Zeeb RTW_RATEID_B_20M = 8,
2372774f206SBjoern A. Zeeb RTW_RATEID_ARFR0_AC_2SS = 9,
2382774f206SBjoern A. Zeeb RTW_RATEID_ARFR1_AC_1SS = 10,
2392774f206SBjoern A. Zeeb RTW_RATEID_ARFR2_AC_2G_1SS = 11,
2402774f206SBjoern A. Zeeb RTW_RATEID_ARFR3_AC_2G_2SS = 12,
2412774f206SBjoern A. Zeeb RTW_RATEID_ARFR4_AC_3SS = 13,
2422774f206SBjoern A. Zeeb RTW_RATEID_ARFR5_N_3SS = 14,
2432774f206SBjoern A. Zeeb RTW_RATEID_ARFR7_N_4SS = 15,
2442774f206SBjoern A. Zeeb RTW_RATEID_ARFR6_AC_4SS = 16
2452774f206SBjoern A. Zeeb };
2462774f206SBjoern A. Zeeb
2472774f206SBjoern A. Zeeb enum rtw_trx_desc_rate {
2482774f206SBjoern A. Zeeb DESC_RATE1M = 0x00,
2492774f206SBjoern A. Zeeb DESC_RATE2M = 0x01,
2502774f206SBjoern A. Zeeb DESC_RATE5_5M = 0x02,
2512774f206SBjoern A. Zeeb DESC_RATE11M = 0x03,
2522774f206SBjoern A. Zeeb
2532774f206SBjoern A. Zeeb DESC_RATE6M = 0x04,
2542774f206SBjoern A. Zeeb DESC_RATE9M = 0x05,
2552774f206SBjoern A. Zeeb DESC_RATE12M = 0x06,
2562774f206SBjoern A. Zeeb DESC_RATE18M = 0x07,
2572774f206SBjoern A. Zeeb DESC_RATE24M = 0x08,
2582774f206SBjoern A. Zeeb DESC_RATE36M = 0x09,
2592774f206SBjoern A. Zeeb DESC_RATE48M = 0x0a,
2602774f206SBjoern A. Zeeb DESC_RATE54M = 0x0b,
2612774f206SBjoern A. Zeeb
2622774f206SBjoern A. Zeeb DESC_RATEMCS0 = 0x0c,
2632774f206SBjoern A. Zeeb DESC_RATEMCS1 = 0x0d,
2642774f206SBjoern A. Zeeb DESC_RATEMCS2 = 0x0e,
2652774f206SBjoern A. Zeeb DESC_RATEMCS3 = 0x0f,
2662774f206SBjoern A. Zeeb DESC_RATEMCS4 = 0x10,
2672774f206SBjoern A. Zeeb DESC_RATEMCS5 = 0x11,
2682774f206SBjoern A. Zeeb DESC_RATEMCS6 = 0x12,
2692774f206SBjoern A. Zeeb DESC_RATEMCS7 = 0x13,
2702774f206SBjoern A. Zeeb DESC_RATEMCS8 = 0x14,
2712774f206SBjoern A. Zeeb DESC_RATEMCS9 = 0x15,
2722774f206SBjoern A. Zeeb DESC_RATEMCS10 = 0x16,
2732774f206SBjoern A. Zeeb DESC_RATEMCS11 = 0x17,
2742774f206SBjoern A. Zeeb DESC_RATEMCS12 = 0x18,
2752774f206SBjoern A. Zeeb DESC_RATEMCS13 = 0x19,
2762774f206SBjoern A. Zeeb DESC_RATEMCS14 = 0x1a,
2772774f206SBjoern A. Zeeb DESC_RATEMCS15 = 0x1b,
2782774f206SBjoern A. Zeeb DESC_RATEMCS16 = 0x1c,
2792774f206SBjoern A. Zeeb DESC_RATEMCS17 = 0x1d,
2802774f206SBjoern A. Zeeb DESC_RATEMCS18 = 0x1e,
2812774f206SBjoern A. Zeeb DESC_RATEMCS19 = 0x1f,
2822774f206SBjoern A. Zeeb DESC_RATEMCS20 = 0x20,
2832774f206SBjoern A. Zeeb DESC_RATEMCS21 = 0x21,
2842774f206SBjoern A. Zeeb DESC_RATEMCS22 = 0x22,
2852774f206SBjoern A. Zeeb DESC_RATEMCS23 = 0x23,
2862774f206SBjoern A. Zeeb DESC_RATEMCS24 = 0x24,
2872774f206SBjoern A. Zeeb DESC_RATEMCS25 = 0x25,
2882774f206SBjoern A. Zeeb DESC_RATEMCS26 = 0x26,
2892774f206SBjoern A. Zeeb DESC_RATEMCS27 = 0x27,
2902774f206SBjoern A. Zeeb DESC_RATEMCS28 = 0x28,
2912774f206SBjoern A. Zeeb DESC_RATEMCS29 = 0x29,
2922774f206SBjoern A. Zeeb DESC_RATEMCS30 = 0x2a,
2932774f206SBjoern A. Zeeb DESC_RATEMCS31 = 0x2b,
2942774f206SBjoern A. Zeeb
2952774f206SBjoern A. Zeeb DESC_RATEVHT1SS_MCS0 = 0x2c,
2962774f206SBjoern A. Zeeb DESC_RATEVHT1SS_MCS1 = 0x2d,
2972774f206SBjoern A. Zeeb DESC_RATEVHT1SS_MCS2 = 0x2e,
2982774f206SBjoern A. Zeeb DESC_RATEVHT1SS_MCS3 = 0x2f,
2992774f206SBjoern A. Zeeb DESC_RATEVHT1SS_MCS4 = 0x30,
3002774f206SBjoern A. Zeeb DESC_RATEVHT1SS_MCS5 = 0x31,
3012774f206SBjoern A. Zeeb DESC_RATEVHT1SS_MCS6 = 0x32,
3022774f206SBjoern A. Zeeb DESC_RATEVHT1SS_MCS7 = 0x33,
3032774f206SBjoern A. Zeeb DESC_RATEVHT1SS_MCS8 = 0x34,
3042774f206SBjoern A. Zeeb DESC_RATEVHT1SS_MCS9 = 0x35,
3052774f206SBjoern A. Zeeb
3062774f206SBjoern A. Zeeb DESC_RATEVHT2SS_MCS0 = 0x36,
3072774f206SBjoern A. Zeeb DESC_RATEVHT2SS_MCS1 = 0x37,
3082774f206SBjoern A. Zeeb DESC_RATEVHT2SS_MCS2 = 0x38,
3092774f206SBjoern A. Zeeb DESC_RATEVHT2SS_MCS3 = 0x39,
3102774f206SBjoern A. Zeeb DESC_RATEVHT2SS_MCS4 = 0x3a,
3112774f206SBjoern A. Zeeb DESC_RATEVHT2SS_MCS5 = 0x3b,
3122774f206SBjoern A. Zeeb DESC_RATEVHT2SS_MCS6 = 0x3c,
3132774f206SBjoern A. Zeeb DESC_RATEVHT2SS_MCS7 = 0x3d,
3142774f206SBjoern A. Zeeb DESC_RATEVHT2SS_MCS8 = 0x3e,
3152774f206SBjoern A. Zeeb DESC_RATEVHT2SS_MCS9 = 0x3f,
3162774f206SBjoern A. Zeeb
3172774f206SBjoern A. Zeeb DESC_RATEVHT3SS_MCS0 = 0x40,
3182774f206SBjoern A. Zeeb DESC_RATEVHT3SS_MCS1 = 0x41,
3192774f206SBjoern A. Zeeb DESC_RATEVHT3SS_MCS2 = 0x42,
3202774f206SBjoern A. Zeeb DESC_RATEVHT3SS_MCS3 = 0x43,
3212774f206SBjoern A. Zeeb DESC_RATEVHT3SS_MCS4 = 0x44,
3222774f206SBjoern A. Zeeb DESC_RATEVHT3SS_MCS5 = 0x45,
3232774f206SBjoern A. Zeeb DESC_RATEVHT3SS_MCS6 = 0x46,
3242774f206SBjoern A. Zeeb DESC_RATEVHT3SS_MCS7 = 0x47,
3252774f206SBjoern A. Zeeb DESC_RATEVHT3SS_MCS8 = 0x48,
3262774f206SBjoern A. Zeeb DESC_RATEVHT3SS_MCS9 = 0x49,
3272774f206SBjoern A. Zeeb
3282774f206SBjoern A. Zeeb DESC_RATEVHT4SS_MCS0 = 0x4a,
3292774f206SBjoern A. Zeeb DESC_RATEVHT4SS_MCS1 = 0x4b,
3302774f206SBjoern A. Zeeb DESC_RATEVHT4SS_MCS2 = 0x4c,
3312774f206SBjoern A. Zeeb DESC_RATEVHT4SS_MCS3 = 0x4d,
3322774f206SBjoern A. Zeeb DESC_RATEVHT4SS_MCS4 = 0x4e,
3332774f206SBjoern A. Zeeb DESC_RATEVHT4SS_MCS5 = 0x4f,
3342774f206SBjoern A. Zeeb DESC_RATEVHT4SS_MCS6 = 0x50,
3352774f206SBjoern A. Zeeb DESC_RATEVHT4SS_MCS7 = 0x51,
3362774f206SBjoern A. Zeeb DESC_RATEVHT4SS_MCS8 = 0x52,
3372774f206SBjoern A. Zeeb DESC_RATEVHT4SS_MCS9 = 0x53,
3382774f206SBjoern A. Zeeb
3392774f206SBjoern A. Zeeb DESC_RATE_MAX,
3402774f206SBjoern A. Zeeb };
3412774f206SBjoern A. Zeeb
3422774f206SBjoern A. Zeeb enum rtw_regulatory_domains {
3432774f206SBjoern A. Zeeb RTW_REGD_FCC = 0,
3442774f206SBjoern A. Zeeb RTW_REGD_MKK = 1,
3452774f206SBjoern A. Zeeb RTW_REGD_ETSI = 2,
3462774f206SBjoern A. Zeeb RTW_REGD_IC = 3,
3472774f206SBjoern A. Zeeb RTW_REGD_KCC = 4,
3482774f206SBjoern A. Zeeb RTW_REGD_ACMA = 5,
3492774f206SBjoern A. Zeeb RTW_REGD_CHILE = 6,
3502774f206SBjoern A. Zeeb RTW_REGD_UKRAINE = 7,
3512774f206SBjoern A. Zeeb RTW_REGD_MEXICO = 8,
3522774f206SBjoern A. Zeeb RTW_REGD_CN = 9,
3532774f206SBjoern A. Zeeb RTW_REGD_WW,
3542774f206SBjoern A. Zeeb
3552774f206SBjoern A. Zeeb RTW_REGD_MAX
3562774f206SBjoern A. Zeeb };
3572774f206SBjoern A. Zeeb
3582774f206SBjoern A. Zeeb enum rtw_txq_flags {
3592774f206SBjoern A. Zeeb RTW_TXQ_AMPDU,
3602774f206SBjoern A. Zeeb RTW_TXQ_BLOCK_BA,
3612774f206SBjoern A. Zeeb };
3622774f206SBjoern A. Zeeb
3632774f206SBjoern A. Zeeb enum rtw_flags {
3642774f206SBjoern A. Zeeb RTW_FLAG_RUNNING,
3652774f206SBjoern A. Zeeb RTW_FLAG_FW_RUNNING,
3662774f206SBjoern A. Zeeb RTW_FLAG_SCANNING,
36790aac0d8SBjoern A. Zeeb RTW_FLAG_POWERON,
3682774f206SBjoern A. Zeeb RTW_FLAG_LEISURE_PS,
3692774f206SBjoern A. Zeeb RTW_FLAG_LEISURE_PS_DEEP,
3702774f206SBjoern A. Zeeb RTW_FLAG_DIG_DISABLE,
3712774f206SBjoern A. Zeeb RTW_FLAG_BUSY_TRAFFIC,
3722774f206SBjoern A. Zeeb RTW_FLAG_WOWLAN,
3732774f206SBjoern A. Zeeb RTW_FLAG_RESTARTING,
3742774f206SBjoern A. Zeeb RTW_FLAG_RESTART_TRIGGERING,
3752774f206SBjoern A. Zeeb RTW_FLAG_FORCE_LOWEST_RATE,
3762774f206SBjoern A. Zeeb
3772774f206SBjoern A. Zeeb NUM_OF_RTW_FLAGS,
3782774f206SBjoern A. Zeeb };
3792774f206SBjoern A. Zeeb
3802774f206SBjoern A. Zeeb enum rtw_evm {
3812774f206SBjoern A. Zeeb RTW_EVM_OFDM = 0,
3822774f206SBjoern A. Zeeb RTW_EVM_1SS,
3832774f206SBjoern A. Zeeb RTW_EVM_2SS_A,
3842774f206SBjoern A. Zeeb RTW_EVM_2SS_B,
3852774f206SBjoern A. Zeeb /* keep it last */
3862774f206SBjoern A. Zeeb RTW_EVM_NUM
3872774f206SBjoern A. Zeeb };
3882774f206SBjoern A. Zeeb
3892774f206SBjoern A. Zeeb enum rtw_snr {
3902774f206SBjoern A. Zeeb RTW_SNR_OFDM_A = 0,
3912774f206SBjoern A. Zeeb RTW_SNR_OFDM_B,
3922774f206SBjoern A. Zeeb RTW_SNR_OFDM_C,
3932774f206SBjoern A. Zeeb RTW_SNR_OFDM_D,
3942774f206SBjoern A. Zeeb RTW_SNR_1SS_A,
3952774f206SBjoern A. Zeeb RTW_SNR_1SS_B,
3962774f206SBjoern A. Zeeb RTW_SNR_1SS_C,
3972774f206SBjoern A. Zeeb RTW_SNR_1SS_D,
3982774f206SBjoern A. Zeeb RTW_SNR_2SS_A,
3992774f206SBjoern A. Zeeb RTW_SNR_2SS_B,
4002774f206SBjoern A. Zeeb RTW_SNR_2SS_C,
4012774f206SBjoern A. Zeeb RTW_SNR_2SS_D,
4022774f206SBjoern A. Zeeb /* keep it last */
4032774f206SBjoern A. Zeeb RTW_SNR_NUM
4042774f206SBjoern A. Zeeb };
4052774f206SBjoern A. Zeeb
40690aac0d8SBjoern A. Zeeb enum rtw_port {
40790aac0d8SBjoern A. Zeeb RTW_PORT_0 = 0,
40890aac0d8SBjoern A. Zeeb RTW_PORT_1 = 1,
40990aac0d8SBjoern A. Zeeb RTW_PORT_2 = 2,
41090aac0d8SBjoern A. Zeeb RTW_PORT_3 = 3,
41190aac0d8SBjoern A. Zeeb RTW_PORT_4 = 4,
41290aac0d8SBjoern A. Zeeb RTW_PORT_NUM
41390aac0d8SBjoern A. Zeeb };
41490aac0d8SBjoern A. Zeeb
4152774f206SBjoern A. Zeeb enum rtw_wow_flags {
4162774f206SBjoern A. Zeeb RTW_WOW_FLAG_EN_MAGIC_PKT,
4172774f206SBjoern A. Zeeb RTW_WOW_FLAG_EN_REKEY_PKT,
4182774f206SBjoern A. Zeeb RTW_WOW_FLAG_EN_DISCONNECT,
4192774f206SBjoern A. Zeeb
4202774f206SBjoern A. Zeeb /* keep it last */
4212774f206SBjoern A. Zeeb RTW_WOW_FLAG_MAX,
4222774f206SBjoern A. Zeeb };
4232774f206SBjoern A. Zeeb
4242774f206SBjoern A. Zeeb /* the power index is represented by differences, which cck-1s & ht40-1s are
4252774f206SBjoern A. Zeeb * the base values, so for 1s's differences, there are only ht20 & ofdm
4262774f206SBjoern A. Zeeb */
4272774f206SBjoern A. Zeeb struct rtw_2g_1s_pwr_idx_diff {
4282774f206SBjoern A. Zeeb #ifdef __LITTLE_ENDIAN
4292774f206SBjoern A. Zeeb s8 ofdm:4;
4302774f206SBjoern A. Zeeb s8 bw20:4;
4312774f206SBjoern A. Zeeb #else
4322774f206SBjoern A. Zeeb s8 bw20:4;
4332774f206SBjoern A. Zeeb s8 ofdm:4;
4342774f206SBjoern A. Zeeb #endif
4352774f206SBjoern A. Zeeb } __packed;
4362774f206SBjoern A. Zeeb
4372774f206SBjoern A. Zeeb struct rtw_2g_ns_pwr_idx_diff {
4382774f206SBjoern A. Zeeb #ifdef __LITTLE_ENDIAN
4392774f206SBjoern A. Zeeb s8 bw20:4;
4402774f206SBjoern A. Zeeb s8 bw40:4;
4412774f206SBjoern A. Zeeb s8 cck:4;
4422774f206SBjoern A. Zeeb s8 ofdm:4;
4432774f206SBjoern A. Zeeb #else
4442774f206SBjoern A. Zeeb s8 ofdm:4;
4452774f206SBjoern A. Zeeb s8 cck:4;
4462774f206SBjoern A. Zeeb s8 bw40:4;
4472774f206SBjoern A. Zeeb s8 bw20:4;
4482774f206SBjoern A. Zeeb #endif
4492774f206SBjoern A. Zeeb } __packed;
4502774f206SBjoern A. Zeeb
4512774f206SBjoern A. Zeeb struct rtw_2g_txpwr_idx {
4522774f206SBjoern A. Zeeb u8 cck_base[6];
4532774f206SBjoern A. Zeeb u8 bw40_base[5];
4542774f206SBjoern A. Zeeb struct rtw_2g_1s_pwr_idx_diff ht_1s_diff;
4552774f206SBjoern A. Zeeb struct rtw_2g_ns_pwr_idx_diff ht_2s_diff;
4562774f206SBjoern A. Zeeb struct rtw_2g_ns_pwr_idx_diff ht_3s_diff;
4572774f206SBjoern A. Zeeb struct rtw_2g_ns_pwr_idx_diff ht_4s_diff;
4582774f206SBjoern A. Zeeb };
4592774f206SBjoern A. Zeeb
4602774f206SBjoern A. Zeeb struct rtw_5g_ht_1s_pwr_idx_diff {
4612774f206SBjoern A. Zeeb #ifdef __LITTLE_ENDIAN
4622774f206SBjoern A. Zeeb s8 ofdm:4;
4632774f206SBjoern A. Zeeb s8 bw20:4;
4642774f206SBjoern A. Zeeb #else
4652774f206SBjoern A. Zeeb s8 bw20:4;
4662774f206SBjoern A. Zeeb s8 ofdm:4;
4672774f206SBjoern A. Zeeb #endif
4682774f206SBjoern A. Zeeb } __packed;
4692774f206SBjoern A. Zeeb
4702774f206SBjoern A. Zeeb struct rtw_5g_ht_ns_pwr_idx_diff {
4712774f206SBjoern A. Zeeb #ifdef __LITTLE_ENDIAN
4722774f206SBjoern A. Zeeb s8 bw20:4;
4732774f206SBjoern A. Zeeb s8 bw40:4;
4742774f206SBjoern A. Zeeb #else
4752774f206SBjoern A. Zeeb s8 bw40:4;
4762774f206SBjoern A. Zeeb s8 bw20:4;
4772774f206SBjoern A. Zeeb #endif
4782774f206SBjoern A. Zeeb } __packed;
4792774f206SBjoern A. Zeeb
4802774f206SBjoern A. Zeeb struct rtw_5g_ofdm_ns_pwr_idx_diff {
4812774f206SBjoern A. Zeeb #ifdef __LITTLE_ENDIAN
4822774f206SBjoern A. Zeeb s8 ofdm_3s:4;
4832774f206SBjoern A. Zeeb s8 ofdm_2s:4;
4842774f206SBjoern A. Zeeb s8 ofdm_4s:4;
4852774f206SBjoern A. Zeeb s8 res:4;
4862774f206SBjoern A. Zeeb #else
4872774f206SBjoern A. Zeeb s8 res:4;
4882774f206SBjoern A. Zeeb s8 ofdm_4s:4;
4892774f206SBjoern A. Zeeb s8 ofdm_2s:4;
4902774f206SBjoern A. Zeeb s8 ofdm_3s:4;
4912774f206SBjoern A. Zeeb #endif
4922774f206SBjoern A. Zeeb } __packed;
4932774f206SBjoern A. Zeeb
4942774f206SBjoern A. Zeeb struct rtw_5g_vht_ns_pwr_idx_diff {
4952774f206SBjoern A. Zeeb #ifdef __LITTLE_ENDIAN
4962774f206SBjoern A. Zeeb s8 bw160:4;
4972774f206SBjoern A. Zeeb s8 bw80:4;
4982774f206SBjoern A. Zeeb #else
4992774f206SBjoern A. Zeeb s8 bw80:4;
5002774f206SBjoern A. Zeeb s8 bw160:4;
5012774f206SBjoern A. Zeeb #endif
5022774f206SBjoern A. Zeeb } __packed;
5032774f206SBjoern A. Zeeb
5042774f206SBjoern A. Zeeb struct rtw_5g_txpwr_idx {
5052774f206SBjoern A. Zeeb u8 bw40_base[14];
5062774f206SBjoern A. Zeeb struct rtw_5g_ht_1s_pwr_idx_diff ht_1s_diff;
5072774f206SBjoern A. Zeeb struct rtw_5g_ht_ns_pwr_idx_diff ht_2s_diff;
5082774f206SBjoern A. Zeeb struct rtw_5g_ht_ns_pwr_idx_diff ht_3s_diff;
5092774f206SBjoern A. Zeeb struct rtw_5g_ht_ns_pwr_idx_diff ht_4s_diff;
5102774f206SBjoern A. Zeeb struct rtw_5g_ofdm_ns_pwr_idx_diff ofdm_diff;
5112774f206SBjoern A. Zeeb struct rtw_5g_vht_ns_pwr_idx_diff vht_1s_diff;
5122774f206SBjoern A. Zeeb struct rtw_5g_vht_ns_pwr_idx_diff vht_2s_diff;
5132774f206SBjoern A. Zeeb struct rtw_5g_vht_ns_pwr_idx_diff vht_3s_diff;
5142774f206SBjoern A. Zeeb struct rtw_5g_vht_ns_pwr_idx_diff vht_4s_diff;
5152774f206SBjoern A. Zeeb };
5162774f206SBjoern A. Zeeb
5172774f206SBjoern A. Zeeb struct rtw_txpwr_idx {
5182774f206SBjoern A. Zeeb struct rtw_2g_txpwr_idx pwr_idx_2g;
5192774f206SBjoern A. Zeeb struct rtw_5g_txpwr_idx pwr_idx_5g;
5202774f206SBjoern A. Zeeb };
5212774f206SBjoern A. Zeeb
5222774f206SBjoern A. Zeeb struct rtw_channel_params {
5232774f206SBjoern A. Zeeb u8 center_chan;
52490aac0d8SBjoern A. Zeeb u8 primary_chan;
5252774f206SBjoern A. Zeeb u8 bandwidth;
5262774f206SBjoern A. Zeeb };
5272774f206SBjoern A. Zeeb
5282774f206SBjoern A. Zeeb struct rtw_hw_reg {
5292774f206SBjoern A. Zeeb u32 addr;
5302774f206SBjoern A. Zeeb u32 mask;
5312774f206SBjoern A. Zeeb };
5322774f206SBjoern A. Zeeb
5332774f206SBjoern A. Zeeb struct rtw_ltecoex_addr {
5342774f206SBjoern A. Zeeb u32 ctrl;
5352774f206SBjoern A. Zeeb u32 wdata;
5362774f206SBjoern A. Zeeb u32 rdata;
5372774f206SBjoern A. Zeeb };
5382774f206SBjoern A. Zeeb
5392774f206SBjoern A. Zeeb struct rtw_reg_domain {
5402774f206SBjoern A. Zeeb u32 addr;
5412774f206SBjoern A. Zeeb u32 mask;
5422774f206SBjoern A. Zeeb #define RTW_REG_DOMAIN_MAC32 0
5432774f206SBjoern A. Zeeb #define RTW_REG_DOMAIN_MAC16 1
5442774f206SBjoern A. Zeeb #define RTW_REG_DOMAIN_MAC8 2
5452774f206SBjoern A. Zeeb #define RTW_REG_DOMAIN_RF_A 3
5462774f206SBjoern A. Zeeb #define RTW_REG_DOMAIN_RF_B 4
5472774f206SBjoern A. Zeeb #define RTW_REG_DOMAIN_NL 0xFF
5482774f206SBjoern A. Zeeb u8 domain;
5492774f206SBjoern A. Zeeb };
5502774f206SBjoern A. Zeeb
5512774f206SBjoern A. Zeeb struct rtw_rf_sipi_addr {
5522774f206SBjoern A. Zeeb u32 hssi_1;
5532774f206SBjoern A. Zeeb u32 hssi_2;
5542774f206SBjoern A. Zeeb u32 lssi_read;
5552774f206SBjoern A. Zeeb u32 lssi_read_pi;
5562774f206SBjoern A. Zeeb };
5572774f206SBjoern A. Zeeb
5582774f206SBjoern A. Zeeb struct rtw_hw_reg_offset {
5592774f206SBjoern A. Zeeb struct rtw_hw_reg hw_reg;
5602774f206SBjoern A. Zeeb u8 offset;
5612774f206SBjoern A. Zeeb };
5622774f206SBjoern A. Zeeb
5632774f206SBjoern A. Zeeb struct rtw_backup_info {
5642774f206SBjoern A. Zeeb u8 len;
5652774f206SBjoern A. Zeeb u32 reg;
5662774f206SBjoern A. Zeeb u32 val;
5672774f206SBjoern A. Zeeb };
5682774f206SBjoern A. Zeeb
5692774f206SBjoern A. Zeeb enum rtw_vif_port_set {
5702774f206SBjoern A. Zeeb PORT_SET_MAC_ADDR = BIT(0),
5712774f206SBjoern A. Zeeb PORT_SET_BSSID = BIT(1),
5722774f206SBjoern A. Zeeb PORT_SET_NET_TYPE = BIT(2),
5732774f206SBjoern A. Zeeb PORT_SET_AID = BIT(3),
5742774f206SBjoern A. Zeeb PORT_SET_BCN_CTRL = BIT(4),
5752774f206SBjoern A. Zeeb };
5762774f206SBjoern A. Zeeb
5772774f206SBjoern A. Zeeb struct rtw_vif_port {
5782774f206SBjoern A. Zeeb struct rtw_hw_reg mac_addr;
5792774f206SBjoern A. Zeeb struct rtw_hw_reg bssid;
5802774f206SBjoern A. Zeeb struct rtw_hw_reg net_type;
5812774f206SBjoern A. Zeeb struct rtw_hw_reg aid;
5822774f206SBjoern A. Zeeb struct rtw_hw_reg bcn_ctrl;
5832774f206SBjoern A. Zeeb };
5842774f206SBjoern A. Zeeb
5852774f206SBjoern A. Zeeb struct rtw_tx_pkt_info {
5862774f206SBjoern A. Zeeb u32 tx_pkt_size;
5872774f206SBjoern A. Zeeb u8 offset;
5882774f206SBjoern A. Zeeb u8 pkt_offset;
5899c951734SBjoern A. Zeeb u8 tim_offset;
5902774f206SBjoern A. Zeeb u8 mac_id;
5912774f206SBjoern A. Zeeb u8 rate_id;
5922774f206SBjoern A. Zeeb u8 rate;
5932774f206SBjoern A. Zeeb u8 qsel;
5942774f206SBjoern A. Zeeb u8 bw;
5952774f206SBjoern A. Zeeb u8 sec_type;
5962774f206SBjoern A. Zeeb u8 sn;
5972774f206SBjoern A. Zeeb bool ampdu_en;
5982774f206SBjoern A. Zeeb u8 ampdu_factor;
5992774f206SBjoern A. Zeeb u8 ampdu_density;
6002774f206SBjoern A. Zeeb u16 seq;
6012774f206SBjoern A. Zeeb bool stbc;
6022774f206SBjoern A. Zeeb bool ldpc;
6032774f206SBjoern A. Zeeb bool dis_rate_fallback;
6042774f206SBjoern A. Zeeb bool bmc;
6052774f206SBjoern A. Zeeb bool use_rate;
6062774f206SBjoern A. Zeeb bool ls;
6072774f206SBjoern A. Zeeb bool fs;
6082774f206SBjoern A. Zeeb bool short_gi;
6092774f206SBjoern A. Zeeb bool report;
6102774f206SBjoern A. Zeeb bool rts;
6112774f206SBjoern A. Zeeb bool dis_qselseq;
6122774f206SBjoern A. Zeeb bool en_hwseq;
6132774f206SBjoern A. Zeeb u8 hw_ssn_sel;
6142774f206SBjoern A. Zeeb bool nav_use_hdr;
6152774f206SBjoern A. Zeeb bool bt_null;
6162774f206SBjoern A. Zeeb };
6172774f206SBjoern A. Zeeb
6182774f206SBjoern A. Zeeb struct rtw_rx_pkt_stat {
6192774f206SBjoern A. Zeeb bool phy_status;
6202774f206SBjoern A. Zeeb bool icv_err;
6212774f206SBjoern A. Zeeb bool crc_err;
6222774f206SBjoern A. Zeeb bool decrypted;
6232774f206SBjoern A. Zeeb bool is_c2h;
6242774f206SBjoern A. Zeeb
6252774f206SBjoern A. Zeeb s32 signal_power;
6262774f206SBjoern A. Zeeb u16 pkt_len;
6272774f206SBjoern A. Zeeb u8 bw;
6282774f206SBjoern A. Zeeb u8 drv_info_sz;
6292774f206SBjoern A. Zeeb u8 shift;
6302774f206SBjoern A. Zeeb u8 rate;
6312774f206SBjoern A. Zeeb u8 mac_id;
6322774f206SBjoern A. Zeeb u8 cam_id;
6332774f206SBjoern A. Zeeb u8 ppdu_cnt;
6342774f206SBjoern A. Zeeb u32 tsf_low;
6352774f206SBjoern A. Zeeb s8 rx_power[RTW_RF_PATH_MAX];
6362774f206SBjoern A. Zeeb u8 rssi;
6372774f206SBjoern A. Zeeb u8 rxsc;
6382774f206SBjoern A. Zeeb s8 rx_snr[RTW_RF_PATH_MAX];
6392774f206SBjoern A. Zeeb u8 rx_evm[RTW_RF_PATH_MAX];
6402774f206SBjoern A. Zeeb s8 cfo_tail[RTW_RF_PATH_MAX];
6412774f206SBjoern A. Zeeb u16 freq;
6422774f206SBjoern A. Zeeb u8 band;
6432774f206SBjoern A. Zeeb
6442774f206SBjoern A. Zeeb struct rtw_sta_info *si;
6452774f206SBjoern A. Zeeb struct ieee80211_vif *vif;
6462774f206SBjoern A. Zeeb struct ieee80211_hdr *hdr;
6472774f206SBjoern A. Zeeb };
6482774f206SBjoern A. Zeeb
6492774f206SBjoern A. Zeeb DECLARE_EWMA(tp, 10, 2);
6502774f206SBjoern A. Zeeb
6512774f206SBjoern A. Zeeb struct rtw_traffic_stats {
6522774f206SBjoern A. Zeeb /* units in bytes */
6532774f206SBjoern A. Zeeb u64 tx_unicast;
6542774f206SBjoern A. Zeeb u64 rx_unicast;
6552774f206SBjoern A. Zeeb
6562774f206SBjoern A. Zeeb /* count for packets */
6572774f206SBjoern A. Zeeb u64 tx_cnt;
6582774f206SBjoern A. Zeeb u64 rx_cnt;
6592774f206SBjoern A. Zeeb
6602774f206SBjoern A. Zeeb /* units in Mbps */
6612774f206SBjoern A. Zeeb u32 tx_throughput;
6622774f206SBjoern A. Zeeb u32 rx_throughput;
6632774f206SBjoern A. Zeeb struct ewma_tp tx_ewma_tp;
6642774f206SBjoern A. Zeeb struct ewma_tp rx_ewma_tp;
6652774f206SBjoern A. Zeeb };
6662774f206SBjoern A. Zeeb
6672774f206SBjoern A. Zeeb enum rtw_lps_mode {
6682774f206SBjoern A. Zeeb RTW_MODE_ACTIVE = 0,
6692774f206SBjoern A. Zeeb RTW_MODE_LPS = 1,
6702774f206SBjoern A. Zeeb RTW_MODE_WMM_PS = 2,
6712774f206SBjoern A. Zeeb };
6722774f206SBjoern A. Zeeb
6732774f206SBjoern A. Zeeb enum rtw_lps_deep_mode {
6742774f206SBjoern A. Zeeb LPS_DEEP_MODE_NONE = 0,
6752774f206SBjoern A. Zeeb LPS_DEEP_MODE_LCLK = 1,
6762774f206SBjoern A. Zeeb LPS_DEEP_MODE_PG = 2,
6772774f206SBjoern A. Zeeb };
6782774f206SBjoern A. Zeeb
6792774f206SBjoern A. Zeeb enum rtw_pwr_state {
6802774f206SBjoern A. Zeeb RTW_RF_OFF = 0x0,
6812774f206SBjoern A. Zeeb RTW_RF_ON = 0x4,
6822774f206SBjoern A. Zeeb RTW_ALL_ON = 0xc,
6832774f206SBjoern A. Zeeb };
6842774f206SBjoern A. Zeeb
6852774f206SBjoern A. Zeeb struct rtw_lps_conf {
6862774f206SBjoern A. Zeeb enum rtw_lps_mode mode;
6872774f206SBjoern A. Zeeb enum rtw_lps_deep_mode deep_mode;
6882774f206SBjoern A. Zeeb enum rtw_lps_deep_mode wow_deep_mode;
6892774f206SBjoern A. Zeeb enum rtw_pwr_state state;
6902774f206SBjoern A. Zeeb u8 awake_interval;
6912774f206SBjoern A. Zeeb u8 rlbm;
6922774f206SBjoern A. Zeeb u8 smart_ps;
6932774f206SBjoern A. Zeeb u8 port_id;
6942774f206SBjoern A. Zeeb bool sec_cam_backup;
6952774f206SBjoern A. Zeeb bool pattern_cam_backup;
6962774f206SBjoern A. Zeeb };
6972774f206SBjoern A. Zeeb
6982774f206SBjoern A. Zeeb enum rtw_hw_key_type {
6992774f206SBjoern A. Zeeb RTW_CAM_NONE = 0,
7002774f206SBjoern A. Zeeb RTW_CAM_WEP40 = 1,
7012774f206SBjoern A. Zeeb RTW_CAM_TKIP = 2,
7022774f206SBjoern A. Zeeb RTW_CAM_AES = 4,
7032774f206SBjoern A. Zeeb RTW_CAM_WEP104 = 5,
7042774f206SBjoern A. Zeeb };
7052774f206SBjoern A. Zeeb
7062774f206SBjoern A. Zeeb struct rtw_cam_entry {
7072774f206SBjoern A. Zeeb bool valid;
7082774f206SBjoern A. Zeeb bool group;
7092774f206SBjoern A. Zeeb u8 addr[ETH_ALEN];
7102774f206SBjoern A. Zeeb u8 hw_key_type;
7112774f206SBjoern A. Zeeb struct ieee80211_key_conf *key;
7122774f206SBjoern A. Zeeb };
7132774f206SBjoern A. Zeeb
7142774f206SBjoern A. Zeeb struct rtw_sec_desc {
7152774f206SBjoern A. Zeeb /* search strategy */
7162774f206SBjoern A. Zeeb bool default_key_search;
7172774f206SBjoern A. Zeeb
7182774f206SBjoern A. Zeeb u32 total_cam_num;
7192774f206SBjoern A. Zeeb struct rtw_cam_entry cam_table[RTW_MAX_SEC_CAM_NUM];
7202774f206SBjoern A. Zeeb DECLARE_BITMAP(cam_map, RTW_MAX_SEC_CAM_NUM);
7212774f206SBjoern A. Zeeb };
7222774f206SBjoern A. Zeeb
7232774f206SBjoern A. Zeeb struct rtw_tx_report {
7242774f206SBjoern A. Zeeb /* protect the tx report queue */
7252774f206SBjoern A. Zeeb spinlock_t q_lock;
7262774f206SBjoern A. Zeeb struct sk_buff_head queue;
7272774f206SBjoern A. Zeeb atomic_t sn;
7282774f206SBjoern A. Zeeb struct timer_list purge_timer;
7292774f206SBjoern A. Zeeb };
7302774f206SBjoern A. Zeeb
7312774f206SBjoern A. Zeeb struct rtw_ra_report {
7322774f206SBjoern A. Zeeb struct rate_info txrate;
7332774f206SBjoern A. Zeeb u32 bit_rate;
7342774f206SBjoern A. Zeeb u8 desc_rate;
7352774f206SBjoern A. Zeeb };
7362774f206SBjoern A. Zeeb
7372774f206SBjoern A. Zeeb struct rtw_txq {
7382774f206SBjoern A. Zeeb struct list_head list;
7392774f206SBjoern A. Zeeb unsigned long flags;
7402774f206SBjoern A. Zeeb };
7412774f206SBjoern A. Zeeb
7422774f206SBjoern A. Zeeb #define RTW_BC_MC_MACID 1
7432774f206SBjoern A. Zeeb DECLARE_EWMA(rssi, 10, 16);
7442774f206SBjoern A. Zeeb
7452774f206SBjoern A. Zeeb struct rtw_sta_info {
74690aac0d8SBjoern A. Zeeb struct rtw_dev *rtwdev;
7472774f206SBjoern A. Zeeb struct ieee80211_sta *sta;
7482774f206SBjoern A. Zeeb struct ieee80211_vif *vif;
7492774f206SBjoern A. Zeeb
7502774f206SBjoern A. Zeeb struct ewma_rssi avg_rssi;
7512774f206SBjoern A. Zeeb u8 rssi_level;
7522774f206SBjoern A. Zeeb
7532774f206SBjoern A. Zeeb u8 mac_id;
7542774f206SBjoern A. Zeeb u8 rate_id;
7552774f206SBjoern A. Zeeb enum rtw_bandwidth bw_mode;
7562774f206SBjoern A. Zeeb enum rtw_rf_type rf_type;
7572774f206SBjoern A. Zeeb u8 stbc_en:2;
7582774f206SBjoern A. Zeeb u8 ldpc_en:2;
7592774f206SBjoern A. Zeeb bool sgi_enable;
7602774f206SBjoern A. Zeeb bool vht_enable;
7612774f206SBjoern A. Zeeb u8 init_ra_lv;
7622774f206SBjoern A. Zeeb u64 ra_mask;
7632774f206SBjoern A. Zeeb
7642774f206SBjoern A. Zeeb DECLARE_BITMAP(tid_ba, IEEE80211_NUM_TIDS);
7652774f206SBjoern A. Zeeb
7662774f206SBjoern A. Zeeb struct rtw_ra_report ra_report;
7672774f206SBjoern A. Zeeb
7682774f206SBjoern A. Zeeb bool use_cfg_mask;
7692774f206SBjoern A. Zeeb struct cfg80211_bitrate_mask *mask;
77090aac0d8SBjoern A. Zeeb
77190aac0d8SBjoern A. Zeeb struct work_struct rc_work;
7722774f206SBjoern A. Zeeb };
7732774f206SBjoern A. Zeeb
7742774f206SBjoern A. Zeeb enum rtw_bfee_role {
7752774f206SBjoern A. Zeeb RTW_BFEE_NONE,
7762774f206SBjoern A. Zeeb RTW_BFEE_SU,
7772774f206SBjoern A. Zeeb RTW_BFEE_MU
7782774f206SBjoern A. Zeeb };
7792774f206SBjoern A. Zeeb
7802774f206SBjoern A. Zeeb struct rtw_bfee {
7812774f206SBjoern A. Zeeb enum rtw_bfee_role role;
7822774f206SBjoern A. Zeeb
7832774f206SBjoern A. Zeeb u16 p_aid;
7842774f206SBjoern A. Zeeb u8 g_id;
7852774f206SBjoern A. Zeeb u8 mac_addr[ETH_ALEN];
7862774f206SBjoern A. Zeeb u8 sound_dim;
7872774f206SBjoern A. Zeeb
7882774f206SBjoern A. Zeeb /* SU-MIMO */
7892774f206SBjoern A. Zeeb u8 su_reg_index;
7902774f206SBjoern A. Zeeb
7912774f206SBjoern A. Zeeb /* MU-MIMO */
7922774f206SBjoern A. Zeeb u16 aid;
7932774f206SBjoern A. Zeeb };
7942774f206SBjoern A. Zeeb
7952774f206SBjoern A. Zeeb struct rtw_bf_info {
7962774f206SBjoern A. Zeeb u8 bfer_mu_cnt;
7972774f206SBjoern A. Zeeb u8 bfer_su_cnt;
7982774f206SBjoern A. Zeeb DECLARE_BITMAP(bfer_su_reg_maping, 2);
7992774f206SBjoern A. Zeeb u8 cur_csi_rpt_rate;
8002774f206SBjoern A. Zeeb };
8012774f206SBjoern A. Zeeb
8022774f206SBjoern A. Zeeb struct rtw_vif {
8032774f206SBjoern A. Zeeb enum rtw_net_type net_type;
8042774f206SBjoern A. Zeeb u16 aid;
80590aac0d8SBjoern A. Zeeb u8 mac_id; /* for STA mode only */
8062774f206SBjoern A. Zeeb u8 mac_addr[ETH_ALEN];
8072774f206SBjoern A. Zeeb u8 bssid[ETH_ALEN];
8082774f206SBjoern A. Zeeb u8 port;
8092774f206SBjoern A. Zeeb u8 bcn_ctrl;
8102774f206SBjoern A. Zeeb struct list_head rsvd_page_list;
8112774f206SBjoern A. Zeeb struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS];
8122774f206SBjoern A. Zeeb const struct rtw_vif_port *conf;
8132774f206SBjoern A. Zeeb struct cfg80211_scan_request *scan_req;
8142774f206SBjoern A. Zeeb struct ieee80211_scan_ies *scan_ies;
8152774f206SBjoern A. Zeeb
8162774f206SBjoern A. Zeeb struct rtw_traffic_stats stats;
8172774f206SBjoern A. Zeeb
8182774f206SBjoern A. Zeeb struct rtw_bfee bfee;
8192774f206SBjoern A. Zeeb };
8202774f206SBjoern A. Zeeb
8212774f206SBjoern A. Zeeb struct rtw_regulatory {
8222774f206SBjoern A. Zeeb char alpha2[2];
8232774f206SBjoern A. Zeeb u8 txpwr_regd_2g;
8242774f206SBjoern A. Zeeb u8 txpwr_regd_5g;
8252774f206SBjoern A. Zeeb };
8262774f206SBjoern A. Zeeb
8272774f206SBjoern A. Zeeb enum rtw_regd_state {
8282774f206SBjoern A. Zeeb RTW_REGD_STATE_WORLDWIDE,
8292774f206SBjoern A. Zeeb RTW_REGD_STATE_PROGRAMMED,
8302774f206SBjoern A. Zeeb RTW_REGD_STATE_SETTING,
8312774f206SBjoern A. Zeeb
8322774f206SBjoern A. Zeeb RTW_REGD_STATE_NR,
8332774f206SBjoern A. Zeeb };
8342774f206SBjoern A. Zeeb
8352774f206SBjoern A. Zeeb struct rtw_regd {
8362774f206SBjoern A. Zeeb enum rtw_regd_state state;
8372774f206SBjoern A. Zeeb const struct rtw_regulatory *regulatory;
8382774f206SBjoern A. Zeeb enum nl80211_dfs_regions dfs_region;
8392774f206SBjoern A. Zeeb };
8402774f206SBjoern A. Zeeb
8412774f206SBjoern A. Zeeb struct rtw_chip_ops {
8422774f206SBjoern A. Zeeb int (*mac_init)(struct rtw_dev *rtwdev);
8432774f206SBjoern A. Zeeb int (*dump_fw_crash)(struct rtw_dev *rtwdev);
8442774f206SBjoern A. Zeeb void (*shutdown)(struct rtw_dev *rtwdev);
8452774f206SBjoern A. Zeeb int (*read_efuse)(struct rtw_dev *rtwdev, u8 *map);
8462774f206SBjoern A. Zeeb void (*phy_set_param)(struct rtw_dev *rtwdev);
8472774f206SBjoern A. Zeeb void (*set_channel)(struct rtw_dev *rtwdev, u8 channel,
8482774f206SBjoern A. Zeeb u8 bandwidth, u8 primary_chan_idx);
8492774f206SBjoern A. Zeeb void (*query_rx_desc)(struct rtw_dev *rtwdev, u8 *rx_desc,
8502774f206SBjoern A. Zeeb struct rtw_rx_pkt_stat *pkt_stat,
8512774f206SBjoern A. Zeeb struct ieee80211_rx_status *rx_status);
8522774f206SBjoern A. Zeeb u32 (*read_rf)(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
8532774f206SBjoern A. Zeeb u32 addr, u32 mask);
8542774f206SBjoern A. Zeeb bool (*write_rf)(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
8552774f206SBjoern A. Zeeb u32 addr, u32 mask, u32 data);
8562774f206SBjoern A. Zeeb void (*set_tx_power_index)(struct rtw_dev *rtwdev);
8572774f206SBjoern A. Zeeb int (*rsvd_page_dump)(struct rtw_dev *rtwdev, u8 *buf, u32 offset,
8582774f206SBjoern A. Zeeb u32 size);
8592774f206SBjoern A. Zeeb int (*set_antenna)(struct rtw_dev *rtwdev,
8602774f206SBjoern A. Zeeb u32 antenna_tx,
8612774f206SBjoern A. Zeeb u32 antenna_rx);
8622774f206SBjoern A. Zeeb void (*cfg_ldo25)(struct rtw_dev *rtwdev, bool enable);
8632774f206SBjoern A. Zeeb void (*efuse_grant)(struct rtw_dev *rtwdev, bool enable);
8642774f206SBjoern A. Zeeb void (*false_alarm_statistics)(struct rtw_dev *rtwdev);
8652774f206SBjoern A. Zeeb void (*phy_calibration)(struct rtw_dev *rtwdev);
8662774f206SBjoern A. Zeeb void (*dpk_track)(struct rtw_dev *rtwdev);
8672774f206SBjoern A. Zeeb void (*cck_pd_set)(struct rtw_dev *rtwdev, u8 level);
8682774f206SBjoern A. Zeeb void (*pwr_track)(struct rtw_dev *rtwdev);
8692774f206SBjoern A. Zeeb void (*config_bfee)(struct rtw_dev *rtwdev, struct rtw_vif *vif,
8702774f206SBjoern A. Zeeb struct rtw_bfee *bfee, bool enable);
8712774f206SBjoern A. Zeeb void (*set_gid_table)(struct rtw_dev *rtwdev,
8722774f206SBjoern A. Zeeb struct ieee80211_vif *vif,
8732774f206SBjoern A. Zeeb struct ieee80211_bss_conf *conf);
8742774f206SBjoern A. Zeeb void (*cfg_csi_rate)(struct rtw_dev *rtwdev, u8 rssi, u8 cur_rate,
8752774f206SBjoern A. Zeeb u8 fixrate_en, u8 *new_rate);
8762774f206SBjoern A. Zeeb void (*adaptivity_init)(struct rtw_dev *rtwdev);
8772774f206SBjoern A. Zeeb void (*adaptivity)(struct rtw_dev *rtwdev);
8782774f206SBjoern A. Zeeb void (*cfo_init)(struct rtw_dev *rtwdev);
8792774f206SBjoern A. Zeeb void (*cfo_track)(struct rtw_dev *rtwdev);
8802774f206SBjoern A. Zeeb void (*config_tx_path)(struct rtw_dev *rtwdev, u8 tx_path,
8812774f206SBjoern A. Zeeb enum rtw_bb_path tx_path_1ss,
8822774f206SBjoern A. Zeeb enum rtw_bb_path tx_path_cck,
8832774f206SBjoern A. Zeeb bool is_tx2_path);
8849c951734SBjoern A. Zeeb void (*config_txrx_mode)(struct rtw_dev *rtwdev, u8 tx_path,
8859c951734SBjoern A. Zeeb u8 rx_path, bool is_tx2_path);
88690aac0d8SBjoern A. Zeeb /* for USB/SDIO only */
88790aac0d8SBjoern A. Zeeb void (*fill_txdesc_checksum)(struct rtw_dev *rtwdev,
88890aac0d8SBjoern A. Zeeb struct rtw_tx_pkt_info *pkt_info,
88990aac0d8SBjoern A. Zeeb u8 *txdesc);
8902774f206SBjoern A. Zeeb
8912774f206SBjoern A. Zeeb /* for coex */
8922774f206SBjoern A. Zeeb void (*coex_set_init)(struct rtw_dev *rtwdev);
8932774f206SBjoern A. Zeeb void (*coex_set_ant_switch)(struct rtw_dev *rtwdev,
8942774f206SBjoern A. Zeeb u8 ctrl_type, u8 pos_type);
8952774f206SBjoern A. Zeeb void (*coex_set_gnt_fix)(struct rtw_dev *rtwdev);
8962774f206SBjoern A. Zeeb void (*coex_set_gnt_debug)(struct rtw_dev *rtwdev);
8972774f206SBjoern A. Zeeb void (*coex_set_rfe_type)(struct rtw_dev *rtwdev);
8982774f206SBjoern A. Zeeb void (*coex_set_wl_tx_power)(struct rtw_dev *rtwdev, u8 wl_pwr);
8992774f206SBjoern A. Zeeb void (*coex_set_wl_rx_gain)(struct rtw_dev *rtwdev, bool low_gain);
9002774f206SBjoern A. Zeeb };
9012774f206SBjoern A. Zeeb
9022774f206SBjoern A. Zeeb #define RTW_PWR_POLLING_CNT 20000
9032774f206SBjoern A. Zeeb
9042774f206SBjoern A. Zeeb #define RTW_PWR_CMD_READ 0x00
9052774f206SBjoern A. Zeeb #define RTW_PWR_CMD_WRITE 0x01
9062774f206SBjoern A. Zeeb #define RTW_PWR_CMD_POLLING 0x02
9072774f206SBjoern A. Zeeb #define RTW_PWR_CMD_DELAY 0x03
9082774f206SBjoern A. Zeeb #define RTW_PWR_CMD_END 0x04
9092774f206SBjoern A. Zeeb
9102774f206SBjoern A. Zeeb /* define the base address of each block */
9112774f206SBjoern A. Zeeb #define RTW_PWR_ADDR_MAC 0x00
9122774f206SBjoern A. Zeeb #define RTW_PWR_ADDR_USB 0x01
9132774f206SBjoern A. Zeeb #define RTW_PWR_ADDR_PCIE 0x02
9142774f206SBjoern A. Zeeb #define RTW_PWR_ADDR_SDIO 0x03
9152774f206SBjoern A. Zeeb
9162774f206SBjoern A. Zeeb #define RTW_PWR_INTF_SDIO_MSK BIT(0)
9172774f206SBjoern A. Zeeb #define RTW_PWR_INTF_USB_MSK BIT(1)
9182774f206SBjoern A. Zeeb #define RTW_PWR_INTF_PCI_MSK BIT(2)
9192774f206SBjoern A. Zeeb #define RTW_PWR_INTF_ALL_MSK (BIT(0) | BIT(1) | BIT(2) | BIT(3))
9202774f206SBjoern A. Zeeb
9212774f206SBjoern A. Zeeb #define RTW_PWR_CUT_TEST_MSK BIT(0)
9222774f206SBjoern A. Zeeb #define RTW_PWR_CUT_A_MSK BIT(1)
9232774f206SBjoern A. Zeeb #define RTW_PWR_CUT_B_MSK BIT(2)
9242774f206SBjoern A. Zeeb #define RTW_PWR_CUT_C_MSK BIT(3)
9252774f206SBjoern A. Zeeb #define RTW_PWR_CUT_D_MSK BIT(4)
9262774f206SBjoern A. Zeeb #define RTW_PWR_CUT_E_MSK BIT(5)
9272774f206SBjoern A. Zeeb #define RTW_PWR_CUT_F_MSK BIT(6)
9282774f206SBjoern A. Zeeb #define RTW_PWR_CUT_G_MSK BIT(7)
9292774f206SBjoern A. Zeeb #define RTW_PWR_CUT_ALL_MSK 0xFF
9302774f206SBjoern A. Zeeb
9312774f206SBjoern A. Zeeb enum rtw_pwr_seq_cmd_delay_unit {
9322774f206SBjoern A. Zeeb RTW_PWR_DELAY_US,
9332774f206SBjoern A. Zeeb RTW_PWR_DELAY_MS,
9342774f206SBjoern A. Zeeb };
9352774f206SBjoern A. Zeeb
9362774f206SBjoern A. Zeeb struct rtw_pwr_seq_cmd {
9372774f206SBjoern A. Zeeb u16 offset;
9382774f206SBjoern A. Zeeb u8 cut_mask;
9392774f206SBjoern A. Zeeb u8 intf_mask;
9402774f206SBjoern A. Zeeb u8 base:4;
9412774f206SBjoern A. Zeeb u8 cmd:4;
9422774f206SBjoern A. Zeeb u8 mask;
9432774f206SBjoern A. Zeeb u8 value;
9442774f206SBjoern A. Zeeb };
9452774f206SBjoern A. Zeeb
9462774f206SBjoern A. Zeeb enum rtw_chip_ver {
9472774f206SBjoern A. Zeeb RTW_CHIP_VER_CUT_A = 0x00,
9482774f206SBjoern A. Zeeb RTW_CHIP_VER_CUT_B = 0x01,
9492774f206SBjoern A. Zeeb RTW_CHIP_VER_CUT_C = 0x02,
9502774f206SBjoern A. Zeeb RTW_CHIP_VER_CUT_D = 0x03,
9512774f206SBjoern A. Zeeb RTW_CHIP_VER_CUT_E = 0x04,
9522774f206SBjoern A. Zeeb RTW_CHIP_VER_CUT_F = 0x05,
9532774f206SBjoern A. Zeeb RTW_CHIP_VER_CUT_G = 0x06,
9542774f206SBjoern A. Zeeb };
9552774f206SBjoern A. Zeeb
9562774f206SBjoern A. Zeeb #define RTW_INTF_PHY_PLATFORM_ALL 0
9572774f206SBjoern A. Zeeb
9582774f206SBjoern A. Zeeb enum rtw_intf_phy_cut {
9592774f206SBjoern A. Zeeb RTW_INTF_PHY_CUT_A = BIT(0),
9602774f206SBjoern A. Zeeb RTW_INTF_PHY_CUT_B = BIT(1),
9612774f206SBjoern A. Zeeb RTW_INTF_PHY_CUT_C = BIT(2),
9622774f206SBjoern A. Zeeb RTW_INTF_PHY_CUT_D = BIT(3),
9632774f206SBjoern A. Zeeb RTW_INTF_PHY_CUT_E = BIT(4),
9642774f206SBjoern A. Zeeb RTW_INTF_PHY_CUT_F = BIT(5),
9652774f206SBjoern A. Zeeb RTW_INTF_PHY_CUT_G = BIT(6),
9662774f206SBjoern A. Zeeb RTW_INTF_PHY_CUT_ALL = 0xFFFF,
9672774f206SBjoern A. Zeeb };
9682774f206SBjoern A. Zeeb
9692774f206SBjoern A. Zeeb enum rtw_ip_sel {
9702774f206SBjoern A. Zeeb RTW_IP_SEL_PHY = 0,
9712774f206SBjoern A. Zeeb RTW_IP_SEL_MAC = 1,
9722774f206SBjoern A. Zeeb RTW_IP_SEL_DBI = 2,
9732774f206SBjoern A. Zeeb
9742774f206SBjoern A. Zeeb RTW_IP_SEL_UNDEF = 0xFFFF
9752774f206SBjoern A. Zeeb };
9762774f206SBjoern A. Zeeb
9772774f206SBjoern A. Zeeb enum rtw_pq_map_id {
9782774f206SBjoern A. Zeeb RTW_PQ_MAP_VO = 0x0,
9792774f206SBjoern A. Zeeb RTW_PQ_MAP_VI = 0x1,
9802774f206SBjoern A. Zeeb RTW_PQ_MAP_BE = 0x2,
9812774f206SBjoern A. Zeeb RTW_PQ_MAP_BK = 0x3,
9822774f206SBjoern A. Zeeb RTW_PQ_MAP_MG = 0x4,
9832774f206SBjoern A. Zeeb RTW_PQ_MAP_HI = 0x5,
9842774f206SBjoern A. Zeeb RTW_PQ_MAP_NUM = 0x6,
9852774f206SBjoern A. Zeeb
9862774f206SBjoern A. Zeeb RTW_PQ_MAP_UNDEF,
9872774f206SBjoern A. Zeeb };
9882774f206SBjoern A. Zeeb
9892774f206SBjoern A. Zeeb enum rtw_dma_mapping {
9902774f206SBjoern A. Zeeb RTW_DMA_MAPPING_EXTRA = 0,
9912774f206SBjoern A. Zeeb RTW_DMA_MAPPING_LOW = 1,
9922774f206SBjoern A. Zeeb RTW_DMA_MAPPING_NORMAL = 2,
9932774f206SBjoern A. Zeeb RTW_DMA_MAPPING_HIGH = 3,
9942774f206SBjoern A. Zeeb
9952774f206SBjoern A. Zeeb RTW_DMA_MAPPING_MAX,
9962774f206SBjoern A. Zeeb RTW_DMA_MAPPING_UNDEF,
9972774f206SBjoern A. Zeeb };
9982774f206SBjoern A. Zeeb
9992774f206SBjoern A. Zeeb struct rtw_rqpn {
10002774f206SBjoern A. Zeeb enum rtw_dma_mapping dma_map_vo;
10012774f206SBjoern A. Zeeb enum rtw_dma_mapping dma_map_vi;
10022774f206SBjoern A. Zeeb enum rtw_dma_mapping dma_map_be;
10032774f206SBjoern A. Zeeb enum rtw_dma_mapping dma_map_bk;
10042774f206SBjoern A. Zeeb enum rtw_dma_mapping dma_map_mg;
10052774f206SBjoern A. Zeeb enum rtw_dma_mapping dma_map_hi;
10062774f206SBjoern A. Zeeb };
10072774f206SBjoern A. Zeeb
10082774f206SBjoern A. Zeeb struct rtw_prioq_addr {
10092774f206SBjoern A. Zeeb u32 rsvd;
10102774f206SBjoern A. Zeeb u32 avail;
10112774f206SBjoern A. Zeeb };
10122774f206SBjoern A. Zeeb
10132774f206SBjoern A. Zeeb struct rtw_prioq_addrs {
10142774f206SBjoern A. Zeeb struct rtw_prioq_addr prio[RTW_DMA_MAPPING_MAX];
10152774f206SBjoern A. Zeeb bool wsize;
10162774f206SBjoern A. Zeeb };
10172774f206SBjoern A. Zeeb
10182774f206SBjoern A. Zeeb struct rtw_page_table {
10192774f206SBjoern A. Zeeb u16 hq_num;
10202774f206SBjoern A. Zeeb u16 nq_num;
10212774f206SBjoern A. Zeeb u16 lq_num;
10222774f206SBjoern A. Zeeb u16 exq_num;
10232774f206SBjoern A. Zeeb u16 gapq_num;
10242774f206SBjoern A. Zeeb };
10252774f206SBjoern A. Zeeb
10262774f206SBjoern A. Zeeb struct rtw_intf_phy_para {
10272774f206SBjoern A. Zeeb u16 offset;
10282774f206SBjoern A. Zeeb u16 value;
10292774f206SBjoern A. Zeeb u16 ip_sel;
10302774f206SBjoern A. Zeeb u16 cut_mask;
10312774f206SBjoern A. Zeeb u16 platform;
10322774f206SBjoern A. Zeeb };
10332774f206SBjoern A. Zeeb
10342774f206SBjoern A. Zeeb struct rtw_wow_pattern {
10352774f206SBjoern A. Zeeb u16 crc;
10362774f206SBjoern A. Zeeb u8 type;
10372774f206SBjoern A. Zeeb u8 valid;
10382774f206SBjoern A. Zeeb u8 mask[RTW_MAX_PATTERN_MASK_SIZE];
10392774f206SBjoern A. Zeeb };
10402774f206SBjoern A. Zeeb
10412774f206SBjoern A. Zeeb struct rtw_pno_request {
10422774f206SBjoern A. Zeeb bool inited;
10432774f206SBjoern A. Zeeb u32 match_set_cnt;
10442774f206SBjoern A. Zeeb struct cfg80211_match_set *match_sets;
10452774f206SBjoern A. Zeeb u8 channel_cnt;
10462774f206SBjoern A. Zeeb struct ieee80211_channel *channels;
10472774f206SBjoern A. Zeeb struct cfg80211_sched_scan_plan scan_plan;
10482774f206SBjoern A. Zeeb };
10492774f206SBjoern A. Zeeb
10502774f206SBjoern A. Zeeb struct rtw_wow_param {
10512774f206SBjoern A. Zeeb struct ieee80211_vif *wow_vif;
10522774f206SBjoern A. Zeeb DECLARE_BITMAP(flags, RTW_WOW_FLAG_MAX);
10532774f206SBjoern A. Zeeb u8 txpause;
10542774f206SBjoern A. Zeeb u8 pattern_cnt;
10552774f206SBjoern A. Zeeb struct rtw_wow_pattern patterns[RTW_MAX_PATTERN_NUM];
10562774f206SBjoern A. Zeeb
10572774f206SBjoern A. Zeeb bool ips_enabled;
10582774f206SBjoern A. Zeeb struct rtw_pno_request pno_req;
10592774f206SBjoern A. Zeeb };
10602774f206SBjoern A. Zeeb
10612774f206SBjoern A. Zeeb struct rtw_intf_phy_para_table {
10622774f206SBjoern A. Zeeb const struct rtw_intf_phy_para *usb2_para;
10632774f206SBjoern A. Zeeb const struct rtw_intf_phy_para *usb3_para;
10642774f206SBjoern A. Zeeb const struct rtw_intf_phy_para *gen1_para;
10652774f206SBjoern A. Zeeb const struct rtw_intf_phy_para *gen2_para;
10662774f206SBjoern A. Zeeb u8 n_usb2_para;
10672774f206SBjoern A. Zeeb u8 n_usb3_para;
10682774f206SBjoern A. Zeeb u8 n_gen1_para;
10692774f206SBjoern A. Zeeb u8 n_gen2_para;
10702774f206SBjoern A. Zeeb };
10712774f206SBjoern A. Zeeb
10722774f206SBjoern A. Zeeb struct rtw_table {
10732774f206SBjoern A. Zeeb const void *data;
10742774f206SBjoern A. Zeeb const u32 size;
10752774f206SBjoern A. Zeeb void (*parse)(struct rtw_dev *rtwdev, const struct rtw_table *tbl);
10762774f206SBjoern A. Zeeb void (*do_cfg)(struct rtw_dev *rtwdev, const struct rtw_table *tbl,
10772774f206SBjoern A. Zeeb u32 addr, u32 data);
10782774f206SBjoern A. Zeeb enum rtw_rf_path rf_path;
10792774f206SBjoern A. Zeeb };
10802774f206SBjoern A. Zeeb
rtw_load_table(struct rtw_dev * rtwdev,const struct rtw_table * tbl)10812774f206SBjoern A. Zeeb static inline void rtw_load_table(struct rtw_dev *rtwdev,
10822774f206SBjoern A. Zeeb const struct rtw_table *tbl)
10832774f206SBjoern A. Zeeb {
10842774f206SBjoern A. Zeeb (*tbl->parse)(rtwdev, tbl);
10852774f206SBjoern A. Zeeb }
10862774f206SBjoern A. Zeeb
10872774f206SBjoern A. Zeeb enum rtw_rfe_fem {
10882774f206SBjoern A. Zeeb RTW_RFE_IFEM,
10892774f206SBjoern A. Zeeb RTW_RFE_EFEM,
10902774f206SBjoern A. Zeeb RTW_RFE_IFEM2G_EFEM5G,
10912774f206SBjoern A. Zeeb RTW_RFE_NUM,
10922774f206SBjoern A. Zeeb };
10932774f206SBjoern A. Zeeb
10942774f206SBjoern A. Zeeb struct rtw_rfe_def {
10952774f206SBjoern A. Zeeb const struct rtw_table *phy_pg_tbl;
10962774f206SBjoern A. Zeeb const struct rtw_table *txpwr_lmt_tbl;
10972774f206SBjoern A. Zeeb const struct rtw_table *agc_btg_tbl;
10982774f206SBjoern A. Zeeb };
10992774f206SBjoern A. Zeeb
11002774f206SBjoern A. Zeeb #define RTW_DEF_RFE(chip, bb_pg, pwrlmt) { \
11012774f206SBjoern A. Zeeb .phy_pg_tbl = &rtw ## chip ## _bb_pg_type ## bb_pg ## _tbl, \
11022774f206SBjoern A. Zeeb .txpwr_lmt_tbl = &rtw ## chip ## _txpwr_lmt_type ## pwrlmt ## _tbl, \
11032774f206SBjoern A. Zeeb }
11042774f206SBjoern A. Zeeb
11052774f206SBjoern A. Zeeb #define RTW_DEF_RFE_EXT(chip, bb_pg, pwrlmt, btg) { \
11062774f206SBjoern A. Zeeb .phy_pg_tbl = &rtw ## chip ## _bb_pg_type ## bb_pg ## _tbl, \
11072774f206SBjoern A. Zeeb .txpwr_lmt_tbl = &rtw ## chip ## _txpwr_lmt_type ## pwrlmt ## _tbl, \
11082774f206SBjoern A. Zeeb .agc_btg_tbl = &rtw ## chip ## _agc_btg_type ## btg ## _tbl, \
11092774f206SBjoern A. Zeeb }
11102774f206SBjoern A. Zeeb
11112774f206SBjoern A. Zeeb #define RTW_PWR_TRK_5G_1 0
11122774f206SBjoern A. Zeeb #define RTW_PWR_TRK_5G_2 1
11132774f206SBjoern A. Zeeb #define RTW_PWR_TRK_5G_3 2
11142774f206SBjoern A. Zeeb #define RTW_PWR_TRK_5G_NUM 3
11152774f206SBjoern A. Zeeb
11162774f206SBjoern A. Zeeb #define RTW_PWR_TRK_TBL_SZ 30
11172774f206SBjoern A. Zeeb
11182774f206SBjoern A. Zeeb /* This table stores the values of TX power that will be adjusted by power
11192774f206SBjoern A. Zeeb * tracking.
11202774f206SBjoern A. Zeeb *
11212774f206SBjoern A. Zeeb * For 5G bands, there are 3 different settings.
11222774f206SBjoern A. Zeeb * For 2G there are cck rate and ofdm rate with different settings.
11232774f206SBjoern A. Zeeb */
11242774f206SBjoern A. Zeeb struct rtw_pwr_track_tbl {
11252774f206SBjoern A. Zeeb const u8 *pwrtrk_5gb_n[RTW_PWR_TRK_5G_NUM];
11262774f206SBjoern A. Zeeb const u8 *pwrtrk_5gb_p[RTW_PWR_TRK_5G_NUM];
11272774f206SBjoern A. Zeeb const u8 *pwrtrk_5ga_n[RTW_PWR_TRK_5G_NUM];
11282774f206SBjoern A. Zeeb const u8 *pwrtrk_5ga_p[RTW_PWR_TRK_5G_NUM];
11292774f206SBjoern A. Zeeb const u8 *pwrtrk_2gb_n;
11302774f206SBjoern A. Zeeb const u8 *pwrtrk_2gb_p;
11312774f206SBjoern A. Zeeb const u8 *pwrtrk_2ga_n;
11322774f206SBjoern A. Zeeb const u8 *pwrtrk_2ga_p;
11332774f206SBjoern A. Zeeb const u8 *pwrtrk_2g_cckb_n;
11342774f206SBjoern A. Zeeb const u8 *pwrtrk_2g_cckb_p;
11352774f206SBjoern A. Zeeb const u8 *pwrtrk_2g_ccka_n;
11362774f206SBjoern A. Zeeb const u8 *pwrtrk_2g_ccka_p;
11372774f206SBjoern A. Zeeb const s8 *pwrtrk_xtal_n;
11382774f206SBjoern A. Zeeb const s8 *pwrtrk_xtal_p;
11392774f206SBjoern A. Zeeb };
11402774f206SBjoern A. Zeeb
11412774f206SBjoern A. Zeeb enum rtw_wlan_cpu {
11422774f206SBjoern A. Zeeb RTW_WCPU_11AC,
11432774f206SBjoern A. Zeeb RTW_WCPU_11N,
11442774f206SBjoern A. Zeeb };
11452774f206SBjoern A. Zeeb
11462774f206SBjoern A. Zeeb enum rtw_fw_fifo_sel {
11472774f206SBjoern A. Zeeb RTW_FW_FIFO_SEL_TX,
11482774f206SBjoern A. Zeeb RTW_FW_FIFO_SEL_RX,
11492774f206SBjoern A. Zeeb RTW_FW_FIFO_SEL_RSVD_PAGE,
11502774f206SBjoern A. Zeeb RTW_FW_FIFO_SEL_REPORT,
11512774f206SBjoern A. Zeeb RTW_FW_FIFO_SEL_LLT,
11522774f206SBjoern A. Zeeb RTW_FW_FIFO_SEL_RXBUF_FW,
11532774f206SBjoern A. Zeeb
11542774f206SBjoern A. Zeeb RTW_FW_FIFO_MAX,
11552774f206SBjoern A. Zeeb };
11562774f206SBjoern A. Zeeb
11572774f206SBjoern A. Zeeb enum rtw_fwcd_item {
11582774f206SBjoern A. Zeeb RTW_FWCD_TLV,
11592774f206SBjoern A. Zeeb RTW_FWCD_REG,
11602774f206SBjoern A. Zeeb RTW_FWCD_ROM,
11612774f206SBjoern A. Zeeb RTW_FWCD_IMEM,
11622774f206SBjoern A. Zeeb RTW_FWCD_DMEM,
11632774f206SBjoern A. Zeeb RTW_FWCD_EMEM,
11642774f206SBjoern A. Zeeb };
11652774f206SBjoern A. Zeeb
11662774f206SBjoern A. Zeeb /* hardware configuration for each IC */
11672774f206SBjoern A. Zeeb struct rtw_chip_info {
11682774f206SBjoern A. Zeeb struct rtw_chip_ops *ops;
11692774f206SBjoern A. Zeeb u8 id;
11702774f206SBjoern A. Zeeb
11712774f206SBjoern A. Zeeb const char *fw_name;
11722774f206SBjoern A. Zeeb enum rtw_wlan_cpu wlan_cpu;
11732774f206SBjoern A. Zeeb u8 tx_pkt_desc_sz;
11742774f206SBjoern A. Zeeb u8 tx_buf_desc_sz;
11752774f206SBjoern A. Zeeb u8 rx_pkt_desc_sz;
11762774f206SBjoern A. Zeeb u8 rx_buf_desc_sz;
11772774f206SBjoern A. Zeeb u32 phy_efuse_size;
11782774f206SBjoern A. Zeeb u32 log_efuse_size;
11792774f206SBjoern A. Zeeb u32 ptct_efuse_size;
11802774f206SBjoern A. Zeeb u32 txff_size;
11812774f206SBjoern A. Zeeb u32 rxff_size;
11822774f206SBjoern A. Zeeb u32 fw_rxff_size;
118390aac0d8SBjoern A. Zeeb u16 rsvd_drv_pg_num;
11842774f206SBjoern A. Zeeb u8 band;
11852774f206SBjoern A. Zeeb u8 page_size;
11862774f206SBjoern A. Zeeb u8 csi_buf_pg_num;
11872774f206SBjoern A. Zeeb u8 dig_max;
11882774f206SBjoern A. Zeeb u8 dig_min;
11892774f206SBjoern A. Zeeb u8 txgi_factor;
11902774f206SBjoern A. Zeeb bool is_pwr_by_rate_dec;
11912774f206SBjoern A. Zeeb bool rx_ldpc;
11922774f206SBjoern A. Zeeb bool tx_stbc;
11932774f206SBjoern A. Zeeb u8 max_power_index;
11949c951734SBjoern A. Zeeb u8 ampdu_density;
11952774f206SBjoern A. Zeeb
11962774f206SBjoern A. Zeeb u16 fw_fifo_addr[RTW_FW_FIFO_MAX];
11972774f206SBjoern A. Zeeb const struct rtw_fwcd_segs *fwcd_segs;
11982774f206SBjoern A. Zeeb
11992774f206SBjoern A. Zeeb u8 default_1ss_tx_path;
12002774f206SBjoern A. Zeeb
12012774f206SBjoern A. Zeeb bool path_div_supported;
12022774f206SBjoern A. Zeeb bool ht_supported;
12032774f206SBjoern A. Zeeb bool vht_supported;
12042774f206SBjoern A. Zeeb u8 lps_deep_mode_supported;
12052774f206SBjoern A. Zeeb
12062774f206SBjoern A. Zeeb /* init values */
12072774f206SBjoern A. Zeeb u8 sys_func_en;
12082774f206SBjoern A. Zeeb const struct rtw_pwr_seq_cmd **pwr_on_seq;
12092774f206SBjoern A. Zeeb const struct rtw_pwr_seq_cmd **pwr_off_seq;
12102774f206SBjoern A. Zeeb const struct rtw_rqpn *rqpn_table;
12112774f206SBjoern A. Zeeb const struct rtw_prioq_addrs *prioq_addrs;
12122774f206SBjoern A. Zeeb const struct rtw_page_table *page_table;
12132774f206SBjoern A. Zeeb const struct rtw_intf_phy_para_table *intf_table;
12142774f206SBjoern A. Zeeb
12152774f206SBjoern A. Zeeb const struct rtw_hw_reg *dig;
12162774f206SBjoern A. Zeeb const struct rtw_hw_reg *dig_cck;
12172774f206SBjoern A. Zeeb u32 rf_base_addr[2];
12182774f206SBjoern A. Zeeb u32 rf_sipi_addr[2];
12192774f206SBjoern A. Zeeb const struct rtw_rf_sipi_addr *rf_sipi_read_addr;
12202774f206SBjoern A. Zeeb u8 fix_rf_phy_num;
12212774f206SBjoern A. Zeeb const struct rtw_ltecoex_addr *ltecoex_addr;
12222774f206SBjoern A. Zeeb
12232774f206SBjoern A. Zeeb const struct rtw_table *mac_tbl;
12242774f206SBjoern A. Zeeb const struct rtw_table *agc_tbl;
12252774f206SBjoern A. Zeeb const struct rtw_table *bb_tbl;
12262774f206SBjoern A. Zeeb const struct rtw_table *rf_tbl[RTW_RF_PATH_MAX];
12272774f206SBjoern A. Zeeb const struct rtw_table *rfk_init_tbl;
12282774f206SBjoern A. Zeeb
12292774f206SBjoern A. Zeeb const struct rtw_rfe_def *rfe_defs;
12302774f206SBjoern A. Zeeb u32 rfe_defs_size;
12312774f206SBjoern A. Zeeb
12322774f206SBjoern A. Zeeb bool en_dis_dpd;
12332774f206SBjoern A. Zeeb u16 dpd_ratemask;
12342774f206SBjoern A. Zeeb u8 iqk_threshold;
12352774f206SBjoern A. Zeeb u8 lck_threshold;
12362774f206SBjoern A. Zeeb const struct rtw_pwr_track_tbl *pwr_track_tbl;
12372774f206SBjoern A. Zeeb
12382774f206SBjoern A. Zeeb u8 bfer_su_max_num;
12392774f206SBjoern A. Zeeb u8 bfer_mu_max_num;
12402774f206SBjoern A. Zeeb
12412774f206SBjoern A. Zeeb struct rtw_hw_reg_offset *edcca_th;
12422774f206SBjoern A. Zeeb s8 l2h_th_ini_cs;
12432774f206SBjoern A. Zeeb s8 l2h_th_ini_ad;
12442774f206SBjoern A. Zeeb
12452774f206SBjoern A. Zeeb const char *wow_fw_name;
12462774f206SBjoern A. Zeeb const struct wiphy_wowlan_support *wowlan_stub;
12472774f206SBjoern A. Zeeb const u8 max_sched_scan_ssids;
124890aac0d8SBjoern A. Zeeb const u16 max_scan_ie_len;
12492774f206SBjoern A. Zeeb
12502774f206SBjoern A. Zeeb /* coex paras */
12512774f206SBjoern A. Zeeb u32 coex_para_ver;
12522774f206SBjoern A. Zeeb u8 bt_desired_ver;
12532774f206SBjoern A. Zeeb bool scbd_support;
12542774f206SBjoern A. Zeeb bool new_scbd10_def; /* true: fix 2M(8822c) */
12552774f206SBjoern A. Zeeb bool ble_hid_profile_support;
12569c951734SBjoern A. Zeeb bool wl_mimo_ps_support;
12572774f206SBjoern A. Zeeb u8 pstdma_type; /* 0: LPSoff, 1:LPSon */
12582774f206SBjoern A. Zeeb u8 bt_rssi_type;
12592774f206SBjoern A. Zeeb u8 ant_isolation;
12602774f206SBjoern A. Zeeb u8 rssi_tolerance;
12612774f206SBjoern A. Zeeb u8 table_sant_num;
12622774f206SBjoern A. Zeeb u8 table_nsant_num;
12632774f206SBjoern A. Zeeb u8 tdma_sant_num;
12642774f206SBjoern A. Zeeb u8 tdma_nsant_num;
12652774f206SBjoern A. Zeeb u8 bt_afh_span_bw20;
12662774f206SBjoern A. Zeeb u8 bt_afh_span_bw40;
12672774f206SBjoern A. Zeeb u8 afh_5g_num;
12682774f206SBjoern A. Zeeb u8 wl_rf_para_num;
12692774f206SBjoern A. Zeeb u8 coex_info_hw_regs_num;
12702774f206SBjoern A. Zeeb const u8 *bt_rssi_step;
12712774f206SBjoern A. Zeeb const u8 *wl_rssi_step;
12722774f206SBjoern A. Zeeb const struct coex_table_para *table_nsant;
12732774f206SBjoern A. Zeeb const struct coex_table_para *table_sant;
12742774f206SBjoern A. Zeeb const struct coex_tdma_para *tdma_sant;
12752774f206SBjoern A. Zeeb const struct coex_tdma_para *tdma_nsant;
12762774f206SBjoern A. Zeeb const struct coex_rf_para *wl_rf_para_tx;
12772774f206SBjoern A. Zeeb const struct coex_rf_para *wl_rf_para_rx;
12782774f206SBjoern A. Zeeb const struct coex_5g_afh_map *afh_5g;
12792774f206SBjoern A. Zeeb const struct rtw_hw_reg *btg_reg;
12802774f206SBjoern A. Zeeb const struct rtw_reg_domain *coex_info_hw_regs;
12812774f206SBjoern A. Zeeb u32 wl_fw_desired_ver;
12822774f206SBjoern A. Zeeb };
12832774f206SBjoern A. Zeeb
12842774f206SBjoern A. Zeeb enum rtw_coex_bt_state_cnt {
12852774f206SBjoern A. Zeeb COEX_CNT_BT_RETRY,
12862774f206SBjoern A. Zeeb COEX_CNT_BT_REINIT,
12872774f206SBjoern A. Zeeb COEX_CNT_BT_REENABLE,
12882774f206SBjoern A. Zeeb COEX_CNT_BT_POPEVENT,
12892774f206SBjoern A. Zeeb COEX_CNT_BT_SETUPLINK,
12902774f206SBjoern A. Zeeb COEX_CNT_BT_IGNWLANACT,
12912774f206SBjoern A. Zeeb COEX_CNT_BT_INQ,
12922774f206SBjoern A. Zeeb COEX_CNT_BT_PAGE,
12932774f206SBjoern A. Zeeb COEX_CNT_BT_ROLESWITCH,
12942774f206SBjoern A. Zeeb COEX_CNT_BT_AFHUPDATE,
12952774f206SBjoern A. Zeeb COEX_CNT_BT_INFOUPDATE,
12962774f206SBjoern A. Zeeb COEX_CNT_BT_IQK,
12972774f206SBjoern A. Zeeb COEX_CNT_BT_IQKFAIL,
12982774f206SBjoern A. Zeeb
12992774f206SBjoern A. Zeeb COEX_CNT_BT_MAX
13002774f206SBjoern A. Zeeb };
13012774f206SBjoern A. Zeeb
13022774f206SBjoern A. Zeeb enum rtw_coex_wl_state_cnt {
13032774f206SBjoern A. Zeeb COEX_CNT_WL_SCANAP,
13042774f206SBjoern A. Zeeb COEX_CNT_WL_CONNPKT,
13052774f206SBjoern A. Zeeb COEX_CNT_WL_COEXRUN,
13062774f206SBjoern A. Zeeb COEX_CNT_WL_NOISY0,
13072774f206SBjoern A. Zeeb COEX_CNT_WL_NOISY1,
13082774f206SBjoern A. Zeeb COEX_CNT_WL_NOISY2,
13092774f206SBjoern A. Zeeb COEX_CNT_WL_5MS_NOEXTEND,
13102774f206SBjoern A. Zeeb COEX_CNT_WL_FW_NOTIFY,
13112774f206SBjoern A. Zeeb
13122774f206SBjoern A. Zeeb COEX_CNT_WL_MAX
13132774f206SBjoern A. Zeeb };
13142774f206SBjoern A. Zeeb
13152774f206SBjoern A. Zeeb struct rtw_coex_rfe {
13162774f206SBjoern A. Zeeb bool ant_switch_exist;
13172774f206SBjoern A. Zeeb bool ant_switch_diversity;
13182774f206SBjoern A. Zeeb bool ant_switch_with_bt;
13192774f206SBjoern A. Zeeb u8 rfe_module_type;
13202774f206SBjoern A. Zeeb u8 ant_switch_polarity;
13212774f206SBjoern A. Zeeb
13222774f206SBjoern A. Zeeb /* true if WLG at BTG, else at WLAG */
13232774f206SBjoern A. Zeeb bool wlg_at_btg;
13242774f206SBjoern A. Zeeb };
13252774f206SBjoern A. Zeeb
13262774f206SBjoern A. Zeeb #define COEX_WL_TDMA_PARA_LENGTH 5
13272774f206SBjoern A. Zeeb
13282774f206SBjoern A. Zeeb struct rtw_coex_dm {
13292774f206SBjoern A. Zeeb bool cur_ps_tdma_on;
13302774f206SBjoern A. Zeeb bool cur_wl_rx_low_gain_en;
13312774f206SBjoern A. Zeeb bool ignore_wl_act;
13322774f206SBjoern A. Zeeb
13332774f206SBjoern A. Zeeb u8 reason;
13342774f206SBjoern A. Zeeb u8 bt_rssi_state[4];
13352774f206SBjoern A. Zeeb u8 wl_rssi_state[4];
13362774f206SBjoern A. Zeeb u8 wl_ch_info[3];
13372774f206SBjoern A. Zeeb u8 cur_ps_tdma;
13382774f206SBjoern A. Zeeb u8 cur_table;
13392774f206SBjoern A. Zeeb u8 ps_tdma_para[5];
13402774f206SBjoern A. Zeeb u8 cur_bt_pwr_lvl;
13412774f206SBjoern A. Zeeb u8 cur_bt_lna_lvl;
13422774f206SBjoern A. Zeeb u8 cur_wl_pwr_lvl;
13432774f206SBjoern A. Zeeb u8 bt_status;
13442774f206SBjoern A. Zeeb u32 cur_ant_pos_type;
13452774f206SBjoern A. Zeeb u32 cur_switch_status;
13462774f206SBjoern A. Zeeb u32 setting_tdma;
13472774f206SBjoern A. Zeeb u8 fw_tdma_para[COEX_WL_TDMA_PARA_LENGTH];
13482774f206SBjoern A. Zeeb };
13492774f206SBjoern A. Zeeb
13502774f206SBjoern A. Zeeb #define COEX_BTINFO_SRC_WL_FW 0x0
13512774f206SBjoern A. Zeeb #define COEX_BTINFO_SRC_BT_RSP 0x1
13522774f206SBjoern A. Zeeb #define COEX_BTINFO_SRC_BT_ACT 0x2
13532774f206SBjoern A. Zeeb #define COEX_BTINFO_SRC_BT_IQK 0x3
13542774f206SBjoern A. Zeeb #define COEX_BTINFO_SRC_BT_SCBD 0x4
13552774f206SBjoern A. Zeeb #define COEX_BTINFO_SRC_H2C60 0x5
13562774f206SBjoern A. Zeeb #define COEX_BTINFO_SRC_MAX 0x6
13572774f206SBjoern A. Zeeb
13582774f206SBjoern A. Zeeb #define COEX_INFO_FTP BIT(7)
13592774f206SBjoern A. Zeeb #define COEX_INFO_A2DP BIT(6)
13602774f206SBjoern A. Zeeb #define COEX_INFO_HID BIT(5)
13612774f206SBjoern A. Zeeb #define COEX_INFO_SCO_BUSY BIT(4)
13622774f206SBjoern A. Zeeb #define COEX_INFO_ACL_BUSY BIT(3)
13632774f206SBjoern A. Zeeb #define COEX_INFO_INQ_PAGE BIT(2)
13642774f206SBjoern A. Zeeb #define COEX_INFO_SCO_ESCO BIT(1)
13652774f206SBjoern A. Zeeb #define COEX_INFO_CONNECTION BIT(0)
13662774f206SBjoern A. Zeeb #define COEX_BTINFO_LENGTH_MAX 10
13672774f206SBjoern A. Zeeb #define COEX_BTINFO_LENGTH 7
13682774f206SBjoern A. Zeeb
13699c951734SBjoern A. Zeeb #define COEX_BT_HIDINFO_LIST 0x0
13709c951734SBjoern A. Zeeb #define COEX_BT_HIDINFO_A 0x1
13719c951734SBjoern A. Zeeb #define COEX_BT_HIDINFO_NAME 3
13729c951734SBjoern A. Zeeb
13739c951734SBjoern A. Zeeb #define COEX_BT_HIDINFO_LENGTH 6
13749c951734SBjoern A. Zeeb #define COEX_BT_HIDINFO_HANDLE_NUM 4
13759c951734SBjoern A. Zeeb #define COEX_BT_HIDINFO_C2H_HANDLE 0
13769c951734SBjoern A. Zeeb #define COEX_BT_HIDINFO_C2H_VENDOR 1
13779c951734SBjoern A. Zeeb #define COEX_BT_BLE_HANDLE_THRS 0x10
13789c951734SBjoern A. Zeeb #define COEX_BT_HIDINFO_NOTCON 0xff
13799c951734SBjoern A. Zeeb
13809c951734SBjoern A. Zeeb struct rtw_coex_hid {
13819c951734SBjoern A. Zeeb u8 hid_handle;
13829c951734SBjoern A. Zeeb u8 hid_vendor;
13839c951734SBjoern A. Zeeb u8 hid_name[COEX_BT_HIDINFO_NAME];
13849c951734SBjoern A. Zeeb bool hid_info_completed;
13859c951734SBjoern A. Zeeb bool is_game_hid;
13869c951734SBjoern A. Zeeb };
13879c951734SBjoern A. Zeeb
13889c951734SBjoern A. Zeeb struct rtw_coex_hid_handle_list {
13899c951734SBjoern A. Zeeb u8 cmd_id;
13909c951734SBjoern A. Zeeb u8 len;
13919c951734SBjoern A. Zeeb u8 subid;
13929c951734SBjoern A. Zeeb u8 handle_cnt;
13939c951734SBjoern A. Zeeb u8 handle[COEX_BT_HIDINFO_HANDLE_NUM];
13949c951734SBjoern A. Zeeb } __packed;
13959c951734SBjoern A. Zeeb
13969c951734SBjoern A. Zeeb struct rtw_coex_hid_info_a {
13979c951734SBjoern A. Zeeb u8 cmd_id;
13989c951734SBjoern A. Zeeb u8 len;
13999c951734SBjoern A. Zeeb u8 subid;
14009c951734SBjoern A. Zeeb u8 handle;
14019c951734SBjoern A. Zeeb u8 vendor;
14029c951734SBjoern A. Zeeb u8 name[COEX_BT_HIDINFO_NAME];
14039c951734SBjoern A. Zeeb } __packed;
14049c951734SBjoern A. Zeeb
14052774f206SBjoern A. Zeeb struct rtw_coex_stat {
14062774f206SBjoern A. Zeeb bool bt_disabled;
14072774f206SBjoern A. Zeeb bool bt_disabled_pre;
14082774f206SBjoern A. Zeeb bool bt_link_exist;
14092774f206SBjoern A. Zeeb bool bt_whck_test;
14102774f206SBjoern A. Zeeb bool bt_inq_page;
14112774f206SBjoern A. Zeeb bool bt_inq_remain;
14122774f206SBjoern A. Zeeb bool bt_inq;
14132774f206SBjoern A. Zeeb bool bt_page;
14142774f206SBjoern A. Zeeb bool bt_ble_voice;
14152774f206SBjoern A. Zeeb bool bt_ble_exist;
14162774f206SBjoern A. Zeeb bool bt_hfp_exist;
14172774f206SBjoern A. Zeeb bool bt_a2dp_exist;
14182774f206SBjoern A. Zeeb bool bt_hid_exist;
14192774f206SBjoern A. Zeeb bool bt_pan_exist; /* PAN or OPP */
14202774f206SBjoern A. Zeeb bool bt_opp_exist; /* OPP only */
14212774f206SBjoern A. Zeeb bool bt_acl_busy;
14222774f206SBjoern A. Zeeb bool bt_fix_2M;
14232774f206SBjoern A. Zeeb bool bt_setup_link;
14242774f206SBjoern A. Zeeb bool bt_multi_link;
14252774f206SBjoern A. Zeeb bool bt_multi_link_pre;
14262774f206SBjoern A. Zeeb bool bt_multi_link_remain;
14272774f206SBjoern A. Zeeb bool bt_a2dp_sink;
14282774f206SBjoern A. Zeeb bool bt_a2dp_active;
14292774f206SBjoern A. Zeeb bool bt_reenable;
14302774f206SBjoern A. Zeeb bool bt_ble_scan_en;
14312774f206SBjoern A. Zeeb bool bt_init_scan;
14322774f206SBjoern A. Zeeb bool bt_slave;
14332774f206SBjoern A. Zeeb bool bt_418_hid_exist;
14342774f206SBjoern A. Zeeb bool bt_ble_hid_exist;
14359c951734SBjoern A. Zeeb bool bt_game_hid_exist;
14369c951734SBjoern A. Zeeb bool bt_hid_handle_cnt;
14372774f206SBjoern A. Zeeb bool bt_mailbox_reply;
14382774f206SBjoern A. Zeeb
14392774f206SBjoern A. Zeeb bool wl_under_lps;
14402774f206SBjoern A. Zeeb bool wl_under_ips;
14412774f206SBjoern A. Zeeb bool wl_hi_pri_task1;
14422774f206SBjoern A. Zeeb bool wl_hi_pri_task2;
14432774f206SBjoern A. Zeeb bool wl_force_lps_ctrl;
14442774f206SBjoern A. Zeeb bool wl_gl_busy;
14452774f206SBjoern A. Zeeb bool wl_linkscan_proc;
14462774f206SBjoern A. Zeeb bool wl_ps_state_fail;
14472774f206SBjoern A. Zeeb bool wl_tx_limit_en;
14482774f206SBjoern A. Zeeb bool wl_ampdu_limit_en;
14492774f206SBjoern A. Zeeb bool wl_connected;
14502774f206SBjoern A. Zeeb bool wl_slot_extend;
14512774f206SBjoern A. Zeeb bool wl_cck_lock;
14522774f206SBjoern A. Zeeb bool wl_cck_lock_pre;
14532774f206SBjoern A. Zeeb bool wl_cck_lock_ever;
14542774f206SBjoern A. Zeeb bool wl_connecting;
14552774f206SBjoern A. Zeeb bool wl_slot_toggle;
14562774f206SBjoern A. Zeeb bool wl_slot_toggle_change; /* if toggle to no-toggle */
14579c951734SBjoern A. Zeeb bool wl_mimo_ps;
14582774f206SBjoern A. Zeeb
14592774f206SBjoern A. Zeeb u32 bt_supported_version;
14602774f206SBjoern A. Zeeb u32 bt_supported_feature;
14612774f206SBjoern A. Zeeb u32 hi_pri_tx;
14622774f206SBjoern A. Zeeb u32 hi_pri_rx;
14632774f206SBjoern A. Zeeb u32 lo_pri_tx;
14642774f206SBjoern A. Zeeb u32 lo_pri_rx;
14652774f206SBjoern A. Zeeb u32 patch_ver;
14662774f206SBjoern A. Zeeb u16 bt_reg_vendor_ae;
14672774f206SBjoern A. Zeeb u16 bt_reg_vendor_ac;
14682774f206SBjoern A. Zeeb s8 bt_rssi;
14692774f206SBjoern A. Zeeb u8 kt_ver;
14702774f206SBjoern A. Zeeb u8 gnt_workaround_state;
14712774f206SBjoern A. Zeeb u8 tdma_timer_base;
14722774f206SBjoern A. Zeeb u8 bt_profile_num;
14732774f206SBjoern A. Zeeb u8 bt_info_c2h[COEX_BTINFO_SRC_MAX][COEX_BTINFO_LENGTH_MAX];
14742774f206SBjoern A. Zeeb u8 bt_info_lb2;
14752774f206SBjoern A. Zeeb u8 bt_info_lb3;
14762774f206SBjoern A. Zeeb u8 bt_info_hb0;
14772774f206SBjoern A. Zeeb u8 bt_info_hb1;
14782774f206SBjoern A. Zeeb u8 bt_info_hb2;
14792774f206SBjoern A. Zeeb u8 bt_info_hb3;
14802774f206SBjoern A. Zeeb u8 bt_ble_scan_type;
14812774f206SBjoern A. Zeeb u8 bt_hid_pair_num;
14822774f206SBjoern A. Zeeb u8 bt_hid_slot;
14832774f206SBjoern A. Zeeb u8 bt_a2dp_bitpool;
14842774f206SBjoern A. Zeeb u8 bt_iqk_state;
14852774f206SBjoern A. Zeeb
14862774f206SBjoern A. Zeeb u16 wl_beacon_interval;
14872774f206SBjoern A. Zeeb u8 wl_noisy_level;
14882774f206SBjoern A. Zeeb u8 wl_fw_dbg_info[10];
14892774f206SBjoern A. Zeeb u8 wl_fw_dbg_info_pre[10];
14902774f206SBjoern A. Zeeb u8 wl_rx_rate;
14912774f206SBjoern A. Zeeb u8 wl_tx_rate;
14922774f206SBjoern A. Zeeb u8 wl_rts_rx_rate;
14932774f206SBjoern A. Zeeb u8 wl_coex_mode;
14942774f206SBjoern A. Zeeb u8 wl_iot_peer;
14952774f206SBjoern A. Zeeb u8 ampdu_max_time;
14962774f206SBjoern A. Zeeb u8 wl_tput_dir;
14972774f206SBjoern A. Zeeb
14982774f206SBjoern A. Zeeb u8 wl_toggle_para[6];
14992774f206SBjoern A. Zeeb u8 wl_toggle_interval;
15002774f206SBjoern A. Zeeb
15012774f206SBjoern A. Zeeb u16 score_board;
15022774f206SBjoern A. Zeeb u16 retry_limit;
15032774f206SBjoern A. Zeeb
15042774f206SBjoern A. Zeeb /* counters to record bt states */
15052774f206SBjoern A. Zeeb u32 cnt_bt[COEX_CNT_BT_MAX];
15062774f206SBjoern A. Zeeb
15072774f206SBjoern A. Zeeb /* counters to record wifi states */
15082774f206SBjoern A. Zeeb u32 cnt_wl[COEX_CNT_WL_MAX];
15092774f206SBjoern A. Zeeb
15102774f206SBjoern A. Zeeb /* counters to record bt c2h data */
15112774f206SBjoern A. Zeeb u32 cnt_bt_info_c2h[COEX_BTINFO_SRC_MAX];
15122774f206SBjoern A. Zeeb
15132774f206SBjoern A. Zeeb u32 darfrc;
15142774f206SBjoern A. Zeeb u32 darfrch;
15159c951734SBjoern A. Zeeb
15169c951734SBjoern A. Zeeb struct rtw_coex_hid hid_info[COEX_BT_HIDINFO_HANDLE_NUM];
15179c951734SBjoern A. Zeeb struct rtw_coex_hid_handle_list hid_handle_list;
15182774f206SBjoern A. Zeeb };
15192774f206SBjoern A. Zeeb
15202774f206SBjoern A. Zeeb struct rtw_coex {
15212774f206SBjoern A. Zeeb struct sk_buff_head queue;
15222774f206SBjoern A. Zeeb wait_queue_head_t wait;
15232774f206SBjoern A. Zeeb
15242774f206SBjoern A. Zeeb bool under_5g;
15252774f206SBjoern A. Zeeb bool stop_dm;
15262774f206SBjoern A. Zeeb bool freeze;
15272774f206SBjoern A. Zeeb bool freerun;
15282774f206SBjoern A. Zeeb bool wl_rf_off;
15292774f206SBjoern A. Zeeb bool manual_control;
15302774f206SBjoern A. Zeeb
15312774f206SBjoern A. Zeeb struct rtw_coex_stat stat;
15322774f206SBjoern A. Zeeb struct rtw_coex_dm dm;
15332774f206SBjoern A. Zeeb struct rtw_coex_rfe rfe;
15342774f206SBjoern A. Zeeb
15352774f206SBjoern A. Zeeb struct delayed_work bt_relink_work;
15362774f206SBjoern A. Zeeb struct delayed_work bt_reenable_work;
15372774f206SBjoern A. Zeeb struct delayed_work defreeze_work;
15382774f206SBjoern A. Zeeb struct delayed_work wl_remain_work;
15392774f206SBjoern A. Zeeb struct delayed_work bt_remain_work;
15402774f206SBjoern A. Zeeb struct delayed_work wl_connecting_work;
15412774f206SBjoern A. Zeeb struct delayed_work bt_multi_link_remain_work;
15422774f206SBjoern A. Zeeb struct delayed_work wl_ccklock_work;
15432774f206SBjoern A. Zeeb
15442774f206SBjoern A. Zeeb };
15452774f206SBjoern A. Zeeb
15462774f206SBjoern A. Zeeb #define DPK_RF_REG_NUM 7
15472774f206SBjoern A. Zeeb #define DPK_RF_PATH_NUM 2
15482774f206SBjoern A. Zeeb #define DPK_BB_REG_NUM 18
15492774f206SBjoern A. Zeeb #define DPK_CHANNEL_WIDTH_80 1
15502774f206SBjoern A. Zeeb
15512774f206SBjoern A. Zeeb DECLARE_EWMA(thermal, 10, 4);
15522774f206SBjoern A. Zeeb
15532774f206SBjoern A. Zeeb struct rtw_dpk_info {
15542774f206SBjoern A. Zeeb bool is_dpk_pwr_on;
15552774f206SBjoern A. Zeeb bool is_reload;
15562774f206SBjoern A. Zeeb
15572774f206SBjoern A. Zeeb DECLARE_BITMAP(dpk_path_ok, DPK_RF_PATH_NUM);
15582774f206SBjoern A. Zeeb
15592774f206SBjoern A. Zeeb u8 thermal_dpk[DPK_RF_PATH_NUM];
15602774f206SBjoern A. Zeeb struct ewma_thermal avg_thermal[DPK_RF_PATH_NUM];
15612774f206SBjoern A. Zeeb
15622774f206SBjoern A. Zeeb u32 gnt_control;
15632774f206SBjoern A. Zeeb u32 gnt_value;
15642774f206SBjoern A. Zeeb
15652774f206SBjoern A. Zeeb u8 result[RTW_RF_PATH_MAX];
15662774f206SBjoern A. Zeeb u8 dpk_txagc[RTW_RF_PATH_MAX];
15672774f206SBjoern A. Zeeb u32 coef[RTW_RF_PATH_MAX][20];
15682774f206SBjoern A. Zeeb u16 dpk_gs[RTW_RF_PATH_MAX];
15692774f206SBjoern A. Zeeb u8 thermal_dpk_delta[RTW_RF_PATH_MAX];
15702774f206SBjoern A. Zeeb u8 pre_pwsf[RTW_RF_PATH_MAX];
15712774f206SBjoern A. Zeeb
15722774f206SBjoern A. Zeeb u8 dpk_band;
15732774f206SBjoern A. Zeeb u8 dpk_ch;
15742774f206SBjoern A. Zeeb u8 dpk_bw;
15752774f206SBjoern A. Zeeb };
15762774f206SBjoern A. Zeeb
15772774f206SBjoern A. Zeeb struct rtw_phy_cck_pd_reg {
15782774f206SBjoern A. Zeeb u32 reg_pd;
15792774f206SBjoern A. Zeeb u32 mask_pd;
15802774f206SBjoern A. Zeeb u32 reg_cs;
15812774f206SBjoern A. Zeeb u32 mask_cs;
15822774f206SBjoern A. Zeeb };
15832774f206SBjoern A. Zeeb
15842774f206SBjoern A. Zeeb #define DACK_MSBK_BACKUP_NUM 0xf
15852774f206SBjoern A. Zeeb #define DACK_DCK_BACKUP_NUM 0x2
15862774f206SBjoern A. Zeeb
15872774f206SBjoern A. Zeeb struct rtw_swing_table {
15882774f206SBjoern A. Zeeb const u8 *p[RTW_RF_PATH_MAX];
15892774f206SBjoern A. Zeeb const u8 *n[RTW_RF_PATH_MAX];
15902774f206SBjoern A. Zeeb };
15912774f206SBjoern A. Zeeb
15922774f206SBjoern A. Zeeb struct rtw_pkt_count {
15932774f206SBjoern A. Zeeb u16 num_bcn_pkt;
15942774f206SBjoern A. Zeeb u16 num_qry_pkt[DESC_RATE_MAX];
15952774f206SBjoern A. Zeeb };
15962774f206SBjoern A. Zeeb
15972774f206SBjoern A. Zeeb DECLARE_EWMA(evm, 10, 4);
15982774f206SBjoern A. Zeeb DECLARE_EWMA(snr, 10, 4);
15992774f206SBjoern A. Zeeb
16002774f206SBjoern A. Zeeb struct rtw_iqk_info {
16012774f206SBjoern A. Zeeb bool done;
16022774f206SBjoern A. Zeeb struct {
16032774f206SBjoern A. Zeeb u32 s1_x;
16042774f206SBjoern A. Zeeb u32 s1_y;
16052774f206SBjoern A. Zeeb u32 s0_x;
16062774f206SBjoern A. Zeeb u32 s0_y;
16072774f206SBjoern A. Zeeb } result;
16082774f206SBjoern A. Zeeb };
16092774f206SBjoern A. Zeeb
16102774f206SBjoern A. Zeeb enum rtw_rf_band {
16112774f206SBjoern A. Zeeb RF_BAND_2G_CCK,
16122774f206SBjoern A. Zeeb RF_BAND_2G_OFDM,
16132774f206SBjoern A. Zeeb RF_BAND_5G_L,
16142774f206SBjoern A. Zeeb RF_BAND_5G_M,
16152774f206SBjoern A. Zeeb RF_BAND_5G_H,
16162774f206SBjoern A. Zeeb RF_BAND_MAX
16172774f206SBjoern A. Zeeb };
16182774f206SBjoern A. Zeeb
16192774f206SBjoern A. Zeeb #define RF_GAIN_NUM 11
16202774f206SBjoern A. Zeeb #define RF_HW_OFFSET_NUM 10
16212774f206SBjoern A. Zeeb
16222774f206SBjoern A. Zeeb struct rtw_gapk_info {
16232774f206SBjoern A. Zeeb u32 rf3f_bp[RF_BAND_MAX][RF_GAIN_NUM][RTW_RF_PATH_MAX];
16242774f206SBjoern A. Zeeb u32 rf3f_fs[RTW_RF_PATH_MAX][RF_GAIN_NUM];
16252774f206SBjoern A. Zeeb bool txgapk_bp_done;
16262774f206SBjoern A. Zeeb s8 offset[RF_GAIN_NUM][RTW_RF_PATH_MAX];
16272774f206SBjoern A. Zeeb s8 fianl_offset[RF_GAIN_NUM][RTW_RF_PATH_MAX];
16282774f206SBjoern A. Zeeb u8 read_txgain;
16292774f206SBjoern A. Zeeb u8 channel;
16302774f206SBjoern A. Zeeb };
16312774f206SBjoern A. Zeeb
16322774f206SBjoern A. Zeeb #define EDCCA_TH_L2H_IDX 0
16332774f206SBjoern A. Zeeb #define EDCCA_TH_H2L_IDX 1
16342774f206SBjoern A. Zeeb #define EDCCA_TH_L2H_LB 48
16352774f206SBjoern A. Zeeb #define EDCCA_ADC_BACKOFF 12
16362774f206SBjoern A. Zeeb #define EDCCA_IGI_BASE 50
16372774f206SBjoern A. Zeeb #define EDCCA_IGI_L2H_DIFF 8
16382774f206SBjoern A. Zeeb #define EDCCA_L2H_H2L_DIFF 7
16392774f206SBjoern A. Zeeb #define EDCCA_L2H_H2L_DIFF_NORMAL 8
16402774f206SBjoern A. Zeeb
16412774f206SBjoern A. Zeeb enum rtw_edcca_mode {
16422774f206SBjoern A. Zeeb RTW_EDCCA_NORMAL = 0,
16432774f206SBjoern A. Zeeb RTW_EDCCA_ADAPTIVITY = 1,
16442774f206SBjoern A. Zeeb };
16452774f206SBjoern A. Zeeb
16462774f206SBjoern A. Zeeb struct rtw_cfo_track {
16472774f206SBjoern A. Zeeb bool is_adjust;
16482774f206SBjoern A. Zeeb u8 crystal_cap;
16492774f206SBjoern A. Zeeb s32 cfo_tail[RTW_RF_PATH_MAX];
16502774f206SBjoern A. Zeeb s32 cfo_cnt[RTW_RF_PATH_MAX];
16512774f206SBjoern A. Zeeb u32 packet_count;
16522774f206SBjoern A. Zeeb u32 packet_count_pre;
16532774f206SBjoern A. Zeeb };
16542774f206SBjoern A. Zeeb
16552774f206SBjoern A. Zeeb #define RRSR_INIT_2G 0x15f
16562774f206SBjoern A. Zeeb #define RRSR_INIT_5G 0x150
16572774f206SBjoern A. Zeeb
16582774f206SBjoern A. Zeeb enum rtw_dm_cap {
16592774f206SBjoern A. Zeeb RTW_DM_CAP_NA,
16602774f206SBjoern A. Zeeb RTW_DM_CAP_TXGAPK,
16612774f206SBjoern A. Zeeb RTW_DM_CAP_NUM
16622774f206SBjoern A. Zeeb };
16632774f206SBjoern A. Zeeb
16642774f206SBjoern A. Zeeb struct rtw_dm_info {
16652774f206SBjoern A. Zeeb u32 cck_fa_cnt;
16662774f206SBjoern A. Zeeb u32 ofdm_fa_cnt;
16672774f206SBjoern A. Zeeb u32 total_fa_cnt;
16682774f206SBjoern A. Zeeb u32 cck_cca_cnt;
16692774f206SBjoern A. Zeeb u32 ofdm_cca_cnt;
16702774f206SBjoern A. Zeeb u32 total_cca_cnt;
16712774f206SBjoern A. Zeeb
16722774f206SBjoern A. Zeeb u32 cck_ok_cnt;
16732774f206SBjoern A. Zeeb u32 cck_err_cnt;
16742774f206SBjoern A. Zeeb u32 ofdm_ok_cnt;
16752774f206SBjoern A. Zeeb u32 ofdm_err_cnt;
16762774f206SBjoern A. Zeeb u32 ht_ok_cnt;
16772774f206SBjoern A. Zeeb u32 ht_err_cnt;
16782774f206SBjoern A. Zeeb u32 vht_ok_cnt;
16792774f206SBjoern A. Zeeb u32 vht_err_cnt;
16802774f206SBjoern A. Zeeb
16812774f206SBjoern A. Zeeb u8 min_rssi;
16822774f206SBjoern A. Zeeb u8 pre_min_rssi;
16832774f206SBjoern A. Zeeb u16 fa_history[4];
16842774f206SBjoern A. Zeeb u8 igi_history[4];
16852774f206SBjoern A. Zeeb u8 igi_bitmap;
16862774f206SBjoern A. Zeeb bool damping;
16872774f206SBjoern A. Zeeb u8 damping_cnt;
16882774f206SBjoern A. Zeeb u8 damping_rssi;
16892774f206SBjoern A. Zeeb
16902774f206SBjoern A. Zeeb u8 cck_gi_u_bnd;
16912774f206SBjoern A. Zeeb u8 cck_gi_l_bnd;
16922774f206SBjoern A. Zeeb
16932774f206SBjoern A. Zeeb u8 fix_rate;
16942774f206SBjoern A. Zeeb u8 tx_rate;
16952774f206SBjoern A. Zeeb u32 rrsr_val_init;
16962774f206SBjoern A. Zeeb u32 rrsr_mask_min;
16972774f206SBjoern A. Zeeb u8 thermal_avg[RTW_RF_PATH_MAX];
16982774f206SBjoern A. Zeeb u8 thermal_meter_k;
16992774f206SBjoern A. Zeeb u8 thermal_meter_lck;
17002774f206SBjoern A. Zeeb s8 delta_power_index[RTW_RF_PATH_MAX];
17012774f206SBjoern A. Zeeb s8 delta_power_index_last[RTW_RF_PATH_MAX];
17022774f206SBjoern A. Zeeb u8 default_ofdm_index;
17032774f206SBjoern A. Zeeb bool pwr_trk_triggered;
17042774f206SBjoern A. Zeeb bool pwr_trk_init_trigger;
17052774f206SBjoern A. Zeeb struct ewma_thermal avg_thermal[RTW_RF_PATH_MAX];
17062774f206SBjoern A. Zeeb s8 txagc_remnant_cck;
17072774f206SBjoern A. Zeeb s8 txagc_remnant_ofdm;
17082774f206SBjoern A. Zeeb
17092774f206SBjoern A. Zeeb /* backup dack results for each path and I/Q */
17102774f206SBjoern A. Zeeb u32 dack_adck[RTW_RF_PATH_MAX];
17112774f206SBjoern A. Zeeb u16 dack_msbk[RTW_RF_PATH_MAX][2][DACK_MSBK_BACKUP_NUM];
17122774f206SBjoern A. Zeeb u8 dack_dck[RTW_RF_PATH_MAX][2][DACK_DCK_BACKUP_NUM];
17132774f206SBjoern A. Zeeb
17142774f206SBjoern A. Zeeb struct rtw_dpk_info dpk_info;
17152774f206SBjoern A. Zeeb struct rtw_cfo_track cfo_track;
17162774f206SBjoern A. Zeeb
17172774f206SBjoern A. Zeeb /* [bandwidth 0:20M/1:40M][number of path] */
17182774f206SBjoern A. Zeeb u8 cck_pd_lv[2][RTW_RF_PATH_MAX];
17192774f206SBjoern A. Zeeb u32 cck_fa_avg;
17202774f206SBjoern A. Zeeb u8 cck_pd_default;
17212774f206SBjoern A. Zeeb
17222774f206SBjoern A. Zeeb /* save the last rx phy status for debug */
17232774f206SBjoern A. Zeeb s8 rx_snr[RTW_RF_PATH_MAX];
17242774f206SBjoern A. Zeeb u8 rx_evm_dbm[RTW_RF_PATH_MAX];
17252774f206SBjoern A. Zeeb s16 cfo_tail[RTW_RF_PATH_MAX];
17262774f206SBjoern A. Zeeb u8 rssi[RTW_RF_PATH_MAX];
17272774f206SBjoern A. Zeeb u8 curr_rx_rate;
17282774f206SBjoern A. Zeeb struct rtw_pkt_count cur_pkt_count;
17292774f206SBjoern A. Zeeb struct rtw_pkt_count last_pkt_count;
17302774f206SBjoern A. Zeeb struct ewma_evm ewma_evm[RTW_EVM_NUM];
17312774f206SBjoern A. Zeeb struct ewma_snr ewma_snr[RTW_SNR_NUM];
17322774f206SBjoern A. Zeeb
17332774f206SBjoern A. Zeeb u32 dm_flags; /* enum rtw_dm_cap */
17342774f206SBjoern A. Zeeb struct rtw_iqk_info iqk;
17352774f206SBjoern A. Zeeb struct rtw_gapk_info gapk;
17362774f206SBjoern A. Zeeb bool is_bt_iqk_timeout;
17372774f206SBjoern A. Zeeb
17382774f206SBjoern A. Zeeb s8 l2h_th_ini;
17392774f206SBjoern A. Zeeb enum rtw_edcca_mode edcca_mode;
17402774f206SBjoern A. Zeeb u8 scan_density;
17412774f206SBjoern A. Zeeb };
17422774f206SBjoern A. Zeeb
17432774f206SBjoern A. Zeeb struct rtw_efuse {
17442774f206SBjoern A. Zeeb u32 size;
17452774f206SBjoern A. Zeeb u32 physical_size;
17462774f206SBjoern A. Zeeb u32 logical_size;
17472774f206SBjoern A. Zeeb u32 protect_size;
17482774f206SBjoern A. Zeeb
17492774f206SBjoern A. Zeeb u8 addr[ETH_ALEN];
17502774f206SBjoern A. Zeeb u8 channel_plan;
17512774f206SBjoern A. Zeeb u8 country_code[2];
17522774f206SBjoern A. Zeeb u8 rf_board_option;
17532774f206SBjoern A. Zeeb u8 rfe_option;
17542774f206SBjoern A. Zeeb u8 power_track_type;
17552774f206SBjoern A. Zeeb u8 thermal_meter[RTW_RF_PATH_MAX];
17562774f206SBjoern A. Zeeb u8 thermal_meter_k;
17572774f206SBjoern A. Zeeb u8 crystal_cap;
17582774f206SBjoern A. Zeeb u8 ant_div_cfg;
17592774f206SBjoern A. Zeeb u8 ant_div_type;
17602774f206SBjoern A. Zeeb u8 regd;
17612774f206SBjoern A. Zeeb u8 afe;
17622774f206SBjoern A. Zeeb
17632774f206SBjoern A. Zeeb u8 lna_type_2g;
17642774f206SBjoern A. Zeeb u8 lna_type_5g;
17652774f206SBjoern A. Zeeb u8 glna_type;
17662774f206SBjoern A. Zeeb u8 alna_type;
17672774f206SBjoern A. Zeeb bool ext_lna_2g;
17682774f206SBjoern A. Zeeb bool ext_lna_5g;
17692774f206SBjoern A. Zeeb u8 pa_type_2g;
17702774f206SBjoern A. Zeeb u8 pa_type_5g;
17712774f206SBjoern A. Zeeb u8 gpa_type;
17722774f206SBjoern A. Zeeb u8 apa_type;
17732774f206SBjoern A. Zeeb bool ext_pa_2g;
17742774f206SBjoern A. Zeeb bool ext_pa_5g;
17752774f206SBjoern A. Zeeb u8 tx_bb_swing_setting_2g;
17762774f206SBjoern A. Zeeb u8 tx_bb_swing_setting_5g;
17772774f206SBjoern A. Zeeb
17782774f206SBjoern A. Zeeb bool btcoex;
17792774f206SBjoern A. Zeeb /* bt share antenna with wifi */
17802774f206SBjoern A. Zeeb bool share_ant;
17812774f206SBjoern A. Zeeb u8 bt_setting;
17822774f206SBjoern A. Zeeb
17832774f206SBjoern A. Zeeb struct {
17842774f206SBjoern A. Zeeb u8 hci;
17852774f206SBjoern A. Zeeb u8 bw;
17862774f206SBjoern A. Zeeb u8 ptcl;
17872774f206SBjoern A. Zeeb u8 nss;
17882774f206SBjoern A. Zeeb u8 ant_num;
17892774f206SBjoern A. Zeeb } hw_cap;
17902774f206SBjoern A. Zeeb
17912774f206SBjoern A. Zeeb struct rtw_txpwr_idx txpwr_idx_table[4];
17922774f206SBjoern A. Zeeb };
17932774f206SBjoern A. Zeeb
17942774f206SBjoern A. Zeeb struct rtw_phy_cond {
17952774f206SBjoern A. Zeeb #ifdef __LITTLE_ENDIAN
17962774f206SBjoern A. Zeeb u32 rfe:8;
17972774f206SBjoern A. Zeeb u32 intf:4;
17982774f206SBjoern A. Zeeb u32 pkg:4;
17992774f206SBjoern A. Zeeb u32 plat:4;
18002774f206SBjoern A. Zeeb u32 intf_rsvd:4;
18012774f206SBjoern A. Zeeb u32 cut:4;
18022774f206SBjoern A. Zeeb u32 branch:2;
18032774f206SBjoern A. Zeeb u32 neg:1;
18042774f206SBjoern A. Zeeb u32 pos:1;
18052774f206SBjoern A. Zeeb #else
18062774f206SBjoern A. Zeeb u32 pos:1;
18072774f206SBjoern A. Zeeb u32 neg:1;
18082774f206SBjoern A. Zeeb u32 branch:2;
18092774f206SBjoern A. Zeeb u32 cut:4;
18102774f206SBjoern A. Zeeb u32 intf_rsvd:4;
18112774f206SBjoern A. Zeeb u32 plat:4;
18122774f206SBjoern A. Zeeb u32 pkg:4;
18132774f206SBjoern A. Zeeb u32 intf:4;
18142774f206SBjoern A. Zeeb u32 rfe:8;
18152774f206SBjoern A. Zeeb #endif
18162774f206SBjoern A. Zeeb /* for intf:4 */
18172774f206SBjoern A. Zeeb #define INTF_PCIE BIT(0)
18182774f206SBjoern A. Zeeb #define INTF_USB BIT(1)
18192774f206SBjoern A. Zeeb #define INTF_SDIO BIT(2)
18202774f206SBjoern A. Zeeb /* for branch:2 */
18212774f206SBjoern A. Zeeb #define BRANCH_IF 0
18222774f206SBjoern A. Zeeb #define BRANCH_ELIF 1
18232774f206SBjoern A. Zeeb #define BRANCH_ELSE 2
18242774f206SBjoern A. Zeeb #define BRANCH_ENDIF 3
18252774f206SBjoern A. Zeeb };
18262774f206SBjoern A. Zeeb
18272774f206SBjoern A. Zeeb struct rtw_fifo_conf {
18282774f206SBjoern A. Zeeb /* tx fifo information */
18292774f206SBjoern A. Zeeb u16 rsvd_boundary;
18302774f206SBjoern A. Zeeb u16 rsvd_pg_num;
18312774f206SBjoern A. Zeeb u16 rsvd_drv_pg_num;
18322774f206SBjoern A. Zeeb u16 txff_pg_num;
18332774f206SBjoern A. Zeeb u16 acq_pg_num;
18342774f206SBjoern A. Zeeb u16 rsvd_drv_addr;
18352774f206SBjoern A. Zeeb u16 rsvd_h2c_info_addr;
18362774f206SBjoern A. Zeeb u16 rsvd_h2c_sta_info_addr;
18372774f206SBjoern A. Zeeb u16 rsvd_h2cq_addr;
18382774f206SBjoern A. Zeeb u16 rsvd_cpu_instr_addr;
18392774f206SBjoern A. Zeeb u16 rsvd_fw_txbuf_addr;
18402774f206SBjoern A. Zeeb u16 rsvd_csibuf_addr;
18412774f206SBjoern A. Zeeb const struct rtw_rqpn *rqpn;
18422774f206SBjoern A. Zeeb };
18432774f206SBjoern A. Zeeb
18442774f206SBjoern A. Zeeb struct rtw_fwcd_desc {
18452774f206SBjoern A. Zeeb u32 size;
18462774f206SBjoern A. Zeeb u8 *next;
18472774f206SBjoern A. Zeeb u8 *data;
18482774f206SBjoern A. Zeeb };
18492774f206SBjoern A. Zeeb
18502774f206SBjoern A. Zeeb struct rtw_fwcd_segs {
18512774f206SBjoern A. Zeeb const u32 *segs;
18522774f206SBjoern A. Zeeb u8 num;
18532774f206SBjoern A. Zeeb };
18542774f206SBjoern A. Zeeb
18552774f206SBjoern A. Zeeb #define FW_CD_TYPE 0xffff
18562774f206SBjoern A. Zeeb #define FW_CD_LEN 4
18572774f206SBjoern A. Zeeb #define FW_CD_VAL 0xaabbccdd
18582774f206SBjoern A. Zeeb struct rtw_fw_state {
18592774f206SBjoern A. Zeeb const struct firmware *firmware;
18602774f206SBjoern A. Zeeb struct rtw_dev *rtwdev;
18612774f206SBjoern A. Zeeb struct completion completion;
18622774f206SBjoern A. Zeeb struct rtw_fwcd_desc fwcd_desc;
18632774f206SBjoern A. Zeeb u16 version;
18642774f206SBjoern A. Zeeb u8 sub_version;
18652774f206SBjoern A. Zeeb u8 sub_index;
18662774f206SBjoern A. Zeeb u16 h2c_version;
18672774f206SBjoern A. Zeeb u32 feature;
186890aac0d8SBjoern A. Zeeb u32 feature_ext;
186990aac0d8SBjoern A. Zeeb enum rtw_fw_type type;
18702774f206SBjoern A. Zeeb };
18712774f206SBjoern A. Zeeb
18722774f206SBjoern A. Zeeb enum rtw_sar_sources {
18732774f206SBjoern A. Zeeb RTW_SAR_SOURCE_NONE,
18742774f206SBjoern A. Zeeb RTW_SAR_SOURCE_COMMON,
18752774f206SBjoern A. Zeeb };
18762774f206SBjoern A. Zeeb
18772774f206SBjoern A. Zeeb enum rtw_sar_bands {
18782774f206SBjoern A. Zeeb RTW_SAR_BAND_0,
18792774f206SBjoern A. Zeeb RTW_SAR_BAND_1,
18802774f206SBjoern A. Zeeb /* RTW_SAR_BAND_2, not used now */
18812774f206SBjoern A. Zeeb RTW_SAR_BAND_3,
18822774f206SBjoern A. Zeeb RTW_SAR_BAND_4,
18832774f206SBjoern A. Zeeb
18842774f206SBjoern A. Zeeb RTW_SAR_BAND_NR,
18852774f206SBjoern A. Zeeb };
18862774f206SBjoern A. Zeeb
188790aac0d8SBjoern A. Zeeb /* the union is reserved for other kinds of SAR sources
18882774f206SBjoern A. Zeeb * which might not re-use same format with array common.
18892774f206SBjoern A. Zeeb */
18902774f206SBjoern A. Zeeb union rtw_sar_cfg {
18912774f206SBjoern A. Zeeb s8 common[RTW_SAR_BAND_NR];
18922774f206SBjoern A. Zeeb };
18932774f206SBjoern A. Zeeb
18942774f206SBjoern A. Zeeb struct rtw_sar {
18952774f206SBjoern A. Zeeb enum rtw_sar_sources src;
18962774f206SBjoern A. Zeeb union rtw_sar_cfg cfg[RTW_RF_PATH_MAX][RTW_RATE_SECTION_MAX];
18972774f206SBjoern A. Zeeb };
18982774f206SBjoern A. Zeeb
18992774f206SBjoern A. Zeeb struct rtw_hal {
19002774f206SBjoern A. Zeeb u32 rcr;
19012774f206SBjoern A. Zeeb
19022774f206SBjoern A. Zeeb u32 chip_version;
19032774f206SBjoern A. Zeeb u8 cut_version;
19042774f206SBjoern A. Zeeb u8 mp_chip;
19052774f206SBjoern A. Zeeb u8 oem_id;
190690aac0d8SBjoern A. Zeeb u8 pkg_type;
19072774f206SBjoern A. Zeeb struct rtw_phy_cond phy_cond;
190890aac0d8SBjoern A. Zeeb bool rfe_btg;
19092774f206SBjoern A. Zeeb
19102774f206SBjoern A. Zeeb u8 ps_mode;
19112774f206SBjoern A. Zeeb u8 current_channel;
19122774f206SBjoern A. Zeeb u8 current_primary_channel_index;
19132774f206SBjoern A. Zeeb u8 current_band_width;
19142774f206SBjoern A. Zeeb u8 current_band_type;
191590aac0d8SBjoern A. Zeeb u8 primary_channel;
19162774f206SBjoern A. Zeeb
19172774f206SBjoern A. Zeeb /* center channel for different available bandwidth,
19182774f206SBjoern A. Zeeb * val of (bw > current_band_width) is invalid
19192774f206SBjoern A. Zeeb */
19202774f206SBjoern A. Zeeb u8 cch_by_bw[RTW_MAX_CHANNEL_WIDTH + 1];
19212774f206SBjoern A. Zeeb
19222774f206SBjoern A. Zeeb u8 sec_ch_offset;
19232774f206SBjoern A. Zeeb u8 rf_type;
19242774f206SBjoern A. Zeeb u8 rf_path_num;
19252774f206SBjoern A. Zeeb u8 rf_phy_num;
19262774f206SBjoern A. Zeeb u32 antenna_tx;
19272774f206SBjoern A. Zeeb u32 antenna_rx;
19282774f206SBjoern A. Zeeb u8 bfee_sts_cap;
19299c951734SBjoern A. Zeeb bool txrx_1ss;
19302774f206SBjoern A. Zeeb
19312774f206SBjoern A. Zeeb /* protect tx power section */
19322774f206SBjoern A. Zeeb struct mutex tx_power_mutex;
19332774f206SBjoern A. Zeeb s8 tx_pwr_by_rate_offset_2g[RTW_RF_PATH_MAX]
19342774f206SBjoern A. Zeeb [DESC_RATE_MAX];
19352774f206SBjoern A. Zeeb s8 tx_pwr_by_rate_offset_5g[RTW_RF_PATH_MAX]
19362774f206SBjoern A. Zeeb [DESC_RATE_MAX];
19372774f206SBjoern A. Zeeb s8 tx_pwr_by_rate_base_2g[RTW_RF_PATH_MAX]
19382774f206SBjoern A. Zeeb [RTW_RATE_SECTION_MAX];
19392774f206SBjoern A. Zeeb s8 tx_pwr_by_rate_base_5g[RTW_RF_PATH_MAX]
19402774f206SBjoern A. Zeeb [RTW_RATE_SECTION_MAX];
19412774f206SBjoern A. Zeeb s8 tx_pwr_limit_2g[RTW_REGD_MAX]
19422774f206SBjoern A. Zeeb [RTW_CHANNEL_WIDTH_MAX]
19432774f206SBjoern A. Zeeb [RTW_RATE_SECTION_MAX]
19442774f206SBjoern A. Zeeb [RTW_MAX_CHANNEL_NUM_2G];
19452774f206SBjoern A. Zeeb s8 tx_pwr_limit_5g[RTW_REGD_MAX]
19462774f206SBjoern A. Zeeb [RTW_CHANNEL_WIDTH_MAX]
19472774f206SBjoern A. Zeeb [RTW_RATE_SECTION_MAX]
19482774f206SBjoern A. Zeeb [RTW_MAX_CHANNEL_NUM_5G];
19492774f206SBjoern A. Zeeb s8 tx_pwr_tbl[RTW_RF_PATH_MAX]
19502774f206SBjoern A. Zeeb [DESC_RATE_MAX];
19512774f206SBjoern A. Zeeb
19522774f206SBjoern A. Zeeb enum rtw_sar_bands sar_band;
19532774f206SBjoern A. Zeeb struct rtw_sar sar;
19549c951734SBjoern A. Zeeb
19559c951734SBjoern A. Zeeb /* for 8821c set channel */
19569c951734SBjoern A. Zeeb u32 ch_param[3];
19572774f206SBjoern A. Zeeb };
19582774f206SBjoern A. Zeeb
19592774f206SBjoern A. Zeeb struct rtw_path_div {
19602774f206SBjoern A. Zeeb enum rtw_bb_path current_tx_path;
19612774f206SBjoern A. Zeeb u32 path_a_sum;
19622774f206SBjoern A. Zeeb u32 path_b_sum;
19632774f206SBjoern A. Zeeb u16 path_a_cnt;
19642774f206SBjoern A. Zeeb u16 path_b_cnt;
19652774f206SBjoern A. Zeeb };
19662774f206SBjoern A. Zeeb
19672774f206SBjoern A. Zeeb struct rtw_chan_info {
19682774f206SBjoern A. Zeeb int pri_ch_idx;
19692774f206SBjoern A. Zeeb int action_id;
19702774f206SBjoern A. Zeeb int bw;
19712774f206SBjoern A. Zeeb u8 extra_info;
19722774f206SBjoern A. Zeeb u8 channel;
19732774f206SBjoern A. Zeeb u16 timeout;
19742774f206SBjoern A. Zeeb };
19752774f206SBjoern A. Zeeb
19762774f206SBjoern A. Zeeb struct rtw_chan_list {
19772774f206SBjoern A. Zeeb u32 buf_size;
19782774f206SBjoern A. Zeeb u32 ch_num;
19792774f206SBjoern A. Zeeb u32 size;
19802774f206SBjoern A. Zeeb u16 addr;
19812774f206SBjoern A. Zeeb };
19822774f206SBjoern A. Zeeb
19832774f206SBjoern A. Zeeb struct rtw_hw_scan_info {
19842774f206SBjoern A. Zeeb struct ieee80211_vif *scanning_vif;
19852774f206SBjoern A. Zeeb u8 probe_pg_size;
19862774f206SBjoern A. Zeeb u8 op_pri_ch_idx;
198790aac0d8SBjoern A. Zeeb u8 op_pri_ch;
19882774f206SBjoern A. Zeeb u8 op_chan;
19892774f206SBjoern A. Zeeb u8 op_bw;
19902774f206SBjoern A. Zeeb };
19912774f206SBjoern A. Zeeb
19922774f206SBjoern A. Zeeb struct rtw_dev {
19932774f206SBjoern A. Zeeb struct ieee80211_hw *hw;
19942774f206SBjoern A. Zeeb struct device *dev;
19952774f206SBjoern A. Zeeb
19962774f206SBjoern A. Zeeb struct rtw_hci hci;
19972774f206SBjoern A. Zeeb
19982774f206SBjoern A. Zeeb struct rtw_hw_scan_info scan_info;
199990aac0d8SBjoern A. Zeeb const struct rtw_chip_info *chip;
20002774f206SBjoern A. Zeeb struct rtw_hal hal;
20012774f206SBjoern A. Zeeb struct rtw_fifo_conf fifo;
20022774f206SBjoern A. Zeeb struct rtw_fw_state fw;
20032774f206SBjoern A. Zeeb struct rtw_efuse efuse;
20042774f206SBjoern A. Zeeb struct rtw_sec_desc sec;
20052774f206SBjoern A. Zeeb struct rtw_traffic_stats stats;
20062774f206SBjoern A. Zeeb struct rtw_regd regd;
20072774f206SBjoern A. Zeeb struct rtw_bf_info bf_info;
20082774f206SBjoern A. Zeeb
20092774f206SBjoern A. Zeeb struct rtw_dm_info dm_info;
20102774f206SBjoern A. Zeeb struct rtw_coex coex;
20112774f206SBjoern A. Zeeb
20122774f206SBjoern A. Zeeb /* ensures exclusive access from mac80211 callbacks */
20132774f206SBjoern A. Zeeb struct mutex mutex;
20142774f206SBjoern A. Zeeb
20152774f206SBjoern A. Zeeb /* watch dog every 2 sec */
20162774f206SBjoern A. Zeeb struct delayed_work watch_dog_work;
20172774f206SBjoern A. Zeeb u32 watch_dog_cnt;
20182774f206SBjoern A. Zeeb
20192774f206SBjoern A. Zeeb struct list_head rsvd_page_list;
20202774f206SBjoern A. Zeeb
20212774f206SBjoern A. Zeeb /* c2h cmd queue & handler work */
20222774f206SBjoern A. Zeeb struct sk_buff_head c2h_queue;
20232774f206SBjoern A. Zeeb struct work_struct c2h_work;
20249c951734SBjoern A. Zeeb struct work_struct ips_work;
20252774f206SBjoern A. Zeeb struct work_struct fw_recovery_work;
20269c951734SBjoern A. Zeeb struct work_struct update_beacon_work;
20272774f206SBjoern A. Zeeb
20282774f206SBjoern A. Zeeb /* used to protect txqs list */
20292774f206SBjoern A. Zeeb spinlock_t txq_lock;
20302774f206SBjoern A. Zeeb struct list_head txqs;
20312774f206SBjoern A. Zeeb struct workqueue_struct *tx_wq;
20322774f206SBjoern A. Zeeb struct work_struct tx_work;
20332774f206SBjoern A. Zeeb struct work_struct ba_work;
20342774f206SBjoern A. Zeeb
20352774f206SBjoern A. Zeeb struct rtw_tx_report tx_report;
20362774f206SBjoern A. Zeeb
20372774f206SBjoern A. Zeeb struct {
203890aac0d8SBjoern A. Zeeb /* indicate the mail box to use with fw */
20392774f206SBjoern A. Zeeb u8 last_box_num;
20402774f206SBjoern A. Zeeb u32 seq;
20412774f206SBjoern A. Zeeb } h2c;
20422774f206SBjoern A. Zeeb
20432774f206SBjoern A. Zeeb /* lps power state & handler work */
20442774f206SBjoern A. Zeeb struct rtw_lps_conf lps_conf;
20452774f206SBjoern A. Zeeb bool ps_enabled;
20462774f206SBjoern A. Zeeb bool beacon_loss;
20472774f206SBjoern A. Zeeb struct completion lps_leave_check;
20482774f206SBjoern A. Zeeb
20492774f206SBjoern A. Zeeb struct dentry *debugfs;
20502774f206SBjoern A. Zeeb
20512774f206SBjoern A. Zeeb u8 sta_cnt;
20522774f206SBjoern A. Zeeb u32 rts_threshold;
20532774f206SBjoern A. Zeeb
205490aac0d8SBjoern A. Zeeb DECLARE_BITMAP(hw_port, RTW_PORT_NUM);
20552774f206SBjoern A. Zeeb DECLARE_BITMAP(mac_id_map, RTW_MAX_MAC_ID_NUM);
20562774f206SBjoern A. Zeeb DECLARE_BITMAP(flags, NUM_OF_RTW_FLAGS);
20572774f206SBjoern A. Zeeb
20582774f206SBjoern A. Zeeb u8 mp_mode;
20592774f206SBjoern A. Zeeb struct rtw_path_div dm_path_div;
20602774f206SBjoern A. Zeeb
20612774f206SBjoern A. Zeeb struct rtw_fw_state wow_fw;
20622774f206SBjoern A. Zeeb struct rtw_wow_param wow;
20632774f206SBjoern A. Zeeb
20642774f206SBjoern A. Zeeb bool need_rfk;
20652774f206SBjoern A. Zeeb struct completion fw_scan_density;
206690aac0d8SBjoern A. Zeeb bool ap_active;
20672774f206SBjoern A. Zeeb
20682774f206SBjoern A. Zeeb /* hci related data, must be last */
20692774f206SBjoern A. Zeeb u8 priv[] __aligned(sizeof(void *));
20702774f206SBjoern A. Zeeb };
20712774f206SBjoern A. Zeeb
20722774f206SBjoern A. Zeeb #include "hci.h"
20732774f206SBjoern A. Zeeb
rtw_is_assoc(struct rtw_dev * rtwdev)20742774f206SBjoern A. Zeeb static inline bool rtw_is_assoc(struct rtw_dev *rtwdev)
20752774f206SBjoern A. Zeeb {
20762774f206SBjoern A. Zeeb return !!rtwdev->sta_cnt;
20772774f206SBjoern A. Zeeb }
20782774f206SBjoern A. Zeeb
rtwtxq_to_txq(struct rtw_txq * rtwtxq)20792774f206SBjoern A. Zeeb static inline struct ieee80211_txq *rtwtxq_to_txq(struct rtw_txq *rtwtxq)
20802774f206SBjoern A. Zeeb {
20812774f206SBjoern A. Zeeb void *p = rtwtxq;
20822774f206SBjoern A. Zeeb
20832774f206SBjoern A. Zeeb return container_of(p, struct ieee80211_txq, drv_priv);
20842774f206SBjoern A. Zeeb }
20852774f206SBjoern A. Zeeb
rtwvif_to_vif(struct rtw_vif * rtwvif)20862774f206SBjoern A. Zeeb static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw_vif *rtwvif)
20872774f206SBjoern A. Zeeb {
20882774f206SBjoern A. Zeeb void *p = rtwvif;
20892774f206SBjoern A. Zeeb
20902774f206SBjoern A. Zeeb return container_of(p, struct ieee80211_vif, drv_priv);
20912774f206SBjoern A. Zeeb }
20922774f206SBjoern A. Zeeb
rtw_ssid_equal(struct cfg80211_ssid * a,struct cfg80211_ssid * b)20932774f206SBjoern A. Zeeb static inline bool rtw_ssid_equal(struct cfg80211_ssid *a,
20942774f206SBjoern A. Zeeb struct cfg80211_ssid *b)
20952774f206SBjoern A. Zeeb {
20962774f206SBjoern A. Zeeb if (!a || !b || a->ssid_len != b->ssid_len)
20972774f206SBjoern A. Zeeb return false;
20982774f206SBjoern A. Zeeb
20992774f206SBjoern A. Zeeb if (memcmp(a->ssid, b->ssid, a->ssid_len))
21002774f206SBjoern A. Zeeb return false;
21012774f206SBjoern A. Zeeb
21022774f206SBjoern A. Zeeb return true;
21032774f206SBjoern A. Zeeb }
21042774f206SBjoern A. Zeeb
rtw_chip_efuse_grant_on(struct rtw_dev * rtwdev)21052774f206SBjoern A. Zeeb static inline void rtw_chip_efuse_grant_on(struct rtw_dev *rtwdev)
21062774f206SBjoern A. Zeeb {
21072774f206SBjoern A. Zeeb if (rtwdev->chip->ops->efuse_grant)
21082774f206SBjoern A. Zeeb rtwdev->chip->ops->efuse_grant(rtwdev, true);
21092774f206SBjoern A. Zeeb }
21102774f206SBjoern A. Zeeb
rtw_chip_efuse_grant_off(struct rtw_dev * rtwdev)21112774f206SBjoern A. Zeeb static inline void rtw_chip_efuse_grant_off(struct rtw_dev *rtwdev)
21122774f206SBjoern A. Zeeb {
21132774f206SBjoern A. Zeeb if (rtwdev->chip->ops->efuse_grant)
21142774f206SBjoern A. Zeeb rtwdev->chip->ops->efuse_grant(rtwdev, false);
21152774f206SBjoern A. Zeeb }
21162774f206SBjoern A. Zeeb
rtw_chip_wcpu_11n(struct rtw_dev * rtwdev)21172774f206SBjoern A. Zeeb static inline bool rtw_chip_wcpu_11n(struct rtw_dev *rtwdev)
21182774f206SBjoern A. Zeeb {
21192774f206SBjoern A. Zeeb return rtwdev->chip->wlan_cpu == RTW_WCPU_11N;
21202774f206SBjoern A. Zeeb }
21212774f206SBjoern A. Zeeb
rtw_chip_wcpu_11ac(struct rtw_dev * rtwdev)21222774f206SBjoern A. Zeeb static inline bool rtw_chip_wcpu_11ac(struct rtw_dev *rtwdev)
21232774f206SBjoern A. Zeeb {
21242774f206SBjoern A. Zeeb return rtwdev->chip->wlan_cpu == RTW_WCPU_11AC;
21252774f206SBjoern A. Zeeb }
21262774f206SBjoern A. Zeeb
rtw_chip_has_rx_ldpc(struct rtw_dev * rtwdev)21272774f206SBjoern A. Zeeb static inline bool rtw_chip_has_rx_ldpc(struct rtw_dev *rtwdev)
21282774f206SBjoern A. Zeeb {
21292774f206SBjoern A. Zeeb return rtwdev->chip->rx_ldpc;
21302774f206SBjoern A. Zeeb }
21312774f206SBjoern A. Zeeb
rtw_chip_has_tx_stbc(struct rtw_dev * rtwdev)21322774f206SBjoern A. Zeeb static inline bool rtw_chip_has_tx_stbc(struct rtw_dev *rtwdev)
21332774f206SBjoern A. Zeeb {
21342774f206SBjoern A. Zeeb return rtwdev->chip->tx_stbc;
21352774f206SBjoern A. Zeeb }
21362774f206SBjoern A. Zeeb
rtw_release_macid(struct rtw_dev * rtwdev,u8 mac_id)21372774f206SBjoern A. Zeeb static inline void rtw_release_macid(struct rtw_dev *rtwdev, u8 mac_id)
21382774f206SBjoern A. Zeeb {
21392774f206SBjoern A. Zeeb clear_bit(mac_id, rtwdev->mac_id_map);
21402774f206SBjoern A. Zeeb }
21412774f206SBjoern A. Zeeb
rtw_chip_dump_fw_crash(struct rtw_dev * rtwdev)21422774f206SBjoern A. Zeeb static inline int rtw_chip_dump_fw_crash(struct rtw_dev *rtwdev)
21432774f206SBjoern A. Zeeb {
21442774f206SBjoern A. Zeeb if (rtwdev->chip->ops->dump_fw_crash)
21452774f206SBjoern A. Zeeb return rtwdev->chip->ops->dump_fw_crash(rtwdev);
21462774f206SBjoern A. Zeeb
21472774f206SBjoern A. Zeeb return 0;
21482774f206SBjoern A. Zeeb }
21492774f206SBjoern A. Zeeb
215090aac0d8SBjoern A. Zeeb static inline
rtw_hw_to_nl80211_band(enum rtw_supported_band hw_band)215190aac0d8SBjoern A. Zeeb enum nl80211_band rtw_hw_to_nl80211_band(enum rtw_supported_band hw_band)
215290aac0d8SBjoern A. Zeeb {
215390aac0d8SBjoern A. Zeeb switch (hw_band) {
215490aac0d8SBjoern A. Zeeb default:
215590aac0d8SBjoern A. Zeeb case RTW_BAND_2G:
215690aac0d8SBjoern A. Zeeb return NL80211_BAND_2GHZ;
215790aac0d8SBjoern A. Zeeb case RTW_BAND_5G:
215890aac0d8SBjoern A. Zeeb return NL80211_BAND_5GHZ;
215990aac0d8SBjoern A. Zeeb case RTW_BAND_60G:
216090aac0d8SBjoern A. Zeeb return NL80211_BAND_60GHZ;
216190aac0d8SBjoern A. Zeeb }
216290aac0d8SBjoern A. Zeeb }
216390aac0d8SBjoern A. Zeeb
21642774f206SBjoern A. Zeeb void rtw_set_rx_freq_band(struct rtw_rx_pkt_stat *pkt_stat, u8 channel);
21659c951734SBjoern A. Zeeb void rtw_set_dtim_period(struct rtw_dev *rtwdev, int dtim_period);
21662774f206SBjoern A. Zeeb void rtw_get_channel_params(struct cfg80211_chan_def *chandef,
21672774f206SBjoern A. Zeeb struct rtw_channel_params *ch_param);
21682774f206SBjoern A. Zeeb bool check_hw_ready(struct rtw_dev *rtwdev, u32 addr, u32 mask, u32 target);
21692774f206SBjoern A. Zeeb bool ltecoex_read_reg(struct rtw_dev *rtwdev, u16 offset, u32 *val);
21702774f206SBjoern A. Zeeb bool ltecoex_reg_write(struct rtw_dev *rtwdev, u16 offset, u32 value);
21712774f206SBjoern A. Zeeb void rtw_restore_reg(struct rtw_dev *rtwdev,
21722774f206SBjoern A. Zeeb struct rtw_backup_info *bckp, u32 num);
21732774f206SBjoern A. Zeeb void rtw_desc_to_mcsrate(u16 rate, u8 *mcs, u8 *nss);
21742774f206SBjoern A. Zeeb void rtw_set_channel(struct rtw_dev *rtwdev);
21752774f206SBjoern A. Zeeb void rtw_chip_prepare_tx(struct rtw_dev *rtwdev);
21762774f206SBjoern A. Zeeb void rtw_vif_port_config(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif,
21772774f206SBjoern A. Zeeb u32 config);
21782774f206SBjoern A. Zeeb void rtw_tx_report_purge_timer(struct timer_list *t);
21799c951734SBjoern A. Zeeb void rtw_update_sta_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si,
21809c951734SBjoern A. Zeeb bool reset_ra_mask);
21812774f206SBjoern A. Zeeb void rtw_core_scan_start(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif,
21822774f206SBjoern A. Zeeb const u8 *mac_addr, bool hw_scan);
21839c951734SBjoern A. Zeeb void rtw_core_scan_complete(struct rtw_dev *rtwdev, struct ieee80211_vif *vif,
21849c951734SBjoern A. Zeeb bool hw_scan);
21852774f206SBjoern A. Zeeb int rtw_core_start(struct rtw_dev *rtwdev);
21862774f206SBjoern A. Zeeb void rtw_core_stop(struct rtw_dev *rtwdev);
21872774f206SBjoern A. Zeeb int rtw_chip_info_setup(struct rtw_dev *rtwdev);
21882774f206SBjoern A. Zeeb int rtw_core_init(struct rtw_dev *rtwdev);
21892774f206SBjoern A. Zeeb void rtw_core_deinit(struct rtw_dev *rtwdev);
21902774f206SBjoern A. Zeeb int rtw_register_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw);
21912774f206SBjoern A. Zeeb void rtw_unregister_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw);
21922774f206SBjoern A. Zeeb u16 rtw_desc_to_bitrate(u8 desc_rate);
21932774f206SBjoern A. Zeeb void rtw_vif_assoc_changed(struct rtw_vif *rtwvif,
21942774f206SBjoern A. Zeeb struct ieee80211_bss_conf *conf);
21952774f206SBjoern A. Zeeb int rtw_sta_add(struct rtw_dev *rtwdev, struct ieee80211_sta *sta,
21962774f206SBjoern A. Zeeb struct ieee80211_vif *vif);
21972774f206SBjoern A. Zeeb void rtw_sta_remove(struct rtw_dev *rtwdev, struct ieee80211_sta *sta,
21982774f206SBjoern A. Zeeb bool fw_exist);
21992774f206SBjoern A. Zeeb void rtw_fw_recovery(struct rtw_dev *rtwdev);
22002774f206SBjoern A. Zeeb void rtw_core_fw_scan_notify(struct rtw_dev *rtwdev, bool start);
22012774f206SBjoern A. Zeeb int rtw_dump_fw(struct rtw_dev *rtwdev, const u32 ocp_src, u32 size,
22022774f206SBjoern A. Zeeb u32 fwcd_item);
22032774f206SBjoern A. Zeeb int rtw_dump_reg(struct rtw_dev *rtwdev, const u32 addr, const u32 size);
22049c951734SBjoern A. Zeeb void rtw_set_txrx_1ss(struct rtw_dev *rtwdev, bool config_1ss);
220590aac0d8SBjoern A. Zeeb void rtw_update_channel(struct rtw_dev *rtwdev, u8 center_channel,
220690aac0d8SBjoern A. Zeeb u8 primary_channel, enum rtw_supported_band band,
220790aac0d8SBjoern A. Zeeb enum rtw_bandwidth bandwidth);
220890aac0d8SBjoern A. Zeeb void rtw_core_port_switch(struct rtw_dev *rtwdev, struct ieee80211_vif *vif);
220990aac0d8SBjoern A. Zeeb bool rtw_core_check_sta_active(struct rtw_dev *rtwdev);
221090aac0d8SBjoern A. Zeeb void rtw_core_enable_beacon(struct rtw_dev *rtwdev, bool enable);
22112774f206SBjoern A. Zeeb #if defined(__linux__)
22122774f206SBjoern A. Zeeb #define rtw88_static_assert(_x) static_assert(_x)
22132774f206SBjoern A. Zeeb #elif defined(__FreeBSD__)
22142774f206SBjoern A. Zeeb #define rtw88_static_assert(_x) _Static_assert(_x, "bad array size")
22152774f206SBjoern A. Zeeb #endif
22162774f206SBjoern A. Zeeb
22172774f206SBjoern A. Zeeb #endif
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