1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/arm/arm,coresight-stm.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Arm CoreSight System Trace MacroCell
8
9maintainers:
10  - Mathieu Poirier <mathieu.poirier@linaro.org>
11  - Mike Leach <mike.leach@linaro.org>
12  - Leo Yan <leo.yan@linaro.org>
13  - Suzuki K Poulose <suzuki.poulose@arm.com>
14
15description: |
16  CoreSight components are compliant with the ARM CoreSight architecture
17  specification and can be connected in various topologies to suit a particular
18  SoCs tracing needs. These trace components can generally be classified as
19  sinks, links and sources. Trace data produced by one or more sources flows
20  through the intermediate links connecting the source to the currently selected
21  sink.
22
23  The STM is a trace source that is integrated into a CoreSight system, designed
24  primarily for high-bandwidth trace of instrumentation embedded into software.
25  This instrumentation is made up of memory-mapped writes to the STM Advanced
26  eXtensible Interface (AXI) slave, which carry information about the behavior
27  of the software.
28
29select:
30  properties:
31    compatible:
32      contains:
33        const: arm,coresight-stm
34  required:
35    - compatible
36
37allOf:
38  - $ref: /schemas/arm/primecell.yaml#
39
40properties:
41  compatible:
42    items:
43      - const: arm,coresight-stm
44      - const: arm,primecell
45
46  reg:
47    maxItems: 2
48
49  reg-names:
50    items:
51      - const: stm-base
52      - const: stm-stimulus-base
53
54  clocks:
55    minItems: 1
56    maxItems: 2
57
58  clock-names:
59    minItems: 1
60    items:
61      - const: apb_pclk
62      - const: atclk
63
64  out-ports:
65    $ref: /schemas/graph.yaml#/properties/ports
66    additionalProperties: false
67
68    properties:
69      port:
70        description: Output connection to the CoreSight Trace bus.
71        $ref: /schemas/graph.yaml#/properties/port
72
73required:
74  - compatible
75  - reg
76  - reg-names
77  - clocks
78  - clock-names
79  - out-ports
80
81unevaluatedProperties: false
82
83examples:
84  - |
85    stm@20100000 {
86        compatible = "arm,coresight-stm", "arm,primecell";
87        reg = <0x20100000 0x1000>,
88              <0x28000000 0x180000>;
89        reg-names = "stm-base", "stm-stimulus-base";
90
91        clocks = <&soc_smc50mhz>;
92        clock-names = "apb_pclk";
93        out-ports {
94            port {
95                stm_out_port: endpoint {
96                    remote-endpoint = <&main_funnel_in_port2>;
97                };
98            };
99        };
100    };
101...
102