1*c66ec88fSEmmanuel Vadot# SPDX-License-Identifier: GPL-2.0 2*c66ec88fSEmmanuel Vadot%YAML 1.2 3*c66ec88fSEmmanuel Vadot--- 4*c66ec88fSEmmanuel Vadot$id: http://devicetree.org/schemas/arm/l2c2x0.yaml# 5*c66ec88fSEmmanuel Vadot$schema: http://devicetree.org/meta-schemas/core.yaml# 6*c66ec88fSEmmanuel Vadot 7*c66ec88fSEmmanuel Vadottitle: ARM L2 Cache Controller 8*c66ec88fSEmmanuel Vadot 9*c66ec88fSEmmanuel Vadotmaintainers: 10*c66ec88fSEmmanuel Vadot - Rob Herring <robh@kernel.org> 11*c66ec88fSEmmanuel Vadot 12*c66ec88fSEmmanuel Vadotdescription: |+ 13*c66ec88fSEmmanuel Vadot ARM cores often have a separate L2C210/L2C220/L2C310 (also known as PL210/ 14*c66ec88fSEmmanuel Vadot PL220/PL310 and variants) based level 2 cache controller. All these various 15*c66ec88fSEmmanuel Vadot implementations of the L2 cache controller have compatible programming 16*c66ec88fSEmmanuel Vadot models (Note 1). Some of the properties that are just prefixed "cache-*" are 17*c66ec88fSEmmanuel Vadot taken from section 3.7.3 of the Devicetree Specification which can be found 18*c66ec88fSEmmanuel Vadot at: 19*c66ec88fSEmmanuel Vadot https://www.devicetree.org/specifications/ 20*c66ec88fSEmmanuel Vadot 21*c66ec88fSEmmanuel Vadot Note 1: The description in this document doesn't apply to integrated L2 22*c66ec88fSEmmanuel Vadot cache controllers as found in e.g. Cortex-A15/A7/A57/A53. These 23*c66ec88fSEmmanuel Vadot integrated L2 controllers are assumed to be all preconfigured by 24*c66ec88fSEmmanuel Vadot early secure boot code. Thus no need to deal with their configuration 25*c66ec88fSEmmanuel Vadot in the kernel at all. 26*c66ec88fSEmmanuel Vadot 27*c66ec88fSEmmanuel VadotallOf: 28*c66ec88fSEmmanuel Vadot - $ref: /schemas/cache-controller.yaml# 29*c66ec88fSEmmanuel Vadot 30*c66ec88fSEmmanuel Vadotproperties: 31*c66ec88fSEmmanuel Vadot compatible: 32*c66ec88fSEmmanuel Vadot oneOf: 33*c66ec88fSEmmanuel Vadot - enum: 34*c66ec88fSEmmanuel Vadot - arm,pl310-cache 35*c66ec88fSEmmanuel Vadot - arm,l220-cache 36*c66ec88fSEmmanuel Vadot - arm,l210-cache 37*c66ec88fSEmmanuel Vadot # DEPRECATED by "brcm,bcm11351-a2-pl310-cache" 38*c66ec88fSEmmanuel Vadot - bcm,bcm11351-a2-pl310-cache 39*c66ec88fSEmmanuel Vadot # For Broadcom bcm11351 chipset where an 40*c66ec88fSEmmanuel Vadot # offset needs to be added to the address before passing down to the L2 41*c66ec88fSEmmanuel Vadot # cache controller 42*c66ec88fSEmmanuel Vadot - brcm,bcm11351-a2-pl310-cache 43*c66ec88fSEmmanuel Vadot # Marvell Controller designed to be 44*c66ec88fSEmmanuel Vadot # compatible with the ARM one, with system cache mode (meaning 45*c66ec88fSEmmanuel Vadot # maintenance operations on L1 are broadcasted to the L2 and L2 46*c66ec88fSEmmanuel Vadot # performs the same operation). 47*c66ec88fSEmmanuel Vadot - marvell,aurora-system-cache 48*c66ec88fSEmmanuel Vadot # Marvell Controller designed to be 49*c66ec88fSEmmanuel Vadot # compatible with the ARM one with outer cache mode. 50*c66ec88fSEmmanuel Vadot - marvell,aurora-outer-cache 51*c66ec88fSEmmanuel Vadot - items: 52*c66ec88fSEmmanuel Vadot # Marvell Tauros3 cache controller, compatible 53*c66ec88fSEmmanuel Vadot # with arm,pl310-cache controller. 54*c66ec88fSEmmanuel Vadot - const: marvell,tauros3-cache 55*c66ec88fSEmmanuel Vadot - const: arm,pl310-cache 56*c66ec88fSEmmanuel Vadot 57*c66ec88fSEmmanuel Vadot cache-level: 58*c66ec88fSEmmanuel Vadot const: 2 59*c66ec88fSEmmanuel Vadot 60*c66ec88fSEmmanuel Vadot cache-unified: true 61*c66ec88fSEmmanuel Vadot cache-size: true 62*c66ec88fSEmmanuel Vadot cache-sets: true 63*c66ec88fSEmmanuel Vadot cache-block-size: true 64*c66ec88fSEmmanuel Vadot cache-line-size: true 65*c66ec88fSEmmanuel Vadot 66*c66ec88fSEmmanuel Vadot reg: 67*c66ec88fSEmmanuel Vadot maxItems: 1 68*c66ec88fSEmmanuel Vadot 69*c66ec88fSEmmanuel Vadot arm,data-latency: 70*c66ec88fSEmmanuel Vadot description: Cycles of latency for Data RAM accesses. Specifies 3 cells of 71*c66ec88fSEmmanuel Vadot read, write and setup latencies. Minimum valid values are 1. Controllers 72*c66ec88fSEmmanuel Vadot without setup latency control should use a value of 0. 73*c66ec88fSEmmanuel Vadot $ref: /schemas/types.yaml#/definitions/uint32-array 74*c66ec88fSEmmanuel Vadot minItems: 2 75*c66ec88fSEmmanuel Vadot maxItems: 3 76*c66ec88fSEmmanuel Vadot items: 77*c66ec88fSEmmanuel Vadot minimum: 0 78*c66ec88fSEmmanuel Vadot maximum: 8 79*c66ec88fSEmmanuel Vadot 80*c66ec88fSEmmanuel Vadot arm,tag-latency: 81*c66ec88fSEmmanuel Vadot description: Cycles of latency for Tag RAM accesses. Specifies 3 cells of 82*c66ec88fSEmmanuel Vadot read, write and setup latencies. Controllers without setup latency control 83*c66ec88fSEmmanuel Vadot should use 0. Controllers without separate read and write Tag RAM latency 84*c66ec88fSEmmanuel Vadot values should only use the first cell. 85*c66ec88fSEmmanuel Vadot $ref: /schemas/types.yaml#/definitions/uint32-array 86*c66ec88fSEmmanuel Vadot minItems: 1 87*c66ec88fSEmmanuel Vadot maxItems: 3 88*c66ec88fSEmmanuel Vadot items: 89*c66ec88fSEmmanuel Vadot minimum: 0 90*c66ec88fSEmmanuel Vadot maximum: 8 91*c66ec88fSEmmanuel Vadot 92*c66ec88fSEmmanuel Vadot arm,dirty-latency: 93*c66ec88fSEmmanuel Vadot description: Cycles of latency for Dirty RAMs. This is a single cell. 94*c66ec88fSEmmanuel Vadot $ref: /schemas/types.yaml#/definitions/uint32 95*c66ec88fSEmmanuel Vadot minimum: 1 96*c66ec88fSEmmanuel Vadot maximum: 8 97*c66ec88fSEmmanuel Vadot 98*c66ec88fSEmmanuel Vadot arm,filter-ranges: 99*c66ec88fSEmmanuel Vadot description: <start length> Starting address and length of window to 100*c66ec88fSEmmanuel Vadot filter. Addresses in the filter window are directed to the M1 port. Other 101*c66ec88fSEmmanuel Vadot addresses will go to the M0 port. 102*c66ec88fSEmmanuel Vadot $ref: /schemas/types.yaml#/definitions/uint32-array 103*c66ec88fSEmmanuel Vadot items: 104*c66ec88fSEmmanuel Vadot minItems: 2 105*c66ec88fSEmmanuel Vadot maxItems: 2 106*c66ec88fSEmmanuel Vadot 107*c66ec88fSEmmanuel Vadot arm,io-coherent: 108*c66ec88fSEmmanuel Vadot description: indicates that the system is operating in an hardware 109*c66ec88fSEmmanuel Vadot I/O coherent mode. Valid only when the arm,pl310-cache compatible 110*c66ec88fSEmmanuel Vadot string is used. 111*c66ec88fSEmmanuel Vadot type: boolean 112*c66ec88fSEmmanuel Vadot 113*c66ec88fSEmmanuel Vadot interrupts: 114*c66ec88fSEmmanuel Vadot # Either a single combined interrupt or up to 9 individual interrupts 115*c66ec88fSEmmanuel Vadot minItems: 1 116*c66ec88fSEmmanuel Vadot maxItems: 9 117*c66ec88fSEmmanuel Vadot 118*c66ec88fSEmmanuel Vadot cache-id-part: 119*c66ec88fSEmmanuel Vadot description: cache id part number to be used if it is not present 120*c66ec88fSEmmanuel Vadot on hardware 121*c66ec88fSEmmanuel Vadot $ref: /schemas/types.yaml#/definitions/uint32 122*c66ec88fSEmmanuel Vadot 123*c66ec88fSEmmanuel Vadot wt-override: 124*c66ec88fSEmmanuel Vadot description: If present then L2 is forced to Write through mode 125*c66ec88fSEmmanuel Vadot type: boolean 126*c66ec88fSEmmanuel Vadot 127*c66ec88fSEmmanuel Vadot arm,double-linefill: 128*c66ec88fSEmmanuel Vadot description: Override double linefill enable setting. Enable if 129*c66ec88fSEmmanuel Vadot non-zero, disable if zero. 130*c66ec88fSEmmanuel Vadot $ref: /schemas/types.yaml#/definitions/uint32 131*c66ec88fSEmmanuel Vadot enum: [0, 1] 132*c66ec88fSEmmanuel Vadot 133*c66ec88fSEmmanuel Vadot arm,double-linefill-incr: 134*c66ec88fSEmmanuel Vadot description: Override double linefill on INCR read. Enable 135*c66ec88fSEmmanuel Vadot if non-zero, disable if zero. 136*c66ec88fSEmmanuel Vadot $ref: /schemas/types.yaml#/definitions/uint32 137*c66ec88fSEmmanuel Vadot enum: [0, 1] 138*c66ec88fSEmmanuel Vadot 139*c66ec88fSEmmanuel Vadot arm,double-linefill-wrap: 140*c66ec88fSEmmanuel Vadot description: Override double linefill on WRAP read. Enable 141*c66ec88fSEmmanuel Vadot if non-zero, disable if zero. 142*c66ec88fSEmmanuel Vadot $ref: /schemas/types.yaml#/definitions/uint32 143*c66ec88fSEmmanuel Vadot enum: [0, 1] 144*c66ec88fSEmmanuel Vadot 145*c66ec88fSEmmanuel Vadot arm,prefetch-drop: 146*c66ec88fSEmmanuel Vadot description: Override prefetch drop enable setting. Enable if non-zero, 147*c66ec88fSEmmanuel Vadot disable if zero. 148*c66ec88fSEmmanuel Vadot $ref: /schemas/types.yaml#/definitions/uint32 149*c66ec88fSEmmanuel Vadot enum: [0, 1] 150*c66ec88fSEmmanuel Vadot 151*c66ec88fSEmmanuel Vadot arm,prefetch-offset: 152*c66ec88fSEmmanuel Vadot description: Override prefetch offset value. 153*c66ec88fSEmmanuel Vadot $ref: /schemas/types.yaml#/definitions/uint32 154*c66ec88fSEmmanuel Vadot enum: [0, 1, 2, 3, 4, 5, 6, 7, 15, 23, 31] 155*c66ec88fSEmmanuel Vadot 156*c66ec88fSEmmanuel Vadot arm,shared-override: 157*c66ec88fSEmmanuel Vadot description: The default behavior of the L220 or PL310 cache 158*c66ec88fSEmmanuel Vadot controllers with respect to the shareable attribute is to transform "normal 159*c66ec88fSEmmanuel Vadot memory non-cacheable transactions" into "cacheable no allocate" (for reads) 160*c66ec88fSEmmanuel Vadot or "write through no write allocate" (for writes). 161*c66ec88fSEmmanuel Vadot On systems where this may cause DMA buffer corruption, this property must 162*c66ec88fSEmmanuel Vadot be specified to indicate that such transforms are precluded. 163*c66ec88fSEmmanuel Vadot type: boolean 164*c66ec88fSEmmanuel Vadot 165*c66ec88fSEmmanuel Vadot arm,parity-enable: 166*c66ec88fSEmmanuel Vadot description: enable parity checking on the L2 cache (L220 or PL310). 167*c66ec88fSEmmanuel Vadot type: boolean 168*c66ec88fSEmmanuel Vadot 169*c66ec88fSEmmanuel Vadot arm,parity-disable: 170*c66ec88fSEmmanuel Vadot description: disable parity checking on the L2 cache (L220 or PL310). 171*c66ec88fSEmmanuel Vadot type: boolean 172*c66ec88fSEmmanuel Vadot 173*c66ec88fSEmmanuel Vadot marvell,ecc-enable: 174*c66ec88fSEmmanuel Vadot description: enable ECC protection on the L2 cache 175*c66ec88fSEmmanuel Vadot type: boolean 176*c66ec88fSEmmanuel Vadot 177*c66ec88fSEmmanuel Vadot arm,outer-sync-disable: 178*c66ec88fSEmmanuel Vadot description: disable the outer sync operation on the L2 cache. 179*c66ec88fSEmmanuel Vadot Some core tiles, especially ARM PB11MPCore have a faulty L220 cache that 180*c66ec88fSEmmanuel Vadot will randomly hang unless outer sync operations are disabled. 181*c66ec88fSEmmanuel Vadot type: boolean 182*c66ec88fSEmmanuel Vadot 183*c66ec88fSEmmanuel Vadot prefetch-data: 184*c66ec88fSEmmanuel Vadot description: | 185*c66ec88fSEmmanuel Vadot Data prefetch. Value: <0> (forcibly disable), <1> 186*c66ec88fSEmmanuel Vadot (forcibly enable), property absent (retain settings set by firmware) 187*c66ec88fSEmmanuel Vadot $ref: /schemas/types.yaml#/definitions/uint32 188*c66ec88fSEmmanuel Vadot enum: [0, 1] 189*c66ec88fSEmmanuel Vadot 190*c66ec88fSEmmanuel Vadot prefetch-instr: 191*c66ec88fSEmmanuel Vadot description: | 192*c66ec88fSEmmanuel Vadot Instruction prefetch. Value: <0> (forcibly disable), 193*c66ec88fSEmmanuel Vadot <1> (forcibly enable), property absent (retain settings set by 194*c66ec88fSEmmanuel Vadot firmware) 195*c66ec88fSEmmanuel Vadot $ref: /schemas/types.yaml#/definitions/uint32 196*c66ec88fSEmmanuel Vadot enum: [0, 1] 197*c66ec88fSEmmanuel Vadot 198*c66ec88fSEmmanuel Vadot arm,dynamic-clock-gating: 199*c66ec88fSEmmanuel Vadot description: | 200*c66ec88fSEmmanuel Vadot L2 dynamic clock gating. Value: <0> (forcibly 201*c66ec88fSEmmanuel Vadot disable), <1> (forcibly enable), property absent (OS specific behavior, 202*c66ec88fSEmmanuel Vadot preferably retain firmware settings) 203*c66ec88fSEmmanuel Vadot $ref: /schemas/types.yaml#/definitions/uint32 204*c66ec88fSEmmanuel Vadot enum: [0, 1] 205*c66ec88fSEmmanuel Vadot 206*c66ec88fSEmmanuel Vadot arm,standby-mode: 207*c66ec88fSEmmanuel Vadot description: L2 standby mode enable. Value <0> (forcibly disable), 208*c66ec88fSEmmanuel Vadot <1> (forcibly enable), property absent (OS specific behavior, 209*c66ec88fSEmmanuel Vadot preferably retain firmware settings) 210*c66ec88fSEmmanuel Vadot $ref: /schemas/types.yaml#/definitions/uint32 211*c66ec88fSEmmanuel Vadot enum: [0, 1] 212*c66ec88fSEmmanuel Vadot 213*c66ec88fSEmmanuel Vadot arm,early-bresp-disable: 214*c66ec88fSEmmanuel Vadot description: Disable the CA9 optimization Early BRESP (PL310) 215*c66ec88fSEmmanuel Vadot type: boolean 216*c66ec88fSEmmanuel Vadot 217*c66ec88fSEmmanuel Vadot arm,full-line-zero-disable: 218*c66ec88fSEmmanuel Vadot description: Disable the CA9 optimization Full line of zero 219*c66ec88fSEmmanuel Vadot write (PL310) 220*c66ec88fSEmmanuel Vadot type: boolean 221*c66ec88fSEmmanuel Vadot 222*c66ec88fSEmmanuel Vadotrequired: 223*c66ec88fSEmmanuel Vadot - compatible 224*c66ec88fSEmmanuel Vadot - cache-unified 225*c66ec88fSEmmanuel Vadot - reg 226*c66ec88fSEmmanuel Vadot 227*c66ec88fSEmmanuel VadotadditionalProperties: false 228*c66ec88fSEmmanuel Vadot 229*c66ec88fSEmmanuel Vadotexamples: 230*c66ec88fSEmmanuel Vadot - | 231*c66ec88fSEmmanuel Vadot cache-controller@fff12000 { 232*c66ec88fSEmmanuel Vadot compatible = "arm,pl310-cache"; 233*c66ec88fSEmmanuel Vadot reg = <0xfff12000 0x1000>; 234*c66ec88fSEmmanuel Vadot arm,data-latency = <1 1 1>; 235*c66ec88fSEmmanuel Vadot arm,tag-latency = <2 2 2>; 236*c66ec88fSEmmanuel Vadot arm,filter-ranges = <0x80000000 0x8000000>; 237*c66ec88fSEmmanuel Vadot cache-unified; 238*c66ec88fSEmmanuel Vadot cache-level = <2>; 239*c66ec88fSEmmanuel Vadot interrupts = <45>; 240*c66ec88fSEmmanuel Vadot }; 241*c66ec88fSEmmanuel Vadot 242*c66ec88fSEmmanuel Vadot... 243