1Mediatek infracfg controller
2============================
3
4The Mediatek infracfg controller provides various clocks and reset
5outputs to the system.
6
7Required Properties:
8
9- compatible: Should be one of:
10	- "mediatek,mt2701-infracfg", "syscon"
11	- "mediatek,mt2712-infracfg", "syscon"
12	- "mediatek,mt6765-infracfg", "syscon"
13	- "mediatek,mt6779-infracfg_ao", "syscon"
14	- "mediatek,mt6797-infracfg", "syscon"
15	- "mediatek,mt7622-infracfg", "syscon"
16	- "mediatek,mt7623-infracfg", "mediatek,mt2701-infracfg", "syscon"
17	- "mediatek,mt7629-infracfg", "syscon"
18	- "mediatek,mt8135-infracfg", "syscon"
19	- "mediatek,mt8167-infracfg", "syscon"
20	- "mediatek,mt8173-infracfg", "syscon"
21	- "mediatek,mt8183-infracfg", "syscon"
22	- "mediatek,mt8516-infracfg", "syscon"
23- #clock-cells: Must be 1
24- #reset-cells: Must be 1
25
26The infracfg controller uses the common clk binding from
27Documentation/devicetree/bindings/clock/clock-bindings.txt
28The available clocks are defined in dt-bindings/clock/mt*-clk.h.
29Also it uses the common reset controller binding from
30Documentation/devicetree/bindings/reset/reset.txt.
31The available reset outputs are defined in
32dt-bindings/reset/mt*-resets.h
33
34Example:
35
36infracfg: power-controller@10001000 {
37	compatible = "mediatek,mt8173-infracfg", "syscon";
38	reg = <0 0x10001000 0 0x1000>;
39	#clock-cells = <1>;
40	#reset-cells = <1>;
41};
42