1MediaTek Serial ATA controller
2
3Required properties:
4 - compatible	   : Must be "mediatek,<chip>-ahci", "mediatek,mtk-ahci".
5		     When using "mediatek,mtk-ahci" compatible strings, you
6		     need SoC specific ones in addition, one of:
7		     - "mediatek,mt7622-ahci"
8 - reg		   : Physical base addresses and length of register sets.
9 - interrupts	   : Interrupt associated with the SATA device.
10 - interrupt-names : Associated name must be: "hostc".
11 - clocks	   : A list of phandle and clock specifier pairs, one for each
12		     entry in clock-names.
13 - clock-names	   : Associated names must be: "ahb", "axi", "asic", "rbc", "pm".
14 - phys		   : A phandle and PHY specifier pair for the PHY port.
15 - phy-names	   : Associated name must be: "sata-phy".
16 - ports-implemented : See ./ahci-platform.txt for details.
17
18Optional properties:
19 - power-domains   : A phandle and power domain specifier pair to the power
20		     domain which is responsible for collapsing and restoring
21		     power to the peripheral.
22 - resets	   : Must contain an entry for each entry in reset-names.
23		     See ../reset/reset.txt for details.
24 - reset-names	   : Associated names must be: "axi", "sw", "reg".
25 - mediatek,phy-mode : A phandle to the system controller, used to enable
26		       SATA function.
27
28Example:
29
30	sata: sata@1a200000 {
31		compatible = "mediatek,mt7622-ahci",
32			     "mediatek,mtk-ahci";
33		reg = <0 0x1a200000 0 0x1100>;
34		interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
35		interrupt-names = "hostc";
36		clocks = <&pciesys CLK_SATA_AHB_EN>,
37			 <&pciesys CLK_SATA_AXI_EN>,
38			 <&pciesys CLK_SATA_ASIC_EN>,
39			 <&pciesys CLK_SATA_RBC_EN>,
40			 <&pciesys CLK_SATA_PM_EN>;
41		clock-names = "ahb", "axi", "asic", "rbc", "pm";
42		phys = <&u3port1 PHY_TYPE_SATA>;
43		phy-names = "sata-phy";
44		ports-implemented = <0x1>;
45		power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
46		resets = <&pciesys MT7622_SATA_AXI_BUS_RST>,
47			 <&pciesys MT7622_SATA_PHY_SW_RST>,
48			 <&pciesys MT7622_SATA_PHY_REG_RST>;
49		reset-names = "axi", "sw", "reg";
50		mediatek,phy-mode = <&pciesys>;
51	};
52