1* Qualcomm AHCI SATA Controller
2
3SATA nodes are defined to describe on-chip Serial ATA controllers.
4Each SATA controller should have its own node.
5
6Required properties:
7- compatible		: compatible list, must contain "generic-ahci"
8- interrupts		: <interrupt mapping for SATA IRQ>
9- reg			: <registers mapping>
10- phys			: Must contain exactly one entry as specified
11			  in phy-bindings.txt
12- phy-names		: Must be "sata-phy"
13
14Required properties for "qcom,ipq806x-ahci" compatible:
15- clocks		: Must contain an entry for each entry in clock-names.
16- clock-names		: Shall be:
17				"slave_iface" - Fabric port AHB clock for SATA
18				"iface" - AHB clock
19				"core" - core clock
20				"rxoob" - RX out-of-band clock
21				"pmalive" - Power Module Alive clock
22- assigned-clocks	: Shall be:
23				SATA_RXOOB_CLK
24				SATA_PMALIVE_CLK
25- assigned-clock-rates	: Shall be:
26				100Mhz (100000000) for SATA_RXOOB_CLK
27				100Mhz (100000000) for SATA_PMALIVE_CLK
28
29Example:
30	sata@29000000 {
31		compatible = "qcom,ipq806x-ahci", "generic-ahci";
32		reg = <0x29000000 0x180>;
33
34		interrupts = <0 209 0x0>;
35
36		clocks = <&gcc SFAB_SATA_S_H_CLK>,
37			 <&gcc SATA_H_CLK>,
38			 <&gcc SATA_A_CLK>,
39			 <&gcc SATA_RXOOB_CLK>,
40			 <&gcc SATA_PMALIVE_CLK>;
41		clock-names = "slave_iface", "iface", "core",
42				"rxoob", "pmalive";
43		assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>;
44		assigned-clock-rates = <100000000>, <100000000>;
45
46		phys = <&sata_phy>;
47		phy-names = "sata-phy";
48	};
49