1d5b0e70fSEmmanuel Vadot# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2d5b0e70fSEmmanuel Vadot%YAML 1.2 3d5b0e70fSEmmanuel Vadot--- 4d5b0e70fSEmmanuel Vadot$id: http://devicetree.org/schemas/bus/qcom,ssc-block-bus.yaml# 5d5b0e70fSEmmanuel Vadot$schema: http://devicetree.org/meta-schemas/core.yaml# 6d5b0e70fSEmmanuel Vadot 7d5b0e70fSEmmanuel Vadottitle: The AHB Bus Providing a Global View of the SSC Block on (some) qcom SoCs 8d5b0e70fSEmmanuel Vadot 9d5b0e70fSEmmanuel Vadotmaintainers: 10d5b0e70fSEmmanuel Vadot - Michael Srba <Michael.Srba@seznam.cz> 11d5b0e70fSEmmanuel Vadot 12d5b0e70fSEmmanuel Vadotdescription: | 13d5b0e70fSEmmanuel Vadot This binding describes the dependencies (clocks, resets, power domains) which 14d5b0e70fSEmmanuel Vadot need to be turned on in a sequence before communication over the AHB bus 15d5b0e70fSEmmanuel Vadot becomes possible. 16d5b0e70fSEmmanuel Vadot 17d5b0e70fSEmmanuel Vadot Additionally, the reg property is used to pass to the driver the location of 18d5b0e70fSEmmanuel Vadot two sadly undocumented registers which need to be poked as part of the sequence. 19d5b0e70fSEmmanuel Vadot 20d5b0e70fSEmmanuel Vadot The SSC (Snapdragon Sensor Core) block contains a gpio controller, i2c/spi/uart 21d5b0e70fSEmmanuel Vadot controllers, a hexagon core, and a clock controller which provides clocks for 22d5b0e70fSEmmanuel Vadot the above. 23d5b0e70fSEmmanuel Vadot 24d5b0e70fSEmmanuel Vadotproperties: 25d5b0e70fSEmmanuel Vadot compatible: 26d5b0e70fSEmmanuel Vadot items: 27d5b0e70fSEmmanuel Vadot - const: qcom,msm8998-ssc-block-bus 28d5b0e70fSEmmanuel Vadot - const: qcom,ssc-block-bus 29d5b0e70fSEmmanuel Vadot 30d5b0e70fSEmmanuel Vadot reg: 31*b97ee269SEmmanuel Vadot items: 32*b97ee269SEmmanuel Vadot - description: SSCAON_CONFIG0 registers 33*b97ee269SEmmanuel Vadot - description: SSCAON_CONFIG1 registers 34d5b0e70fSEmmanuel Vadot 35d5b0e70fSEmmanuel Vadot reg-names: 36d5b0e70fSEmmanuel Vadot items: 37d5b0e70fSEmmanuel Vadot - const: mpm_sscaon_config0 38d5b0e70fSEmmanuel Vadot - const: mpm_sscaon_config1 39d5b0e70fSEmmanuel Vadot 40d5b0e70fSEmmanuel Vadot '#address-cells': 41d5b0e70fSEmmanuel Vadot enum: [ 1, 2 ] 42d5b0e70fSEmmanuel Vadot 43d5b0e70fSEmmanuel Vadot '#size-cells': 44d5b0e70fSEmmanuel Vadot enum: [ 1, 2 ] 45d5b0e70fSEmmanuel Vadot 46d5b0e70fSEmmanuel Vadot ranges: true 47d5b0e70fSEmmanuel Vadot 48d5b0e70fSEmmanuel Vadot clocks: 49d5b0e70fSEmmanuel Vadot maxItems: 6 50d5b0e70fSEmmanuel Vadot 51d5b0e70fSEmmanuel Vadot clock-names: 52d5b0e70fSEmmanuel Vadot items: 53d5b0e70fSEmmanuel Vadot - const: xo 54d5b0e70fSEmmanuel Vadot - const: aggre2 55d5b0e70fSEmmanuel Vadot - const: gcc_im_sleep 56d5b0e70fSEmmanuel Vadot - const: aggre2_north 57d5b0e70fSEmmanuel Vadot - const: ssc_xo 58d5b0e70fSEmmanuel Vadot - const: ssc_ahbs 59d5b0e70fSEmmanuel Vadot 60d5b0e70fSEmmanuel Vadot power-domains: 61*b97ee269SEmmanuel Vadot items: 62*b97ee269SEmmanuel Vadot - description: CX power domain 63*b97ee269SEmmanuel Vadot - description: MX power domain 64d5b0e70fSEmmanuel Vadot 65d5b0e70fSEmmanuel Vadot power-domain-names: 66d5b0e70fSEmmanuel Vadot items: 67d5b0e70fSEmmanuel Vadot - const: ssc_cx 68d5b0e70fSEmmanuel Vadot - const: ssc_mx 69d5b0e70fSEmmanuel Vadot 70d5b0e70fSEmmanuel Vadot resets: 71*b97ee269SEmmanuel Vadot items: 72*b97ee269SEmmanuel Vadot - description: Main reset 73*b97ee269SEmmanuel Vadot - description: 74*b97ee269SEmmanuel Vadot SSC Branch Control Register reset (associated with the ssc_xo and 75*b97ee269SEmmanuel Vadot ssc_ahbs clocks) 76d5b0e70fSEmmanuel Vadot 77d5b0e70fSEmmanuel Vadot reset-names: 78d5b0e70fSEmmanuel Vadot items: 79d5b0e70fSEmmanuel Vadot - const: ssc_reset 80d5b0e70fSEmmanuel Vadot - const: ssc_bcr 81d5b0e70fSEmmanuel Vadot 82d5b0e70fSEmmanuel Vadot qcom,halt-regs: 83d5b0e70fSEmmanuel Vadot $ref: /schemas/types.yaml#/definitions/phandle-array 84d5b0e70fSEmmanuel Vadot description: describes how to locate the ssc AXI halt register 85d5b0e70fSEmmanuel Vadot items: 86d5b0e70fSEmmanuel Vadot - items: 87d5b0e70fSEmmanuel Vadot - description: Phandle reference to a syscon representing TCSR 88d5b0e70fSEmmanuel Vadot - description: offset for the ssc AXI halt register 89d5b0e70fSEmmanuel Vadot 90d5b0e70fSEmmanuel Vadotrequired: 91d5b0e70fSEmmanuel Vadot - compatible 92d5b0e70fSEmmanuel Vadot - reg 93d5b0e70fSEmmanuel Vadot - reg-names 94d5b0e70fSEmmanuel Vadot - '#address-cells' 95d5b0e70fSEmmanuel Vadot - '#size-cells' 96d5b0e70fSEmmanuel Vadot - ranges 97d5b0e70fSEmmanuel Vadot - clocks 98d5b0e70fSEmmanuel Vadot - clock-names 99d5b0e70fSEmmanuel Vadot - power-domains 100d5b0e70fSEmmanuel Vadot - power-domain-names 101d5b0e70fSEmmanuel Vadot - resets 102d5b0e70fSEmmanuel Vadot - reset-names 103d5b0e70fSEmmanuel Vadot - qcom,halt-regs 104d5b0e70fSEmmanuel Vadot 105d5b0e70fSEmmanuel VadotadditionalProperties: 106d5b0e70fSEmmanuel Vadot type: object 107d5b0e70fSEmmanuel Vadot 108d5b0e70fSEmmanuel Vadotexamples: 109d5b0e70fSEmmanuel Vadot - | 110d5b0e70fSEmmanuel Vadot #include <dt-bindings/clock/qcom,gcc-msm8998.h> 111d5b0e70fSEmmanuel Vadot #include <dt-bindings/clock/qcom,rpmcc.h> 112d5b0e70fSEmmanuel Vadot #include <dt-bindings/power/qcom-rpmpd.h> 113d5b0e70fSEmmanuel Vadot 114d5b0e70fSEmmanuel Vadot soc { 115d5b0e70fSEmmanuel Vadot #address-cells = <1>; 116d5b0e70fSEmmanuel Vadot #size-cells = <1>; 117d5b0e70fSEmmanuel Vadot 118d5b0e70fSEmmanuel Vadot // devices under this node are physically located in the SSC block, connected to an ssc-internal bus; 119d5b0e70fSEmmanuel Vadot ssc_ahb_slave: bus@10ac008 { 120d5b0e70fSEmmanuel Vadot #address-cells = <1>; 121d5b0e70fSEmmanuel Vadot #size-cells = <1>; 122d5b0e70fSEmmanuel Vadot ranges; 123d5b0e70fSEmmanuel Vadot 124d5b0e70fSEmmanuel Vadot compatible = "qcom,msm8998-ssc-block-bus", "qcom,ssc-block-bus"; 125d5b0e70fSEmmanuel Vadot reg = <0x10ac008 0x4>, <0x10ac010 0x4>; 126d5b0e70fSEmmanuel Vadot reg-names = "mpm_sscaon_config0", "mpm_sscaon_config1"; 127d5b0e70fSEmmanuel Vadot 128d5b0e70fSEmmanuel Vadot clocks = <&xo>, 129d5b0e70fSEmmanuel Vadot <&rpmcc RPM_SMD_AGGR2_NOC_CLK>, 130d5b0e70fSEmmanuel Vadot <&gcc GCC_IM_SLEEP>, 131d5b0e70fSEmmanuel Vadot <&gcc AGGRE2_SNOC_NORTH_AXI>, 132d5b0e70fSEmmanuel Vadot <&gcc SSC_XO>, 133d5b0e70fSEmmanuel Vadot <&gcc SSC_CNOC_AHBS_CLK>; 134d5b0e70fSEmmanuel Vadot clock-names = "xo", "aggre2", "gcc_im_sleep", "aggre2_north", "ssc_xo", "ssc_ahbs"; 135d5b0e70fSEmmanuel Vadot 136d5b0e70fSEmmanuel Vadot resets = <&gcc GCC_SSC_RESET>, <&gcc GCC_SSC_BCR>; 137d5b0e70fSEmmanuel Vadot reset-names = "ssc_reset", "ssc_bcr"; 138d5b0e70fSEmmanuel Vadot 139d5b0e70fSEmmanuel Vadot power-domains = <&rpmpd MSM8998_SSCCX>, <&rpmpd MSM8998_SSCMX>; 140d5b0e70fSEmmanuel Vadot power-domain-names = "ssc_cx", "ssc_mx"; 141d5b0e70fSEmmanuel Vadot 142d5b0e70fSEmmanuel Vadot qcom,halt-regs = <&tcsr_mutex_regs 0x26000>; 143d5b0e70fSEmmanuel Vadot }; 144d5b0e70fSEmmanuel Vadot }; 145