1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/cache/l2c2x0.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: ARM L2 Cache Controller
8
9maintainers:
10  - Rob Herring <robh@kernel.org>
11
12description: |+
13  ARM cores often have a separate L2C210/L2C220/L2C310 (also known as PL210/
14  PL220/PL310 and variants) based level 2 cache controller. All these various
15  implementations of the L2 cache controller have compatible programming
16  models (Note 1). Some of the properties that are just prefixed "cache-*" are
17  taken from section 3.7.3 of the Devicetree Specification which can be found
18  at:
19  https://www.devicetree.org/specifications/
20
21  Note 1: The description in this document doesn't apply to integrated L2
22    cache controllers as found in e.g. Cortex-A15/A7/A57/A53. These
23    integrated L2 controllers are assumed to be all preconfigured by
24    early secure boot code. Thus no need to deal with their configuration
25    in the kernel at all.
26
27allOf:
28  - $ref: /schemas/cache-controller.yaml#
29
30properties:
31  compatible:
32    oneOf:
33      - enum:
34          - arm,pl310-cache
35          - arm,l220-cache
36          - arm,l210-cache
37            # DEPRECATED by "brcm,bcm11351-a2-pl310-cache"
38          - bcm,bcm11351-a2-pl310-cache
39            # For Broadcom bcm11351 chipset where an
40            # offset needs to be added to the address before passing down to the L2
41            # cache controller
42          - brcm,bcm11351-a2-pl310-cache
43            # Marvell Controller designed to be
44            # compatible with the ARM one, with system cache mode (meaning
45            # maintenance operations on L1 are broadcasted to the L2 and L2
46            # performs the same operation).
47          - marvell,aurora-system-cache
48            # Marvell Controller designed to be
49            # compatible with the ARM one with outer cache mode.
50          - marvell,aurora-outer-cache
51      - items:
52           # Marvell Tauros3 cache controller, compatible
53           # with arm,pl310-cache controller.
54          - const: marvell,tauros3-cache
55          - const: arm,pl310-cache
56
57  cache-level:
58    const: 2
59
60  cache-unified: true
61  cache-size: true
62  cache-sets: true
63  cache-block-size: true
64  cache-line-size: true
65
66  reg:
67    maxItems: 1
68
69  arm,data-latency:
70    description: Cycles of latency for Data RAM accesses. Specifies 3 cells of
71      read, write and setup latencies. Minimum valid values are 1. Controllers
72      without setup latency control should use a value of 0.
73    $ref: /schemas/types.yaml#/definitions/uint32-array
74    minItems: 2
75    maxItems: 3
76    items:
77      minimum: 0
78      maximum: 8
79
80  arm,tag-latency:
81    description: Cycles of latency for Tag RAM accesses. Specifies 3 cells of
82      read, write and setup latencies. Controllers without setup latency control
83      should use 0. Controllers without separate read and write Tag RAM latency
84      values should only use the first cell.
85    $ref: /schemas/types.yaml#/definitions/uint32-array
86    minItems: 1
87    maxItems: 3
88    items:
89      minimum: 0
90      maximum: 8
91
92  arm,dirty-latency:
93    description: Cycles of latency for Dirty RAMs. This is a single cell.
94    $ref: /schemas/types.yaml#/definitions/uint32
95    minimum: 1
96    maximum: 8
97
98  arm,filter-ranges:
99    description: <start length> Starting address and length of window to
100      filter. Addresses in the filter window are directed to the M1 port. Other
101      addresses will go to the M0 port.
102    $ref: /schemas/types.yaml#/definitions/uint32-array
103    items:
104      minItems: 2
105      maxItems: 2
106
107  arm,io-coherent:
108    description: indicates that the system is operating in an hardware
109      I/O coherent mode. Valid only when the arm,pl310-cache compatible
110      string is used.
111    type: boolean
112
113  interrupts:
114    # Either a single combined interrupt or up to 9 individual interrupts
115    minItems: 1
116    maxItems: 9
117
118  cache-id-part:
119    description: cache id part number to be used if it is not present
120      on hardware
121    $ref: /schemas/types.yaml#/definitions/uint32
122
123  wt-override:
124    description: If present then L2 is forced to Write through mode
125    type: boolean
126
127  arm,double-linefill:
128    description: Override double linefill enable setting. Enable if
129      non-zero, disable if zero.
130    $ref: /schemas/types.yaml#/definitions/uint32
131    enum: [0, 1]
132
133  arm,double-linefill-incr:
134    description: Override double linefill on INCR read. Enable
135      if non-zero, disable if zero.
136    $ref: /schemas/types.yaml#/definitions/uint32
137    enum: [0, 1]
138
139  arm,double-linefill-wrap:
140    description: Override double linefill on WRAP read. Enable
141      if non-zero, disable if zero.
142    $ref: /schemas/types.yaml#/definitions/uint32
143    enum: [0, 1]
144
145  arm,prefetch-drop:
146    description: Override prefetch drop enable setting. Enable if non-zero,
147      disable if zero.
148    $ref: /schemas/types.yaml#/definitions/uint32
149    enum: [0, 1]
150
151  arm,prefetch-offset:
152    description: Override prefetch offset value.
153    $ref: /schemas/types.yaml#/definitions/uint32
154    enum: [0, 1, 2, 3, 4, 5, 6, 7, 15, 23, 31]
155
156  arm,shared-override:
157    description: The default behavior of the L220 or PL310 cache
158      controllers with respect to the shareable attribute is to transform "normal
159      memory non-cacheable transactions" into "cacheable no allocate" (for reads)
160      or "write through no write allocate" (for writes).
161      On systems where this may cause DMA buffer corruption, this property must
162      be specified to indicate that such transforms are precluded.
163    type: boolean
164
165  arm,parity-enable:
166    description: enable parity checking on the L2 cache (L220 or PL310).
167    type: boolean
168
169  arm,parity-disable:
170    description: disable parity checking on the L2 cache (L220 or PL310).
171    type: boolean
172
173  marvell,ecc-enable:
174    description: enable ECC protection on the L2 cache
175    type: boolean
176
177  arm,outer-sync-disable:
178    description: disable the outer sync operation on the L2 cache.
179      Some core tiles, especially ARM PB11MPCore have a faulty L220 cache that
180      will randomly hang unless outer sync operations are disabled.
181    type: boolean
182
183  prefetch-data:
184    description: |
185      Data prefetch. Value: <0> (forcibly disable), <1>
186      (forcibly enable), property absent (retain settings set by firmware)
187    $ref: /schemas/types.yaml#/definitions/uint32
188    enum: [0, 1]
189
190  prefetch-instr:
191    description: |
192      Instruction prefetch. Value: <0> (forcibly disable),
193      <1> (forcibly enable), property absent (retain settings set by
194      firmware)
195    $ref: /schemas/types.yaml#/definitions/uint32
196    enum: [0, 1]
197
198  arm,dynamic-clock-gating:
199    description: |
200      L2 dynamic clock gating. Value: <0> (forcibly
201      disable), <1> (forcibly enable), property absent (OS specific behavior,
202      preferably retain firmware settings)
203    $ref: /schemas/types.yaml#/definitions/uint32
204    enum: [0, 1]
205
206  arm,standby-mode:
207    description: L2 standby mode enable. Value <0> (forcibly disable),
208      <1> (forcibly enable), property absent (OS specific behavior,
209      preferably retain firmware settings)
210    $ref: /schemas/types.yaml#/definitions/uint32
211    enum: [0, 1]
212
213  arm,early-bresp-disable:
214    description: Disable the CA9 optimization Early BRESP (PL310)
215    type: boolean
216
217  arm,full-line-zero-disable:
218    description: Disable the CA9 optimization Full line of zero
219      write (PL310)
220    type: boolean
221
222required:
223  - compatible
224  - cache-unified
225  - reg
226
227additionalProperties: false
228
229examples:
230  - |
231    cache-controller@fff12000 {
232        compatible = "arm,pl310-cache";
233        reg = <0xfff12000 0x1000>;
234        arm,data-latency = <1 1 1>;
235        arm,tag-latency = <2 2 2>;
236        arm,filter-ranges = <0x80000000 0x8000000>;
237        cache-unified;
238        cache-level = <2>;
239        interrupts = <45>;
240    };
241
242...
243