1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/brcm,iproc-clocks.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Broadcom iProc Family Clocks
8
9maintainers:
10  - Ray Jui <rjui@broadcom.com>
11  - Scott Branden <sbranden@broadcom.com>
12
13description: |
14  The iProc clock controller manages clocks that are common to the iProc family.
15  An SoC from the iProc family may have several PLLs, e.g., ARMPLL, GENPLL,
16  LCPLL0, MIPIPLL, and etc., all derived from an onboard crystal. Each PLL
17  comprises of several leaf clocks
18
19  ASIU clocks are a special case. These clocks are derived directly from the
20  reference clock of the onboard crystal.
21
22properties:
23  compatible:
24    enum:
25      - brcm,bcm63138-armpll
26      - brcm,cygnus-armpll
27      - brcm,cygnus-genpll
28      - brcm,cygnus-lcpll0
29      - brcm,cygnus-mipipll
30      - brcm,cygnus-asiu-clk
31      - brcm,cygnus-audiopll
32      - brcm,hr2-armpll
33      - brcm,nsp-armpll
34      - brcm,nsp-genpll
35      - brcm,nsp-lcpll0
36      - brcm,ns2-genpll-scr
37      - brcm,ns2-genpll-sw
38      - brcm,ns2-lcpll-ddr
39      - brcm,ns2-lcpll-ports
40      - brcm,sr-genpll0
41      - brcm,sr-genpll1
42      - brcm,sr-genpll2
43      - brcm,sr-genpll3
44      - brcm,sr-genpll4
45      - brcm,sr-genpll5
46      - brcm,sr-genpll6
47      - brcm,sr-lcpll0
48      - brcm,sr-lcpll1
49      - brcm,sr-lcpll-pcie
50
51  reg:
52    minItems: 1
53    items:
54      - description: base register
55      - description: power register
56      - description: ASIU or split status register
57
58  clocks:
59    description: The input parent clock phandle for the PLL / ASIU clock. For
60      most iProc PLLs, this is an onboard crystal with a fixed rate.
61    maxItems: 1
62
63  '#clock-cells':
64    true
65
66  clock-output-names:
67    minItems: 1
68    maxItems: 45
69
70allOf:
71  - if:
72      properties:
73        compatible:
74          contains:
75            enum:
76              - brcm,cygnus-armpll
77              - brcm,nsp-armpll
78    then:
79      properties:
80        '#clock-cells':
81          const: 0
82    else:
83      properties:
84        '#clock-cells':
85          const: 1
86      required:
87        - clock-output-names
88  - if:
89      properties:
90        compatible:
91          contains:
92            enum:
93              - brcm,cygnus-armpll
94              - brcm,cygnus-genpll
95              - brcm,cygnus-lcpll0
96              - brcm,cygnus-mipipll
97              - brcm,cygnus-asiu-clk
98              - brcm,cygnus-audiopll
99    then:
100      properties:
101        clock-output-names:
102          description: |
103            The following table defines the set of PLL/clock index and ID for Cygnus.
104            These clock IDs are defined in:
105                "include/dt-bindings/clock/bcm-cygnus.h"
106
107            Clock      	Source (Parent)	Index	ID
108            -----	---------------	-----	--
109            crystal	N/A		N/A	N/A
110
111            armpll	crystal		N/A	N/A
112
113            keypad	crystal (ASIU)	0	BCM_CYGNUS_ASIU_KEYPAD_CLK
114            adc/tsc	crystal (ASIU)	1	BCM_CYGNUS_ASIU_ADC_CLK
115            pwm	crystal (ASIU)		2	BCM_CYGNUS_ASIU_PWM_CLK
116
117            genpll	crystal		0	BCM_CYGNUS_GENPLL
118            axi21	genpll		1	BCM_CYGNUS_GENPLL_AXI21_CLK
119            250mhz	genpll		2	BCM_CYGNUS_GENPLL_250MHZ_CLK
120            ihost_sys	genpll		3	BCM_CYGNUS_GENPLL_IHOST_SYS_CLK
121            enet_sw	genpll		4	BCM_CYGNUS_GENPLL_ENET_SW_CLK
122            audio_125	genpll		5	BCM_CYGNUS_GENPLL_AUDIO_125_CLK
123            can		genpll		6	BCM_CYGNUS_GENPLL_CAN_CLK
124
125            lcpll0	crystal		0	BCM_CYGNUS_LCPLL0
126            pcie_phy	lcpll0		1	BCM_CYGNUS_LCPLL0_PCIE_PHY_REF_CLK
127            ddr_phy	lcpll0		2	BCM_CYGNUS_LCPLL0_DDR_PHY_CLK
128            sdio	lcpll0		3	BCM_CYGNUS_LCPLL0_SDIO_CLK
129            usb_phy	lcpll0		4	BCM_CYGNUS_LCPLL0_USB_PHY_REF_CLK
130            smart_card	lcpll0		5	BCM_CYGNUS_LCPLL0_SMART_CARD_CLK
131            ch5_unused	lcpll0		6	BCM_CYGNUS_LCPLL0_CH5_UNUSED
132
133            mipipll	crystal		0	BCM_CYGNUS_MIPIPLL
134            ch0_unused	mipipll		1	BCM_CYGNUS_MIPIPLL_CH0_UNUSED
135            ch1_lcd	mipipll		2	BCM_CYGNUS_MIPIPLL_CH1_LCD
136            ch2_v3d	mipipll		3	BCM_CYGNUS_MIPIPLL_CH2_V3D
137            ch3_unused	mipipll		4	BCM_CYGNUS_MIPIPLL_CH3_UNUSED
138            ch4_unused	mipipll		5	BCM_CYGNUS_MIPIPLL_CH4_UNUSED
139            ch5_unused	mipipll		6	BCM_CYGNUS_MIPIPLL_CH5_UNUSED
140
141            audiopll	crystal		0	BCM_CYGNUS_AUDIOPLL
142            ch0_audio	audiopll	1	BCM_CYGNUS_AUDIOPLL_CH0
143            ch1_audio	audiopll	2	BCM_CYGNUS_AUDIOPLL_CH1
144            ch2_audio	audiopll	3	BCM_CYGNUS_AUDIOPLL_CH2
145  - if:
146      properties:
147        compatible:
148          contains:
149            enum:
150              - brcm,hr2-armpll
151    then:
152      properties:
153        clock-output-names:
154          description: |
155            The following table defines the set of PLL/clock for Hurricane 2:
156
157            Clock	Source		Index	ID
158            -----	------		-----	--
159            crystal	N/A		N/A	N/A
160
161            armpll	crystal		N/A	N/A
162  - if:
163      properties:
164        compatible:
165          contains:
166            enum:
167              - brcm,nsp-armpll
168              - brcm,nsp-genpll
169              - brcm,nsp-lcpll0
170    then:
171      properties:
172        clock-output-names:
173          description: |
174            The following table defines the set of PLL/clock index and ID for Northstar and
175            Northstar Plus.  These clock IDs are defined in:
176                "include/dt-bindings/clock/bcm-nsp.h"
177
178            Clock	Source		Index	ID
179            -----	------		-----	--
180            crystal	N/A		N/A	N/A
181
182            armpll	crystal		N/A	N/A
183
184            genpll	crystal		0	BCM_NSP_GENPLL
185            phy		genpll		1	BCM_NSP_GENPLL_PHY_CLK
186            ethernetclk	genpll		2	BCM_NSP_GENPLL_ENET_SW_CLK
187            usbclk	genpll		3	BCM_NSP_GENPLL_USB_PHY_REF_CLK
188            iprocfast	genpll		4	BCM_NSP_GENPLL_IPROCFAST_CLK
189            sata1	genpll		5	BCM_NSP_GENPLL_SATA1_CLK
190            sata2	genpll		6	BCM_NSP_GENPLL_SATA2_CLK
191
192            lcpll0	crystal		0	BCM_NSP_LCPLL0
193            pcie_phy	lcpll0		1	BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK
194            sdio	lcpll0		2	BCM_NSP_LCPLL0_SDIO_CLK
195            ddr_phy	lcpll0		3	BCM_NSP_LCPLL0_DDR_PHY_CLK
196  - if:
197      properties:
198        compatible:
199          contains:
200            enum:
201              - brcm,ns2-genpll-scr
202              - brcm,ns2-genpll-sw
203              - brcm,ns2-lcpll-ddr
204              - brcm,ns2-lcpll-ports
205    then:
206      properties:
207        clock-output-names:
208          description: |
209            The following table defines the set of PLL/clock index and ID for Northstar 2.
210            These clock IDs are defined in:
211                "include/dt-bindings/clock/bcm-ns2.h"
212
213            Clock	Source		Index	ID
214            -----	------		-----	--
215            crystal	N/A		N/A	N/A
216
217            genpll_scr	crystal		0	BCM_NS2_GENPLL_SCR
218            scr		genpll_scr	1	BCM_NS2_GENPLL_SCR_SCR_CLK
219            fs		genpll_scr	2	BCM_NS2_GENPLL_SCR_FS_CLK
220            audio_ref	genpll_scr	3	BCM_NS2_GENPLL_SCR_AUDIO_CLK
221            ch3_unused	genpll_scr	4	BCM_NS2_GENPLL_SCR_CH3_UNUSED
222            ch4_unused	genpll_scr	5	BCM_NS2_GENPLL_SCR_CH4_UNUSED
223            ch5_unused	genpll_scr	6	BCM_NS2_GENPLL_SCR_CH5_UNUSED
224
225            genpll_sw	crystal		0	BCM_NS2_GENPLL_SW
226            rpe		genpll_sw	1	BCM_NS2_GENPLL_SW_RPE_CLK
227            250		genpll_sw	2	BCM_NS2_GENPLL_SW_250_CLK
228            nic		genpll_sw	3	BCM_NS2_GENPLL_SW_NIC_CLK
229            chimp	genpll_sw	4	BCM_NS2_GENPLL_SW_CHIMP_CLK
230            port	genpll_sw	5	BCM_NS2_GENPLL_SW_PORT_CLK
231            sdio	genpll_sw	6	BCM_NS2_GENPLL_SW_SDIO_CLK
232
233            lcpll_ddr	crystal		0	BCM_NS2_LCPLL_DDR
234            pcie_sata_usb lcpll_ddr	1	BCM_NS2_LCPLL_DDR_PCIE_SATA_USB_CLK
235            ddr		lcpll_ddr	2	BCM_NS2_LCPLL_DDR_DDR_CLK
236            ch2_unused	lcpll_ddr	3	BCM_NS2_LCPLL_DDR_CH2_UNUSED
237            ch3_unused	lcpll_ddr	4	BCM_NS2_LCPLL_DDR_CH3_UNUSED
238            ch4_unused	lcpll_ddr	5	BCM_NS2_LCPLL_DDR_CH4_UNUSED
239            ch5_unused	lcpll_ddr	6	BCM_NS2_LCPLL_DDR_CH5_UNUSED
240
241            lcpll_ports	crystal		0	BCM_NS2_LCPLL_PORTS
242            wan		lcpll_ports	1	BCM_NS2_LCPLL_PORTS_WAN_CLK
243            rgmii	lcpll_ports	2	BCM_NS2_LCPLL_PORTS_RGMII_CLK
244            ch2_unused	lcpll_ports	3	BCM_NS2_LCPLL_PORTS_CH2_UNUSED
245            ch3_unused	lcpll_ports	4	BCM_NS2_LCPLL_PORTS_CH3_UNUSED
246            ch4_unused	lcpll_ports	5	BCM_NS2_LCPLL_PORTS_CH4_UNUSED
247            ch5_unused	lcpll_ports	6	BCM_NS2_LCPLL_PORTS_CH5_UNUSED
248  - if:
249      properties:
250        compatible:
251          contains:
252            enum:
253              - brcm,sr-genpll0
254              - brcm,sr-genpll1
255              - brcm,sr-genpll2
256              - brcm,sr-genpll3
257              - brcm,sr-genpll4
258              - brcm,sr-genpll5
259              - brcm,sr-genpll6
260              - brcm,sr-lcpll0
261              - brcm,sr-lcpll1
262              - brcm,sr-lcpll-pcie
263    then:
264      properties:
265        clock-output-names:
266          description: |
267            The following table defines the set of PLL/clock index and ID for Stingray.
268            These clock IDs are defined in:
269                "include/dt-bindings/clock/bcm-sr.h"
270
271            Clock		Source		Index	ID
272            -----		------		-----	--
273            crystal		N/A		N/A	N/A
274            crmu_ref25m		crystal		N/A	N/A
275
276            genpll0		crystal		0	BCM_SR_GENPLL0
277            clk_125m		genpll0		1	BCM_SR_GENPLL0_125M_CLK
278            clk_scr		genpll0		2	BCM_SR_GENPLL0_SCR_CLK
279            clk_250		genpll0		3	BCM_SR_GENPLL0_250M_CLK
280            clk_pcie_axi	genpll0		4	BCM_SR_GENPLL0_PCIE_AXI_CLK
281            clk_paxc_axi_x2	genpll0		5	BCM_SR_GENPLL0_PAXC_AXI_X2_CLK
282            clk_paxc_axi	genpll0		6	BCM_SR_GENPLL0_PAXC_AXI_CLK
283
284            genpll1		crystal		0	BCM_SR_GENPLL1
285            clk_pcie_tl		genpll1		1	BCM_SR_GENPLL1_PCIE_TL_CLK
286            clk_mhb_apb		genpll1		2	BCM_SR_GENPLL1_MHB_APB_CLK
287
288            genpll2		crystal		0	BCM_SR_GENPLL2
289            clk_nic		genpll2		1	BCM_SR_GENPLL2_NIC_CLK
290            clk_ts_500_ref	genpll2		2	BCM_SR_GENPLL2_TS_500_REF_CLK
291            clk_125_nitro	genpll2		3	BCM_SR_GENPLL2_125_NITRO_CLK
292            clk_chimp		genpll2		4	BCM_SR_GENPLL2_CHIMP_CLK
293            clk_nic_flash	genpll2		5	BCM_SR_GENPLL2_NIC_FLASH_CLK
294            clk_fs		genpll2		6	BCM_SR_GENPLL2_FS_CLK
295
296            genpll3		crystal		0	BCM_SR_GENPLL3
297            clk_hsls		genpll3		1	BCM_SR_GENPLL3_HSLS_CLK
298            clk_sdio		genpll3		2	BCM_SR_GENPLL3_SDIO_CLK
299
300            genpll4		crystal		0	BCM_SR_GENPLL4
301            clk_ccn		genpll4		1	BCM_SR_GENPLL4_CCN_CLK
302            clk_tpiu_pll	genpll4		2	BCM_SR_GENPLL4_TPIU_PLL_CLK
303            clk_noc		genpll4		3	BCM_SR_GENPLL4_NOC_CLK
304            clk_chclk_fs4	genpll4		4	BCM_SR_GENPLL4_CHCLK_FS4_CLK
305            clk_bridge_fscpu	genpll4		5	BCM_SR_GENPLL4_BRIDGE_FSCPU_CLK
306
307            genpll5		crystal		0	BCM_SR_GENPLL5
308            clk_fs4_hf		genpll5		1	BCM_SR_GENPLL5_FS4_HF_CLK
309            clk_crypto_ae	genpll5		2	BCM_SR_GENPLL5_CRYPTO_AE_CLK
310            clk_raid_ae		genpll5		3	BCM_SR_GENPLL5_RAID_AE_CLK
311
312            genpll6		crystal		0	BCM_SR_GENPLL6
313            clk_48_usb		genpll6		1	BCM_SR_GENPLL6_48_USB_CLK
314
315            lcpll0		crystal		0	BCM_SR_LCPLL0
316            clk_sata_refp 	lcpll0		1	BCM_SR_LCPLL0_SATA_REFP_CLK
317            clk_sata_refn	lcpll0		2	BCM_SR_LCPLL0_SATA_REFN_CLK
318            clk_sata_350	lcpll0		3	BCM_SR_LCPLL0_SATA_350_CLK
319            clk_sata_500	lcpll0		4	BCM_SR_LCPLL0_SATA_500_CLK
320
321            lcpll1		crystal		0	BCM_SR_LCPLL1
322            clk_wan		lcpll1		1	BCM_SR_LCPLL1_WAN_CLK
323            clk_usb_ref		lcpll1		2	BCM_SR_LCPLL1_USB_REF_CLK
324            clk_crmu_ts		lcpll1		3	BCM_SR_LCPLL1_CRMU_TS_CLK
325
326            lcpll_pcie		crystal		0	BCM_SR_LCPLL_PCIE
327            clk_pcie_phy_ref	lcpll1		1	BCM_SR_LCPLL_PCIE_PHY_REF_CLK
328  - if:
329      properties:
330        compatible:
331          contains:
332            const: brcm,cygnus-genpll
333    then:
334      properties:
335        clock-output-names:
336          items:
337            - const: genpll
338            - const: axi21
339            - const: 250mhz
340            - const: ihost_sys
341            - const: enet_sw
342            - const: audio_125
343            - const: can
344  - if:
345      properties:
346        compatible:
347          contains:
348            const: brcm,nsp-lcpll0
349    then:
350      properties:
351        clock-output-names:
352          items:
353            - const: lcpll0
354            - const: pcie_phy
355            - const: sdio
356            - const: ddr_phy
357  - if:
358      properties:
359        compatible:
360          contains:
361            const: brcm,nsp-genpll
362    then:
363      properties:
364        clock-output-names:
365          items:
366            - const: genpll
367            - const: phy
368            - const: ethernetclk
369            - const: usbclk
370            - const: iprocfast
371            - const: sata1
372            - const: sata2
373
374required:
375  - reg
376  - clocks
377  - '#clock-cells'
378
379additionalProperties: false
380
381examples:
382  - |
383    osc1: oscillator {
384        #clock-cells = <0>;
385        compatible = "fixed-clock";
386        clock-frequency = <25000000>;
387    };
388
389    genpll@301d000 {
390        #clock-cells = <1>;
391        compatible = "brcm,cygnus-genpll";
392        reg = <0x301d000 0x2c>, <0x301c020 0x4>;
393        clocks = <&os1c>;
394        clock-output-names = "genpll", "axi21", "250mhz", "ihost_sys",
395                     "enet_sw", "audio_125", "can";
396    };
397  - |
398    osc2: oscillator {
399        #clock-cells = <0>;
400        compatible = "fixed-clock";
401        clock-frequency = <25000000>;
402    };
403
404    asiu_clks@301d048 {
405        #clock-cells = <1>;
406        compatible = "brcm,cygnus-asiu-clk";
407        reg = <0x301d048 0xc>, <0x180aa024 0x4>;
408        clocks = <&osc2>;
409        clock-output-names = "keypad", "adc/touch", "pwm";
410    };
411  - |
412    arm_clk@0 {
413        #clock-cells = <0>;
414        compatible = "brcm,nsp-armpll";
415        clocks = <&osc>;
416        reg = <0x0 0x1000>;
417    };
418