1* Samsung Audio Subsystem Clock Controller
2
3The Samsung Audio Subsystem clock controller generates and supplies clocks
4to Audio Subsystem block available in the S5PV210 and Exynos SoCs. The clock
5binding described here is applicable to all SoCs in Exynos family.
6
7Required Properties:
8
9- compatible: should be one of the following:
10  - "samsung,exynos4210-audss-clock" - controller compatible with all Exynos4 SoCs.
11  - "samsung,exynos5250-audss-clock" - controller compatible with Exynos5250
12    SoCs.
13  - "samsung,exynos5410-audss-clock" - controller compatible with Exynos5410
14    SoCs.
15  - "samsung,exynos5420-audss-clock" - controller compatible with Exynos5420
16    SoCs.
17- reg: physical base address and length of the controller's register set.
18
19- #clock-cells: should be 1.
20
21- clocks:
22  - pll_ref: Fixed rate PLL reference clock, parent of mout_audss. "fin_pll"
23    is used if not specified.
24  - pll_in: Input PLL to the AudioSS block, parent of mout_audss. "fout_epll"
25    is used if not specified.
26  - cdclk: External i2s clock, parent of mout_i2s. "cdclk0" is used if not
27    specified.
28  - sclk_audio: Audio bus clock, parent of mout_i2s. "sclk_audio0" is used if
29    not specified.
30  - sclk_pcm_in: PCM clock, parent of sclk_pcm.  "sclk_pcm0" is used if not
31    specified.
32
33- clock-names: Aliases for the above clocks. They should be "pll_ref",
34  "pll_in", "cdclk", "sclk_audio", and "sclk_pcm_in" respectively.
35
36Optional Properties:
37
38  - power-domains: a phandle to respective power domain node as described by
39    generic PM domain bindings (see power/power_domain.txt for more
40    information).
41
42The following is the list of clocks generated by the controller. Each clock is
43assigned an identifier and client nodes use this identifier to specify the
44clock which they consume. Some of the clocks are available only on a particular
45Exynos4 SoC and this is specified where applicable.
46
47Provided clocks:
48
49Clock           ID      SoC (if specific)
50-----------------------------------------------
51
52mout_audss      0
53mout_i2s        1
54dout_srp        2
55dout_aud_bus    3
56dout_i2s        4
57srp_clk         5
58i2s_bus         6
59sclk_i2s        7
60pcm_bus         8
61sclk_pcm        9
62adma            10      Exynos5420
63
64Example 1: An example of a clock controller node using the default input
65	   clock names is listed below.
66
67clock_audss: audss-clock-controller@3810000 {
68	compatible = "samsung,exynos5250-audss-clock";
69	reg = <0x03810000 0x0C>;
70	#clock-cells = <1>;
71};
72
73Example 2: An example of a clock controller node with the input clocks
74           specified.
75
76clock_audss: audss-clock-controller@3810000 {
77	compatible = "samsung,exynos5250-audss-clock";
78	reg = <0x03810000 0x0C>;
79	#clock-cells = <1>;
80	clocks = <&clock 1>, <&clock 7>, <&clock 138>, <&clock 160>,
81		<&ext_i2s_clk>;
82	clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in", "cdclk";
83};
84
85Example 3: I2S controller node that consumes the clock generated by the clock
86           controller. Refer to the standard clock bindings for information
87           about 'clocks' and 'clock-names' property.
88
89i2s0: i2s@3830000 {
90	compatible = "samsung,i2s-v5";
91	reg = <0x03830000 0x100>;
92	dmas = <&pdma0 10
93		&pdma0 9
94		&pdma0 8>;
95	dma-names = "tx", "rx", "tx-sec";
96	clocks = <&clock_audss EXYNOS_I2S_BUS>,
97		<&clock_audss EXYNOS_I2S_BUS>,
98		<&clock_audss EXYNOS_SCLK_I2S>,
99		<&clock_audss EXYNOS_MOUT_AUDSS>,
100		<&clock_audss EXYNOS_MOUT_I2S>;
101	clock-names = "iis", "i2s_opclk0", "i2s_opclk1",
102		      "mout_audss", "mout_i2s";
103};
104