1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/imx8mq-clock.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: NXP i.MX8M Quad Clock Control Module Binding
8
9maintainers:
10  - Anson Huang <Anson.Huang@nxp.com>
11
12description: |
13  NXP i.MX8M Quad clock control module is an integrated clock controller, which
14  generates and supplies to all modules.
15
16properties:
17  compatible:
18    const: fsl,imx8mq-ccm
19
20  reg:
21    maxItems: 1
22
23  clocks:
24    items:
25      - description: 32k osc
26      - description: 25m osc
27      - description: 27m osc
28      - description: ext1 clock input
29      - description: ext2 clock input
30      - description: ext3 clock input
31      - description: ext4 clock input
32
33  clock-names:
34    items:
35      - const: ckil
36      - const: osc_25m
37      - const: osc_27m
38      - const: clk_ext1
39      - const: clk_ext2
40      - const: clk_ext3
41      - const: clk_ext4
42
43  '#clock-cells':
44    const: 1
45    description:
46      The clock consumer should specify the desired clock by having the clock
47      ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8mq-clock.h
48      for the full list of i.MX8M Quad clock IDs.
49
50required:
51  - compatible
52  - reg
53  - clocks
54  - clock-names
55  - '#clock-cells'
56
57examples:
58  # Clock Control Module node:
59  - |
60    clk: clock-controller@30380000 {
61        compatible = "fsl,imx8mq-ccm";
62        reg = <0x30380000 0x10000>;
63        #clock-cells = <1>;
64        clocks = <&ckil>, <&osc_25m>, <&osc_27m>,
65                 <&clk_ext1>, <&clk_ext2>,
66                 <&clk_ext3>, <&clk_ext4>;
67        clock-names = "ckil", "osc_25m", "osc_27m",
68                      "clk_ext1", "clk_ext2",
69                      "clk_ext3", "clk_ext4";
70    };
71
72...
73