1NVIDIA Tegra124 DFLL FCPU clocksource
2
3This binding uses the common clock binding:
4Documentation/devicetree/bindings/clock/clock-bindings.txt
5
6The DFLL IP block on Tegra is a root clocksource designed for clocking
7the fast CPU cluster. It consists of a free-running voltage controlled
8oscillator connected to the CPU voltage rail (VDD_CPU), and a closed loop
9control module that will automatically adjust the VDD_CPU voltage by
10communicating with an off-chip PMIC either via an I2C bus or via PWM signals.
11
12Required properties:
13- compatible : should be one of:
14  - "nvidia,tegra124-dfll": for Tegra124
15  - "nvidia,tegra210-dfll": for Tegra210
16- reg : Defines the following set of registers, in the order listed:
17        - registers for the DFLL control logic.
18        - registers for the I2C output logic.
19        - registers for the integrated I2C master controller.
20        - look-up table RAM for voltage register values.
21- interrupts: Should contain the DFLL block interrupt.
22- clocks: Must contain an entry for each entry in clock-names.
23  See clock-bindings.txt for details.
24- clock-names: Must include the following entries:
25  - soc: Clock source for the DFLL control logic.
26  - ref: The closed loop reference clock
27  - i2c: Clock source for the integrated I2C master.
28- resets: Must contain an entry for each entry in reset-names.
29  See ../reset/reset.txt for details.
30- reset-names: Must include the following entries:
31  - dvco: Reset control for the DFLL DVCO.
32- #clock-cells: Must be 0.
33- clock-output-names: Name of the clock output.
34- vdd-cpu-supply: Regulator for the CPU voltage rail that the DFLL
35  hardware will start controlling. The regulator will be queried for
36  the I2C register, control values and supported voltages.
37
38Required properties for the control loop parameters:
39- nvidia,sample-rate: Sample rate of the DFLL control loop.
40- nvidia,droop-ctrl: See the register CL_DVFS_DROOP_CTRL in the TRM.
41- nvidia,force-mode: See the field DFLL_PARAMS_FORCE_MODE in the TRM.
42- nvidia,cf: Numeric value, see the field DFLL_PARAMS_CF_PARAM in the TRM.
43- nvidia,ci: Numeric value, see the field DFLL_PARAMS_CI_PARAM in the TRM.
44- nvidia,cg: Numeric value, see the field DFLL_PARAMS_CG_PARAM in the TRM.
45
46Optional properties for the control loop parameters:
47- nvidia,cg-scale: Boolean value, see the field DFLL_PARAMS_CG_SCALE in the TRM.
48
49Optional properties for mode selection:
50- nvidia,pwm-to-pmic: Use PWM to control regulator rather then I2C.
51
52Required properties for I2C mode:
53- nvidia,i2c-fs-rate: I2C transfer rate, if using full speed mode.
54
55Required properties for PWM mode:
56- nvidia,pwm-period-nanoseconds: period of PWM square wave in nanoseconds.
57- nvidia,pwm-tristate-microvolts: Regulator voltage in micro volts when PWM
58  control is disabled and the PWM output is tristated. Note that this voltage is
59  configured in hardware, typically via a resistor divider.
60- nvidia,pwm-min-microvolts: Regulator voltage in micro volts when PWM control
61  is enabled and PWM output is low. Hence, this is the minimum output voltage
62  that the regulator supports when PWM control is enabled.
63- nvidia,pwm-voltage-step-microvolts: Voltage increase in micro volts
64  corresponding to a 1/33th increase in duty cycle. Eg the voltage for 2/33th
65  duty cycle would be: nvidia,pwm-min-microvolts +
66  nvidia,pwm-voltage-step-microvolts * 2.
67- pinctrl-0: I/O pad configuration when PWM control is enabled.
68- pinctrl-1: I/O pad configuration when PWM control is disabled.
69- pinctrl-names: must include the following entries:
70  - dvfs_pwm_enable: I/O pad configuration when PWM control is enabled.
71  - dvfs_pwm_disable: I/O pad configuration when PWM control is disabled.
72
73Example for I2C:
74
75clock@70110000 {
76        compatible = "nvidia,tegra124-dfll";
77        reg = <0 0x70110000 0 0x100>, /* DFLL control */
78              <0 0x70110000 0 0x100>, /* I2C output control */
79              <0 0x70110100 0 0x100>, /* Integrated I2C controller */
80              <0 0x70110200 0 0x100>; /* Look-up table RAM */
81        interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
82        clocks = <&tegra_car TEGRA124_CLK_DFLL_SOC>,
83                 <&tegra_car TEGRA124_CLK_DFLL_REF>,
84                 <&tegra_car TEGRA124_CLK_I2C5>;
85        clock-names = "soc", "ref", "i2c";
86        resets = <&tegra_car TEGRA124_RST_DFLL_DVCO>;
87        reset-names = "dvco";
88        #clock-cells = <0>;
89        clock-output-names = "dfllCPU_out";
90        vdd-cpu-supply = <&vdd_cpu>;
91
92        nvidia,sample-rate = <12500>;
93        nvidia,droop-ctrl = <0x00000f00>;
94        nvidia,force-mode = <1>;
95        nvidia,cf = <10>;
96        nvidia,ci = <0>;
97        nvidia,cg = <2>;
98
99        nvidia,i2c-fs-rate = <400000>;
100};
101
102Example for PWM:
103
104clock@70110000 {
105	compatible = "nvidia,tegra124-dfll";
106	reg = <0 0x70110000 0 0x100>, /* DFLL control */
107	      <0 0x70110000 0 0x100>, /* I2C output control */
108	      <0 0x70110100 0 0x100>, /* Integrated I2C controller */
109	      <0 0x70110200 0 0x100>; /* Look-up table RAM */
110	interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
111	clocks = <&tegra_car TEGRA210_CLK_DFLL_SOC>,
112	         <&tegra_car TEGRA210_CLK_DFLL_REF>,
113		 <&tegra_car TEGRA124_CLK_I2C5>;;
114	clock-names = "soc", "ref", "i2c";
115	resets = <&tegra_car TEGRA124_RST_DFLL_DVCO>;
116	reset-names = "dvco";
117	#clock-cells = <0>;
118	clock-output-names = "dfllCPU_out";
119
120	nvidia,sample-rate = <25000>;
121	nvidia,droop-ctrl = <0x00000f00>;
122	nvidia,force-mode = <1>;
123	nvidia,cf = <6>;
124	nvidia,ci = <0>;
125	nvidia,cg = <2>;
126
127	nvidia,pwm-min-microvolts = <708000>; /* 708mV */
128	nvidia,pwm-period-nanoseconds = <2500>; /* 2.5us */
129	nvidia,pwm-to-pmic;
130	nvidia,pwm-tristate-microvolts = <1000000>;
131	nvidia,pwm-voltage-step-microvolts = <19200>; /* 19.2mV */
132
133	pinctrl-names = "dvfs_pwm_enable", "dvfs_pwm_disable";
134	pinctrl-0 = <&dvfs_pwm_active_state>;
135	pinctrl-1 = <&dvfs_pwm_inactive_state>;
136};
137
138/* pinmux nodes added for completeness. Binding doc can be found in:
139 * Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-pinmux.yaml
140 */
141
142pinmux: pinmux@700008d4 {
143	dvfs_pwm_active_state: dvfs_pwm_active {
144		dvfs_pwm_pbb1 {
145			nvidia,pins = "dvfs_pwm_pbb1";
146			nvidia,tristate = <TEGRA_PIN_DISABLE>;
147		};
148	};
149	dvfs_pwm_inactive_state: dvfs_pwm_inactive {
150		dvfs_pwm_pbb1 {
151			nvidia,pins = "dvfs_pwm_pbb1";
152			nvidia,tristate = <TEGRA_PIN_ENABLE>;
153		};
154	};
155};
156