1* Renesas R8A7778 Clock Pulse Generator (CPG)
2
3The CPG generates core clocks for the R8A7778. It includes two PLLs and
4several fixed ratio dividers.
5The CPG also provides a Clock Domain for SoC devices, in combination with the
6CPG Module Stop (MSTP) Clocks.
7
8Required Properties:
9
10  - compatible: Must be "renesas,r8a7778-cpg-clocks"
11  - reg: Base address and length of the memory resource used by the CPG
12  - #clock-cells: Must be 1
13  - clock-output-names: The names of the clocks. Supported clocks are
14    "plla", "pllb", "b", "out", "p", "s", and "s1".
15  - #power-domain-cells: Must be 0
16
17SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed
18through an MSTP clock should refer to the CPG device node in their
19"power-domains" property, as documented by the generic PM domain bindings in
20Documentation/devicetree/bindings/power/power_domain.txt.
21
22
23Examples
24--------
25
26  - CPG device node:
27
28	cpg_clocks: cpg_clocks@ffc80000 {
29		compatible = "renesas,r8a7778-cpg-clocks";
30		reg = <0xffc80000 0x80>;
31		#clock-cells = <1>;
32		clocks = <&extal_clk>;
33		clock-output-names = "plla", "pllb", "b",
34				     "out", "p", "s", "s1";
35		#power-domain-cells = <0>;
36	};
37
38
39  - CPG/MSTP Clock Domain member device node:
40
41	sdhi0: sd@ffe4c000 {
42		compatible = "renesas,sdhi-r8a7778";
43		reg = <0xffe4c000 0x100>;
44		interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>;
45		clocks = <&mstp3_clks R8A7778_CLK_SDHI0>;
46		power-domains = <&cpg_clocks>;
47	};
48