1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2# Copyright 2022 Unisoc Inc.
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/clock/sprd,ums512-clk.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: UMS512 Soc clock controller
9
10maintainers:
11  - Orson Zhai <orsonzhai@gmail.com>
12  - Baolin Wang <baolin.wang7@gmail.com>
13  - Chunyan Zhang <zhang.lyra@gmail.com>
14
15properties:
16  compatible:
17    enum:
18      - sprd,ums512-apahb-gate
19      - sprd,ums512-ap-clk
20      - sprd,ums512-aonapb-clk
21      - sprd,ums512-pmu-gate
22      - sprd,ums512-g0-pll
23      - sprd,ums512-g2-pll
24      - sprd,ums512-g3-pll
25      - sprd,ums512-gc-pll
26      - sprd,ums512-aon-gate
27      - sprd,ums512-audcpapb-gate
28      - sprd,ums512-audcpahb-gate
29      - sprd,ums512-gpu-clk
30      - sprd,ums512-mm-clk
31      - sprd,ums512-mm-gate-clk
32      - sprd,ums512-apapb-gate
33
34  "#clock-cells":
35    const: 1
36
37  clocks:
38    minItems: 1
39    maxItems: 4
40    description: |
41      The input parent clock(s) phandle for the clock, only list
42      fixed clocks which are declared in devicetree.
43
44  clock-names:
45    minItems: 1
46    items:
47      - const: ext-26m
48      - const: ext-32k
49      - const: ext-4m
50      - const: rco-100m
51
52  reg:
53    maxItems: 1
54
55required:
56  - compatible
57  - '#clock-cells'
58  - reg
59
60additionalProperties: false
61
62examples:
63  - |
64    ap_clk: clock-controller@20200000 {
65      compatible = "sprd,ums512-ap-clk";
66      reg = <0x20200000 0x1000>;
67      clocks = <&ext_26m>;
68      clock-names = "ext-26m";
69      #clock-cells = <1>;
70    };
71...
72