1Binding for Texas Instruments APLL clock.
2
3Binding status: Unstable - ABI compatibility may be broken in the future
4
5This binding uses the common clock binding[1].  It assumes a
6register-mapped APLL with usually two selectable input clocks
7(reference clock and bypass clock), with analog phase locked
8loop logic for multiplying the input clock to a desired output
9clock. This clock also typically supports different operation
10modes (locked, low power stop etc.) APLL mostly behaves like
11a subtype of a DPLL [2], although a simplified one at that.
12
13[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
14[2] Documentation/devicetree/bindings/clock/ti/dpll.txt
15
16Required properties:
17- compatible : shall be "ti,dra7-apll-clock" or "ti,omap2-apll-clock"
18- #clock-cells : from common clock binding; shall be set to 0.
19- clocks : link phandles of parent clocks (clk-ref and clk-bypass)
20- reg : address and length of the register set for controlling the APLL.
21  It contains the information of registers in the following order:
22	"control" - contains the control register offset
23	"idlest" - contains the idlest register offset
24	"autoidle" - contains the autoidle register offset (OMAP2 only)
25- ti,clock-frequency : static clock frequency for the clock (OMAP2 only)
26- ti,idlest-shift : bit-shift for the idlest field (OMAP2 only)
27- ti,bit-shift : bit-shift for enable and autoidle fields (OMAP2 only)
28
29Examples:
30	apll_pcie_ck: apll_pcie_ck {
31		#clock-cells = <0>;
32		clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>;
33		reg = <0x021c>, <0x0220>;
34		compatible = "ti,dra7-apll-clock";
35	};
36
37	apll96_ck: apll96_ck {
38		#clock-cells = <0>;
39		compatible = "ti,omap2-apll-clock";
40		clocks = <&sys_ck>;
41		ti,bit-shift = <2>;
42		ti,idlest-shift = <8>;
43		ti,clock-frequency = <96000000>;
44		reg = <0x0500>, <0x0530>, <0x0520>;
45	};
46