1Binding for TI divider clock
2
3Binding status: Unstable - ABI compatibility may be broken in the future
4
5This binding uses the common clock binding[1].  It assumes a
6register-mapped adjustable clock rate divider that does not gate and has
7only one input clock or parent.  By default the value programmed into
8the register is one less than the actual divisor value.  E.g:
9
10register value		actual divisor value
110			1
121			2
132			3
14
15This assumption may be modified by the following optional properties:
16
17ti,index-starts-at-one - valid divisor values start at 1, not the default
18of 0.  E.g:
19register value		actual divisor value
201			1
212			2
223			3
23
24ti,index-power-of-two - valid divisor values are powers of two.  E.g:
25register value		actual divisor value
260			1
271			2
282			4
29
30Additionally an array of valid dividers may be supplied like so:
31
32	ti,dividers = <4>, <8>, <0>, <16>;
33
34Which will map the resulting values to a divisor table by their index:
35register value		actual divisor value
360			4
371			8
382			<invalid divisor, skipped>
393			16
40
41Any zero value in this array means the corresponding bit-value is invalid
42and must not be used.
43
44The binding must also provide the register to control the divider and
45unless the divider array is provided, min and max dividers. Optionally
46the number of bits to shift that mask, if necessary. If the shift value
47is missing it is the same as supplying a zero shift.
48
49This binding can also optionally provide support to the hardware autoidle
50feature, see [2].
51
52[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
53[2] Documentation/devicetree/bindings/clock/ti/autoidle.txt
54
55Required properties:
56- compatible : shall be "ti,divider-clock" or "ti,composite-divider-clock".
57- #clock-cells : from common clock binding; shall be set to 0.
58- clocks : link to phandle of parent clock
59- reg : offset for register controlling adjustable divider
60
61Optional properties:
62- clock-output-names : from common clock binding.
63- ti,dividers : array of integers defining divisors
64- ti,bit-shift : number of bits to shift the divider value, defaults to 0
65- ti,min-div : min divisor for dividing the input clock rate, only
66  needed if the first divisor is offset from the default value (1)
67- ti,max-div : max divisor for dividing the input clock rate, only needed
68  if ti,dividers is not defined.
69- ti,index-starts-at-one : valid divisor programming starts at 1, not zero,
70  only valid if ti,dividers is not defined.
71- ti,index-power-of-two : valid divisor programming must be a power of two,
72  only valid if ti,dividers is not defined.
73- ti,autoidle-shift : bit shift of the autoidle enable bit for the clock,
74  see [2]
75- ti,invert-autoidle-bit : autoidle is enabled by setting the bit to 0,
76  see [2]
77- ti,set-rate-parent : clk_set_rate is propagated to parent
78- ti,latch-bit : latch the divider value to HW, only needed if the register
79  access requires this. As an example dra76x DPLL_GMAC H14 divider implements
80  such behavior.
81
82Examples:
83dpll_usb_m2_ck: dpll_usb_m2_ck@4a008190 {
84	#clock-cells = <0>;
85	compatible = "ti,divider-clock";
86	clocks = <&dpll_usb_ck>;
87	ti,max-div = <127>;
88	reg = <0x190>;
89	ti,index-starts-at-one;
90};
91
92aess_fclk: aess_fclk@4a004528 {
93	#clock-cells = <0>;
94	compatible = "ti,divider-clock";
95	clocks = <&abe_clk>;
96	ti,bit-shift = <24>;
97	reg = <0x528>;
98	ti,max-div = <2>;
99};
100
101dpll_core_m3x2_div_ck: dpll_core_m3x2_div_ck {
102	#clock-cells = <0>;
103	compatible = "ti,composite-divider-clock";
104	clocks = <&dpll_core_x2_ck>;
105	ti,max-div = <31>;
106	reg = <0x0134>;
107	ti,index-starts-at-one;
108};
109
110ssi_ssr_div_fck_3430es2: ssi_ssr_div_fck_3430es2 {
111	#clock-cells = <0>;
112	compatible = "ti,composite-divider-clock";
113	clocks = <&corex2_fck>;
114	ti,bit-shift = <8>;
115	reg = <0x0a40>;
116	ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
117};
118