1c66ec88fSEmmanuel VadotBinding for Texas Instruments DPLL clock. 2c66ec88fSEmmanuel Vadot 3c66ec88fSEmmanuel VadotBinding status: Unstable - ABI compatibility may be broken in the future 4c66ec88fSEmmanuel Vadot 5c66ec88fSEmmanuel VadotThis binding uses the common clock binding[1]. It assumes a 6c66ec88fSEmmanuel Vadotregister-mapped DPLL with usually two selectable input clocks 7c66ec88fSEmmanuel Vadot(reference clock and bypass clock), with digital phase locked 8c66ec88fSEmmanuel Vadotloop logic for multiplying the input clock to a desired output 9c66ec88fSEmmanuel Vadotclock. This clock also typically supports different operation 10c66ec88fSEmmanuel Vadotmodes (locked, low power stop etc.) This binding has several 11c66ec88fSEmmanuel Vadotsub-types, which effectively result in slightly different setup 12c66ec88fSEmmanuel Vadotfor the actual DPLL clock. 13c66ec88fSEmmanuel Vadot 14c66ec88fSEmmanuel Vadot[1] Documentation/devicetree/bindings/clock/clock-bindings.txt 15c66ec88fSEmmanuel Vadot 16c66ec88fSEmmanuel VadotRequired properties: 17c66ec88fSEmmanuel Vadot- compatible : shall be one of: 18c66ec88fSEmmanuel Vadot "ti,omap3-dpll-clock", 19c66ec88fSEmmanuel Vadot "ti,omap3-dpll-core-clock", 20c66ec88fSEmmanuel Vadot "ti,omap3-dpll-per-clock", 21c66ec88fSEmmanuel Vadot "ti,omap3-dpll-per-j-type-clock", 22c66ec88fSEmmanuel Vadot "ti,omap4-dpll-clock", 23c66ec88fSEmmanuel Vadot "ti,omap4-dpll-x2-clock", 24c66ec88fSEmmanuel Vadot "ti,omap4-dpll-core-clock", 25c66ec88fSEmmanuel Vadot "ti,omap4-dpll-m4xen-clock", 26c66ec88fSEmmanuel Vadot "ti,omap4-dpll-j-type-clock", 27c66ec88fSEmmanuel Vadot "ti,omap5-mpu-dpll-clock", 28c66ec88fSEmmanuel Vadot "ti,am3-dpll-no-gate-clock", 29c66ec88fSEmmanuel Vadot "ti,am3-dpll-j-type-clock", 30c66ec88fSEmmanuel Vadot "ti,am3-dpll-no-gate-j-type-clock", 31c66ec88fSEmmanuel Vadot "ti,am3-dpll-clock", 32c66ec88fSEmmanuel Vadot "ti,am3-dpll-core-clock", 33c66ec88fSEmmanuel Vadot "ti,am3-dpll-x2-clock", 34c66ec88fSEmmanuel Vadot "ti,omap2-dpll-core-clock", 35c66ec88fSEmmanuel Vadot 36c66ec88fSEmmanuel Vadot- #clock-cells : from common clock binding; shall be set to 0. 37c66ec88fSEmmanuel Vadot- clocks : link phandles of parent clocks, first entry lists reference clock 38c66ec88fSEmmanuel Vadot and second entry bypass clock 39c66ec88fSEmmanuel Vadot- reg : offsets for the register set for controlling the DPLL. 40c66ec88fSEmmanuel Vadot Registers are listed in following order: 41c66ec88fSEmmanuel Vadot "control" - contains the control register base address 42c66ec88fSEmmanuel Vadot "idlest" - contains the idle status register base address 43c66ec88fSEmmanuel Vadot "mult-div1" - contains the multiplier / divider register base address 44c66ec88fSEmmanuel Vadot "autoidle" - contains the autoidle register base address (optional) 45*5956d97fSEmmanuel Vadot "ssc-deltam" - DPLL supports spread spectrum clocking (SSC), contains 46*5956d97fSEmmanuel Vadot the frequency spreading register base address (optional) 47*5956d97fSEmmanuel Vadot "ssc-modfreq" - DPLL supports spread spectrum clocking (SSC), contains 48*5956d97fSEmmanuel Vadot the modulation frequency register base address 49*5956d97fSEmmanuel Vadot (optional) 50c66ec88fSEmmanuel Vadot ti,am3-* dpll types do not have autoidle register 51c66ec88fSEmmanuel Vadot ti,omap2-* dpll type does not support idlest / autoidle registers 52c66ec88fSEmmanuel Vadot 53c66ec88fSEmmanuel VadotOptional properties: 54c66ec88fSEmmanuel Vadot- DPLL mode setting - defining any one or more of the following overrides 55c66ec88fSEmmanuel Vadot default setting. 56c66ec88fSEmmanuel Vadot - ti,low-power-stop : DPLL supports low power stop mode, gating output 57c66ec88fSEmmanuel Vadot - ti,low-power-bypass : DPLL output matches rate of parent bypass clock 58c66ec88fSEmmanuel Vadot - ti,lock : DPLL locks in programmed rate 59*5956d97fSEmmanuel Vadot - ti,min-div : the minimum divisor to start from to round the DPLL 60*5956d97fSEmmanuel Vadot target rate 61*5956d97fSEmmanuel Vadot - ti,ssc-deltam : DPLL supports spread spectrum clocking, frequency 62*5956d97fSEmmanuel Vadot spreading in permille (10th of a percent) 63*5956d97fSEmmanuel Vadot - ti,ssc-modfreq-hz : DPLL supports spread spectrum clocking, spread 64*5956d97fSEmmanuel Vadot spectrum modulation frequency 65*5956d97fSEmmanuel Vadot - ti,ssc-downspread : DPLL supports spread spectrum clocking, boolean 66*5956d97fSEmmanuel Vadot to enable the downspread feature 67c66ec88fSEmmanuel Vadot 68c66ec88fSEmmanuel VadotExamples: 69c66ec88fSEmmanuel Vadot dpll_core_ck: dpll_core_ck@44e00490 { 70c66ec88fSEmmanuel Vadot #clock-cells = <0>; 71c66ec88fSEmmanuel Vadot compatible = "ti,omap4-dpll-core-clock"; 72c66ec88fSEmmanuel Vadot clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; 73c66ec88fSEmmanuel Vadot reg = <0x490>, <0x45c>, <0x488>, <0x468>; 74c66ec88fSEmmanuel Vadot }; 75c66ec88fSEmmanuel Vadot 76c66ec88fSEmmanuel Vadot dpll2_ck: dpll2_ck@48004004 { 77c66ec88fSEmmanuel Vadot #clock-cells = <0>; 78c66ec88fSEmmanuel Vadot compatible = "ti,omap3-dpll-clock"; 79c66ec88fSEmmanuel Vadot clocks = <&sys_ck>, <&dpll2_fck>; 80c66ec88fSEmmanuel Vadot ti,low-power-stop; 81c66ec88fSEmmanuel Vadot ti,low-power-bypass; 82c66ec88fSEmmanuel Vadot ti,lock; 83c66ec88fSEmmanuel Vadot reg = <0x4>, <0x24>, <0x34>, <0x40>; 84c66ec88fSEmmanuel Vadot }; 85c66ec88fSEmmanuel Vadot 86c66ec88fSEmmanuel Vadot dpll_core_ck: dpll_core_ck@44e00490 { 87c66ec88fSEmmanuel Vadot #clock-cells = <0>; 88c66ec88fSEmmanuel Vadot compatible = "ti,am3-dpll-core-clock"; 89c66ec88fSEmmanuel Vadot clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; 90c66ec88fSEmmanuel Vadot reg = <0x90>, <0x5c>, <0x68>; 91c66ec88fSEmmanuel Vadot }; 92c66ec88fSEmmanuel Vadot 93c66ec88fSEmmanuel Vadot dpll_ck: dpll_ck { 94c66ec88fSEmmanuel Vadot #clock-cells = <0>; 95c66ec88fSEmmanuel Vadot compatible = "ti,omap2-dpll-core-clock"; 96c66ec88fSEmmanuel Vadot clocks = <&sys_ck>, <&sys_ck>; 97c66ec88fSEmmanuel Vadot reg = <0x0500>, <0x0540>; 98c66ec88fSEmmanuel Vadot }; 99*5956d97fSEmmanuel Vadot 100*5956d97fSEmmanuel Vadot dpll_disp_ck: dpll_disp_ck { 101*5956d97fSEmmanuel Vadot #clock-cells = <0>; 102*5956d97fSEmmanuel Vadot compatible = "ti,am3-dpll-no-gate-clock"; 103*5956d97fSEmmanuel Vadot clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; 104*5956d97fSEmmanuel Vadot reg = <0x0498>, <0x0448>, <0x0454>, <0x044c>, <0x0450>; 105*5956d97fSEmmanuel Vadot }; 106