1Binding for MediaTek's CPUFreq driver
2=====================================
3
4Required properties:
5- clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock names.
6- clock-names: Should contain the following:
7	"cpu"		- The multiplexer for clock input of CPU cluster.
8	"intermediate"	- A parent of "cpu" clock which is used as "intermediate" clock
9			  source (usually MAINPLL) when the original CPU PLL is under
10			  transition and not stable yet.
11	Please refer to Documentation/devicetree/bindings/clock/clock-bindings.txt for
12	generic clock consumer properties.
13- operating-points-v2: Please refer to Documentation/devicetree/bindings/opp/opp.txt
14	for detail.
15- proc-supply: Regulator for Vproc of CPU cluster.
16
17Optional properties:
18- sram-supply: Regulator for Vsram of CPU cluster. When present, the cpufreq driver
19	       needs to do "voltage tracking" to step by step scale up/down Vproc and
20	       Vsram to fit SoC specific needs. When absent, the voltage scaling
21	       flow is handled by hardware, hence no software "voltage tracking" is
22	       needed.
23- #cooling-cells:
24	For details, please refer to
25	Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml
26
27Example 1 (MT7623 SoC):
28
29	cpu_opp_table: opp_table {
30		compatible = "operating-points-v2";
31		opp-shared;
32
33		opp-598000000 {
34			opp-hz = /bits/ 64 <598000000>;
35			opp-microvolt = <1050000>;
36		};
37
38		opp-747500000 {
39			opp-hz = /bits/ 64 <747500000>;
40			opp-microvolt = <1050000>;
41		};
42
43		opp-1040000000 {
44			opp-hz = /bits/ 64 <1040000000>;
45			opp-microvolt = <1150000>;
46		};
47
48		opp-1196000000 {
49			opp-hz = /bits/ 64 <1196000000>;
50			opp-microvolt = <1200000>;
51		};
52
53		opp-1300000000 {
54			opp-hz = /bits/ 64 <1300000000>;
55			opp-microvolt = <1300000>;
56		};
57	};
58
59	cpu0: cpu@0 {
60		device_type = "cpu";
61		compatible = "arm,cortex-a7";
62		reg = <0x0>;
63		clocks = <&infracfg CLK_INFRA_CPUSEL>,
64			 <&apmixedsys CLK_APMIXED_MAINPLL>;
65		clock-names = "cpu", "intermediate";
66		operating-points-v2 = <&cpu_opp_table>;
67		#cooling-cells = <2>;
68	};
69	cpu@1 {
70		device_type = "cpu";
71		compatible = "arm,cortex-a7";
72		reg = <0x1>;
73		operating-points-v2 = <&cpu_opp_table>;
74	};
75	cpu@2 {
76		device_type = "cpu";
77		compatible = "arm,cortex-a7";
78		reg = <0x2>;
79		operating-points-v2 = <&cpu_opp_table>;
80	};
81	cpu@3 {
82		device_type = "cpu";
83		compatible = "arm,cortex-a7";
84		reg = <0x3>;
85		operating-points-v2 = <&cpu_opp_table>;
86	};
87
88Example 2 (MT8173 SoC):
89	cpu_opp_table_a: opp_table_a {
90		compatible = "operating-points-v2";
91		opp-shared;
92
93		opp-507000000 {
94			opp-hz = /bits/ 64 <507000000>;
95			opp-microvolt = <859000>;
96		};
97
98		opp-702000000 {
99			opp-hz = /bits/ 64 <702000000>;
100			opp-microvolt = <908000>;
101		};
102
103		opp-1001000000 {
104			opp-hz = /bits/ 64 <1001000000>;
105			opp-microvolt = <983000>;
106		};
107
108		opp-1105000000 {
109			opp-hz = /bits/ 64 <1105000000>;
110			opp-microvolt = <1009000>;
111		};
112
113		opp-1183000000 {
114			opp-hz = /bits/ 64 <1183000000>;
115			opp-microvolt = <1028000>;
116		};
117
118		opp-1404000000 {
119			opp-hz = /bits/ 64 <1404000000>;
120			opp-microvolt = <1083000>;
121		};
122
123		opp-1508000000 {
124			opp-hz = /bits/ 64 <1508000000>;
125			opp-microvolt = <1109000>;
126		};
127
128		opp-1573000000 {
129			opp-hz = /bits/ 64 <1573000000>;
130			opp-microvolt = <1125000>;
131		};
132	};
133
134	cpu_opp_table_b: opp_table_b {
135		compatible = "operating-points-v2";
136		opp-shared;
137
138		opp-507000000 {
139			opp-hz = /bits/ 64 <507000000>;
140			opp-microvolt = <828000>;
141		};
142
143		opp-702000000 {
144			opp-hz = /bits/ 64 <702000000>;
145			opp-microvolt = <867000>;
146		};
147
148		opp-1001000000 {
149			opp-hz = /bits/ 64 <1001000000>;
150			opp-microvolt = <927000>;
151		};
152
153		opp-1209000000 {
154			opp-hz = /bits/ 64 <1209000000>;
155			opp-microvolt = <968000>;
156		};
157
158		opp-1404000000 {
159			opp-hz = /bits/ 64 <1007000000>;
160			opp-microvolt = <1028000>;
161		};
162
163		opp-1612000000 {
164			opp-hz = /bits/ 64 <1612000000>;
165			opp-microvolt = <1049000>;
166		};
167
168		opp-1807000000 {
169			opp-hz = /bits/ 64 <1807000000>;
170			opp-microvolt = <1089000>;
171		};
172
173		opp-1989000000 {
174			opp-hz = /bits/ 64 <1989000000>;
175			opp-microvolt = <1125000>;
176		};
177	};
178
179	cpu0: cpu@0 {
180		device_type = "cpu";
181		compatible = "arm,cortex-a53";
182		reg = <0x000>;
183		enable-method = "psci";
184		cpu-idle-states = <&CPU_SLEEP_0>;
185		clocks = <&infracfg CLK_INFRA_CA53SEL>,
186			 <&apmixedsys CLK_APMIXED_MAINPLL>;
187		clock-names = "cpu", "intermediate";
188		operating-points-v2 = <&cpu_opp_table_a>;
189	};
190
191	cpu1: cpu@1 {
192		device_type = "cpu";
193		compatible = "arm,cortex-a53";
194		reg = <0x001>;
195		enable-method = "psci";
196		cpu-idle-states = <&CPU_SLEEP_0>;
197		clocks = <&infracfg CLK_INFRA_CA53SEL>,
198			 <&apmixedsys CLK_APMIXED_MAINPLL>;
199		clock-names = "cpu", "intermediate";
200		operating-points-v2 = <&cpu_opp_table_a>;
201	};
202
203	cpu2: cpu@100 {
204		device_type = "cpu";
205		compatible = "arm,cortex-a57";
206		reg = <0x100>;
207		enable-method = "psci";
208		cpu-idle-states = <&CPU_SLEEP_0>;
209		clocks = <&infracfg CLK_INFRA_CA57SEL>,
210			 <&apmixedsys CLK_APMIXED_MAINPLL>;
211		clock-names = "cpu", "intermediate";
212		operating-points-v2 = <&cpu_opp_table_b>;
213	};
214
215	cpu3: cpu@101 {
216		device_type = "cpu";
217		compatible = "arm,cortex-a57";
218		reg = <0x101>;
219		enable-method = "psci";
220		cpu-idle-states = <&CPU_SLEEP_0>;
221		clocks = <&infracfg CLK_INFRA_CA57SEL>,
222			 <&apmixedsys CLK_APMIXED_MAINPLL>;
223		clock-names = "cpu", "intermediate";
224		operating-points-v2 = <&cpu_opp_table_b>;
225	};
226
227	&cpu0 {
228		proc-supply = <&mt6397_vpca15_reg>;
229	};
230
231	&cpu1 {
232		proc-supply = <&mt6397_vpca15_reg>;
233	};
234
235	&cpu2 {
236		proc-supply = <&da9211_vcpu_reg>;
237		sram-supply = <&mt6397_vsramca7_reg>;
238	};
239
240	&cpu3 {
241		proc-supply = <&da9211_vcpu_reg>;
242		sram-supply = <&mt6397_vsramca7_reg>;
243	};
244