1Binding for MediaTek's CPUFreq driver
2=====================================
3
4Required properties:
5- clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock names.
6- clock-names: Should contain the following:
7	"cpu"		- The multiplexer for clock input of CPU cluster.
8	"intermediate"	- A parent of "cpu" clock which is used as "intermediate" clock
9			  source (usually MAINPLL) when the original CPU PLL is under
10			  transition and not stable yet.
11	Please refer to Documentation/devicetree/bindings/clock/clock-bindings.txt for
12	generic clock consumer properties.
13- operating-points-v2: Please refer to Documentation/devicetree/bindings/opp/opp-v2.yaml
14	for detail.
15- proc-supply: Regulator for Vproc of CPU cluster.
16
17Optional properties:
18- sram-supply: Regulator for Vsram of CPU cluster. When present, the cpufreq driver
19	       needs to do "voltage tracking" to step by step scale up/down Vproc and
20	       Vsram to fit SoC specific needs. When absent, the voltage scaling
21	       flow is handled by hardware, hence no software "voltage tracking" is
22	       needed.
23- mediatek,cci:
24	Used to confirm the link status between cpufreq and mediatek cci. Because
25	cpufreq and mediatek cci could share the same regulator in some MediaTek SoCs.
26	To prevent the issue of high frequency and low voltage, we need to use this
27	property to make sure mediatek cci is ready.
28	For details of mediatek cci, please refer to
29	Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml
30- #cooling-cells:
31	For details, please refer to
32	Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml
33
34Example 1 (MT7623 SoC):
35
36	cpu_opp_table: opp_table {
37		compatible = "operating-points-v2";
38		opp-shared;
39
40		opp-598000000 {
41			opp-hz = /bits/ 64 <598000000>;
42			opp-microvolt = <1050000>;
43		};
44
45		opp-747500000 {
46			opp-hz = /bits/ 64 <747500000>;
47			opp-microvolt = <1050000>;
48		};
49
50		opp-1040000000 {
51			opp-hz = /bits/ 64 <1040000000>;
52			opp-microvolt = <1150000>;
53		};
54
55		opp-1196000000 {
56			opp-hz = /bits/ 64 <1196000000>;
57			opp-microvolt = <1200000>;
58		};
59
60		opp-1300000000 {
61			opp-hz = /bits/ 64 <1300000000>;
62			opp-microvolt = <1300000>;
63		};
64	};
65
66	cpu0: cpu@0 {
67		device_type = "cpu";
68		compatible = "arm,cortex-a7";
69		reg = <0x0>;
70		clocks = <&infracfg CLK_INFRA_CPUSEL>,
71			 <&apmixedsys CLK_APMIXED_MAINPLL>;
72		clock-names = "cpu", "intermediate";
73		operating-points-v2 = <&cpu_opp_table>;
74		#cooling-cells = <2>;
75	};
76	cpu@1 {
77		device_type = "cpu";
78		compatible = "arm,cortex-a7";
79		reg = <0x1>;
80		operating-points-v2 = <&cpu_opp_table>;
81	};
82	cpu@2 {
83		device_type = "cpu";
84		compatible = "arm,cortex-a7";
85		reg = <0x2>;
86		operating-points-v2 = <&cpu_opp_table>;
87	};
88	cpu@3 {
89		device_type = "cpu";
90		compatible = "arm,cortex-a7";
91		reg = <0x3>;
92		operating-points-v2 = <&cpu_opp_table>;
93	};
94
95Example 2 (MT8173 SoC):
96	cpu_opp_table_a: opp_table_a {
97		compatible = "operating-points-v2";
98		opp-shared;
99
100		opp-507000000 {
101			opp-hz = /bits/ 64 <507000000>;
102			opp-microvolt = <859000>;
103		};
104
105		opp-702000000 {
106			opp-hz = /bits/ 64 <702000000>;
107			opp-microvolt = <908000>;
108		};
109
110		opp-1001000000 {
111			opp-hz = /bits/ 64 <1001000000>;
112			opp-microvolt = <983000>;
113		};
114
115		opp-1105000000 {
116			opp-hz = /bits/ 64 <1105000000>;
117			opp-microvolt = <1009000>;
118		};
119
120		opp-1183000000 {
121			opp-hz = /bits/ 64 <1183000000>;
122			opp-microvolt = <1028000>;
123		};
124
125		opp-1404000000 {
126			opp-hz = /bits/ 64 <1404000000>;
127			opp-microvolt = <1083000>;
128		};
129
130		opp-1508000000 {
131			opp-hz = /bits/ 64 <1508000000>;
132			opp-microvolt = <1109000>;
133		};
134
135		opp-1573000000 {
136			opp-hz = /bits/ 64 <1573000000>;
137			opp-microvolt = <1125000>;
138		};
139	};
140
141	cpu_opp_table_b: opp_table_b {
142		compatible = "operating-points-v2";
143		opp-shared;
144
145		opp-507000000 {
146			opp-hz = /bits/ 64 <507000000>;
147			opp-microvolt = <828000>;
148		};
149
150		opp-702000000 {
151			opp-hz = /bits/ 64 <702000000>;
152			opp-microvolt = <867000>;
153		};
154
155		opp-1001000000 {
156			opp-hz = /bits/ 64 <1001000000>;
157			opp-microvolt = <927000>;
158		};
159
160		opp-1209000000 {
161			opp-hz = /bits/ 64 <1209000000>;
162			opp-microvolt = <968000>;
163		};
164
165		opp-1404000000 {
166			opp-hz = /bits/ 64 <1007000000>;
167			opp-microvolt = <1028000>;
168		};
169
170		opp-1612000000 {
171			opp-hz = /bits/ 64 <1612000000>;
172			opp-microvolt = <1049000>;
173		};
174
175		opp-1807000000 {
176			opp-hz = /bits/ 64 <1807000000>;
177			opp-microvolt = <1089000>;
178		};
179
180		opp-1989000000 {
181			opp-hz = /bits/ 64 <1989000000>;
182			opp-microvolt = <1125000>;
183		};
184	};
185
186	cpu0: cpu@0 {
187		device_type = "cpu";
188		compatible = "arm,cortex-a53";
189		reg = <0x000>;
190		enable-method = "psci";
191		cpu-idle-states = <&CPU_SLEEP_0>;
192		clocks = <&infracfg CLK_INFRA_CA53SEL>,
193			 <&apmixedsys CLK_APMIXED_MAINPLL>;
194		clock-names = "cpu", "intermediate";
195		operating-points-v2 = <&cpu_opp_table_a>;
196	};
197
198	cpu1: cpu@1 {
199		device_type = "cpu";
200		compatible = "arm,cortex-a53";
201		reg = <0x001>;
202		enable-method = "psci";
203		cpu-idle-states = <&CPU_SLEEP_0>;
204		clocks = <&infracfg CLK_INFRA_CA53SEL>,
205			 <&apmixedsys CLK_APMIXED_MAINPLL>;
206		clock-names = "cpu", "intermediate";
207		operating-points-v2 = <&cpu_opp_table_a>;
208	};
209
210	cpu2: cpu@100 {
211		device_type = "cpu";
212		compatible = "arm,cortex-a72";
213		reg = <0x100>;
214		enable-method = "psci";
215		cpu-idle-states = <&CPU_SLEEP_0>;
216		clocks = <&infracfg CLK_INFRA_CA72SEL>,
217			 <&apmixedsys CLK_APMIXED_MAINPLL>;
218		clock-names = "cpu", "intermediate";
219		operating-points-v2 = <&cpu_opp_table_b>;
220	};
221
222	cpu3: cpu@101 {
223		device_type = "cpu";
224		compatible = "arm,cortex-a72";
225		reg = <0x101>;
226		enable-method = "psci";
227		cpu-idle-states = <&CPU_SLEEP_0>;
228		clocks = <&infracfg CLK_INFRA_CA72SEL>,
229			 <&apmixedsys CLK_APMIXED_MAINPLL>;
230		clock-names = "cpu", "intermediate";
231		operating-points-v2 = <&cpu_opp_table_b>;
232	};
233
234	&cpu0 {
235		proc-supply = <&mt6397_vpca15_reg>;
236	};
237
238	&cpu1 {
239		proc-supply = <&mt6397_vpca15_reg>;
240	};
241
242	&cpu2 {
243		proc-supply = <&da9211_vcpu_reg>;
244		sram-supply = <&mt6397_vsramca7_reg>;
245	};
246
247	&cpu3 {
248		proc-supply = <&da9211_vcpu_reg>;
249		sram-supply = <&mt6397_vsramca7_reg>;
250	};
251