1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/allwinner,sun8i-a83t-dw-hdmi.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Allwinner A83t DWC HDMI TX Encoder Device Tree Bindings
8
9description: |
10  The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller
11  IP with Allwinner\'s own PHY IP. It supports audio and video outputs
12  and CEC.
13
14  These DT bindings follow the Synopsys DWC HDMI TX bindings defined
15  in bridge/synopsys,dw-hdmi.yaml with the following device-specific
16  properties.
17
18maintainers:
19  - Chen-Yu Tsai <wens@csie.org>
20  - Maxime Ripard <mripard@kernel.org>
21
22properties:
23  "#phy-cells":
24    const: 0
25
26  compatible:
27    oneOf:
28      - const: allwinner,sun8i-a83t-dw-hdmi
29      - const: allwinner,sun50i-h6-dw-hdmi
30
31      - items:
32          - enum:
33              - allwinner,sun8i-h3-dw-hdmi
34              - allwinner,sun8i-r40-dw-hdmi
35              - allwinner,sun50i-a64-dw-hdmi
36          - const: allwinner,sun8i-a83t-dw-hdmi
37
38  reg:
39    maxItems: 1
40
41  reg-io-width:
42    const: 1
43
44  interrupts:
45    maxItems: 1
46
47  clocks:
48    minItems: 3
49    maxItems: 6
50    items:
51      - description: Bus Clock
52      - description: Register Clock
53      - description: TMDS Clock
54      - description: HDMI CEC Clock
55      - description: HDCP Clock
56      - description: HDCP Bus Clock
57
58  clock-names:
59    minItems: 3
60    maxItems: 6
61    items:
62      - const: iahb
63      - const: isfr
64      - const: tmds
65      - const: cec
66      - const: hdcp
67      - const: hdcp-bus
68
69  resets:
70    minItems: 1
71    maxItems: 2
72    items:
73      - description: HDMI Controller Reset
74      - description: HDCP Reset
75
76  reset-names:
77    minItems: 1
78    maxItems: 2
79    items:
80      - const: ctrl
81      - const: hdcp
82
83  phys:
84    maxItems: 1
85    description:
86      Phandle to the DWC HDMI PHY.
87
88  phy-names:
89    const: phy
90
91  hvcc-supply:
92    description:
93      The VCC power supply of the controller
94
95  ports:
96    $ref: /schemas/graph.yaml#/properties/ports
97
98    properties:
99      port@0:
100        $ref: /schemas/graph.yaml#/properties/port
101        description: |
102          Input endpoints of the controller. Usually the associated
103          TCON.
104
105      port@1:
106        $ref: /schemas/graph.yaml#/properties/port
107        description: |
108          Output endpoints of the controller. Usually an HDMI
109          connector.
110
111    required:
112      - port@0
113      - port@1
114
115required:
116  - compatible
117  - reg
118  - reg-io-width
119  - interrupts
120  - clocks
121  - clock-names
122  - resets
123  - reset-names
124  - phys
125  - phy-names
126  - ports
127
128if:
129  properties:
130    compatible:
131      contains:
132        enum:
133          - allwinner,sun50i-h6-dw-hdmi
134
135then:
136  properties:
137    clocks:
138      minItems: 6
139
140    clock-names:
141      minItems: 6
142
143    resets:
144      minItems: 2
145
146    reset-names:
147      minItems: 2
148
149
150additionalProperties: false
151
152examples:
153  - |
154    #include <dt-bindings/interrupt-controller/arm-gic.h>
155
156    /*
157     * This comes from the clock/sun8i-a83t-ccu.h and
158     * reset/sun8i-a83t-ccu.h headers, but we can't include them since
159     * it would trigger a bunch of warnings for redefinitions of
160     * symbols with the other example.
161     */
162    #define CLK_BUS_HDMI	39
163    #define CLK_HDMI		93
164    #define CLK_HDMI_SLOW	94
165    #define RST_BUS_HDMI1	26
166
167    hdmi@1ee0000 {
168        compatible = "allwinner,sun8i-a83t-dw-hdmi";
169        reg = <0x01ee0000 0x10000>;
170        reg-io-width = <1>;
171        interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
172        clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>,
173                 <&ccu CLK_HDMI>;
174        clock-names = "iahb", "isfr", "tmds";
175        resets = <&ccu RST_BUS_HDMI1>;
176        reset-names = "ctrl";
177        phys = <&hdmi_phy>;
178        phy-names = "phy";
179        pinctrl-names = "default";
180        pinctrl-0 = <&hdmi_pins>;
181        status = "disabled";
182
183        ports {
184            #address-cells = <1>;
185            #size-cells = <0>;
186
187            port@0 {
188                reg = <0>;
189
190                endpoint {
191                    remote-endpoint = <&tcon1_out_hdmi>;
192                };
193            };
194
195            port@1 {
196                reg = <1>;
197            };
198        };
199    };
200
201    /* Cleanup after ourselves */
202    #undef CLK_BUS_HDMI
203    #undef CLK_HDMI
204    #undef CLK_HDMI_SLOW
205
206  - |
207    #include <dt-bindings/interrupt-controller/arm-gic.h>
208
209    /*
210     * This comes from the clock/sun50i-h6-ccu.h and
211     * reset/sun50i-h6-ccu.h headers, but we can't include them since
212     * it would trigger a bunch of warnings for redefinitions of
213     * symbols with the other example.
214     */
215    #define CLK_BUS_HDMI	126
216    #define CLK_BUS_HDCP	137
217    #define CLK_HDMI		123
218    #define CLK_HDMI_SLOW	124
219    #define CLK_HDMI_CEC	125
220    #define CLK_HDCP		136
221    #define RST_BUS_HDMI_SUB	57
222    #define RST_BUS_HDCP	62
223
224    hdmi@6000000 {
225        compatible = "allwinner,sun50i-h6-dw-hdmi";
226        reg = <0x06000000 0x10000>;
227        reg-io-width = <1>;
228        interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
229        clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>,
230                 <&ccu CLK_HDMI>, <&ccu CLK_HDMI_CEC>,
231                 <&ccu CLK_HDCP>, <&ccu CLK_BUS_HDCP>;
232        clock-names = "iahb", "isfr", "tmds", "cec", "hdcp",
233                      "hdcp-bus";
234        resets = <&ccu RST_BUS_HDMI_SUB>, <&ccu RST_BUS_HDCP>;
235        reset-names = "ctrl", "hdcp";
236        phys = <&hdmi_phy>;
237        phy-names = "phy";
238        pinctrl-names = "default";
239        pinctrl-0 = <&hdmi_pins>;
240        status = "disabled";
241
242        ports {
243            #address-cells = <1>;
244            #size-cells = <0>;
245
246            port@0 {
247                reg = <0>;
248
249                endpoint {
250                    remote-endpoint = <&tcon_top_hdmi_out_hdmi>;
251                };
252            };
253
254            port@1 {
255                reg = <1>;
256            };
257        };
258    };
259
260...
261