1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/allwinner,sun8i-a83t-hdmi-phy.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Allwinner A83t HDMI PHY
8
9maintainers:
10  - Chen-Yu Tsai <wens@csie.org>
11  - Maxime Ripard <mripard@kernel.org>
12
13properties:
14  "#phy-cells":
15    const: 0
16
17  compatible:
18    enum:
19      - allwinner,sun8i-a83t-hdmi-phy
20      - allwinner,sun8i-h3-hdmi-phy
21      - allwinner,sun8i-r40-hdmi-phy
22      - allwinner,sun50i-a64-hdmi-phy
23      - allwinner,sun50i-h6-hdmi-phy
24
25  reg:
26    maxItems: 1
27
28  clocks:
29    minItems: 2
30    items:
31      - description: Bus Clock
32      - description: Module Clock
33      - description: Parent of the PHY clock
34      - description: Second possible parent of the PHY clock
35
36  clock-names:
37    minItems: 2
38    items:
39      - const: bus
40      - const: mod
41      - const: pll-0
42      - const: pll-1
43
44  resets:
45    maxItems: 1
46
47  reset-names:
48    const: phy
49
50required:
51  - compatible
52  - reg
53  - clocks
54  - clock-names
55  - resets
56  - reset-names
57
58if:
59  properties:
60    compatible:
61      contains:
62        enum:
63          - allwinner,sun8i-r40-hdmi-phy
64
65then:
66  properties:
67    clocks:
68      minItems: 4
69
70    clock-names:
71      minItems: 4
72
73else:
74  if:
75    properties:
76      compatible:
77        contains:
78          enum:
79            - allwinner,sun8i-h3-hdmi-phy
80            - allwinner,sun50i-a64-hdmi-phy
81
82  then:
83    properties:
84      clocks:
85        minItems: 3
86
87      clock-names:
88        minItems: 3
89
90  else:
91    properties:
92      clocks:
93        maxItems: 2
94
95      clock-names:
96        maxItems: 2
97
98additionalProperties: false
99
100examples:
101  - |
102    #include <dt-bindings/clock/sun8i-a83t-ccu.h>
103    #include <dt-bindings/reset/sun8i-a83t-ccu.h>
104
105    hdmi_phy: hdmi-phy@1ef0000 {
106        compatible = "allwinner,sun8i-a83t-hdmi-phy";
107        reg = <0x01ef0000 0x10000>;
108        clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>;
109        clock-names = "bus", "mod";
110        resets = <&ccu RST_BUS_HDMI0>;
111        reset-names = "phy";
112        #phy-cells = <0>;
113    };
114
115...
116