1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/bridge/renesas,lvds.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Renesas R-Car LVDS Encoder
8
9maintainers:
10  - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
11
12description: |
13  These DT bindings describe the LVDS encoder embedded in the Renesas R-Car
14  Gen2, R-Car Gen3, RZ/G1 and RZ/G2 SoCs.
15
16properties:
17  compatible:
18    enum:
19      - renesas,r8a7742-lvds # for RZ/G1H compatible LVDS encoders
20      - renesas,r8a7743-lvds # for RZ/G1M compatible LVDS encoders
21      - renesas,r8a7744-lvds # for RZ/G1N compatible LVDS encoders
22      - renesas,r8a774a1-lvds # for RZ/G2M compatible LVDS encoders
23      - renesas,r8a774b1-lvds # for RZ/G2N compatible LVDS encoders
24      - renesas,r8a774c0-lvds # for RZ/G2E compatible LVDS encoders
25      - renesas,r8a774e1-lvds # for RZ/G2H compatible LVDS encoders
26      - renesas,r8a7790-lvds # for R-Car H2 compatible LVDS encoders
27      - renesas,r8a7791-lvds # for R-Car M2-W compatible LVDS encoders
28      - renesas,r8a7793-lvds # for R-Car M2-N compatible LVDS encoders
29      - renesas,r8a7795-lvds # for R-Car H3 compatible LVDS encoders
30      - renesas,r8a7796-lvds # for R-Car M3-W compatible LVDS encoders
31      - renesas,r8a77965-lvds # for R-Car M3-N compatible LVDS encoders
32      - renesas,r8a77970-lvds # for R-Car V3M compatible LVDS encoders
33      - renesas,r8a77980-lvds # for R-Car V3H compatible LVDS encoders
34      - renesas,r8a77990-lvds # for R-Car E3 compatible LVDS encoders
35      - renesas,r8a77995-lvds # for R-Car D3 compatible LVDS encoders
36
37  reg:
38    maxItems: 1
39
40  clocks:
41    minItems: 1
42    maxItems: 4
43
44  clock-names:
45    minItems: 1
46    maxItems: 4
47
48  resets:
49    maxItems: 1
50
51  ports:
52    type: object
53    description: |
54      This device has two video ports. Their connections are modelled using the
55      OF graph bindings specified in Documentation/devicetree/bindings/graph.txt.
56      Each port shall have a single endpoint.
57
58    properties:
59      '#address-cells':
60        const: 1
61
62      '#size-cells':
63        const: 0
64
65      port@0:
66        type: object
67        description: Parallel RGB input port
68
69      port@1:
70        type: object
71        description: LVDS output port
72
73    required:
74      - port@0
75      - port@1
76
77    additionalProperties: false
78
79  power-domains:
80    maxItems: 1
81
82  renesas,companion:
83    $ref: /schemas/types.yaml#/definitions/phandle
84    description:
85      phandle to the companion LVDS encoder. This property is mandatory
86      for the first LVDS encoder on D3 and E3 SoCs, and shall point to
87      the second encoder to be used as a companion in dual-link mode. It
88      shall not be set for any other LVDS encoder.
89
90required:
91  - compatible
92  - reg
93  - clocks
94  - power-domains
95  - resets
96  - ports
97
98if:
99  properties:
100    compatible:
101      enum:
102        - renesas,r8a774c0-lvds
103        - renesas,r8a77990-lvds
104        - renesas,r8a77995-lvds
105then:
106  properties:
107    clocks:
108      minItems: 1
109      maxItems: 4
110      items:
111        - description: Functional clock
112        - description: EXTAL input clock
113        - description: DU_DOTCLKIN0 input clock
114        - description: DU_DOTCLKIN1 input clock
115
116    clock-names:
117      minItems: 1
118      maxItems: 4
119      items:
120        - const: fck
121        # The LVDS encoder can use the EXTAL or DU_DOTCLKINx clocks.
122        # These clocks are optional.
123        - enum:
124            - extal
125            - dclkin.0
126            - dclkin.1
127        - enum:
128            - extal
129            - dclkin.0
130            - dclkin.1
131        - enum:
132            - extal
133            - dclkin.0
134            - dclkin.1
135
136  required:
137    - clock-names
138
139else:
140  properties:
141    clocks:
142      maxItems: 1
143      items:
144        - description: Functional clock
145
146    clock-names:
147      maxItems: 1
148      items:
149        - const: fck
150
151    renesas,companion: false
152
153additionalProperties: false
154
155examples:
156  - |
157    #include <dt-bindings/clock/renesas-cpg-mssr.h>
158    #include <dt-bindings/power/r8a7795-sysc.h>
159
160    lvds@feb90000 {
161        compatible = "renesas,r8a7795-lvds";
162        reg = <0xfeb90000 0x14>;
163        clocks = <&cpg CPG_MOD 727>;
164        power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
165        resets = <&cpg 727>;
166
167        ports {
168            #address-cells = <1>;
169            #size-cells = <0>;
170
171            port@0 {
172                reg = <0>;
173                lvds_in: endpoint {
174                    remote-endpoint = <&du_out_lvds0>;
175                };
176            };
177            port@1 {
178                reg = <1>;
179                lvds_out: endpoint {
180                    remote-endpoint = <&panel_in>;
181                };
182            };
183        };
184    };
185
186  - |
187    #include <dt-bindings/clock/renesas-cpg-mssr.h>
188    #include <dt-bindings/power/r8a77990-sysc.h>
189
190    lvds0: lvds@feb90000 {
191        compatible = "renesas,r8a77990-lvds";
192        reg = <0xfeb90000 0x20>;
193        clocks = <&cpg CPG_MOD 727>,
194                 <&x13_clk>,
195                 <&extal_clk>;
196        clock-names = "fck", "dclkin.0", "extal";
197        power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
198        resets = <&cpg 727>;
199
200        renesas,companion = <&lvds1>;
201
202        ports {
203            #address-cells = <1>;
204            #size-cells = <0>;
205
206            port@0 {
207                reg = <0>;
208                lvds0_in: endpoint {
209                    remote-endpoint = <&du_out_lvds0>;
210                };
211            };
212            port@1 {
213                reg = <1>;
214                lvds0_out: endpoint {
215                    remote-endpoint = <&panel_in1>;
216                };
217            };
218        };
219    };
220
221    lvds1: lvds@feb90100 {
222        compatible = "renesas,r8a77990-lvds";
223        reg = <0xfeb90100 0x20>;
224        clocks = <&cpg CPG_MOD 727>,
225                 <&x13_clk>,
226                 <&extal_clk>;
227        clock-names = "fck", "dclkin.0", "extal";
228        power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
229        resets = <&cpg 726>;
230
231        ports {
232            #address-cells = <1>;
233            #size-cells = <0>;
234
235            port@0 {
236                reg = <0>;
237                lvds1_in: endpoint {
238                    remote-endpoint = <&du_out_lvds1>;
239                };
240            };
241            port@1 {
242                reg = <1>;
243                lvds1_out: endpoint {
244                    remote-endpoint = <&panel_in2>;
245                };
246            };
247        };
248    };
249
250...
251