1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/bridge/synopsys,dw-hdmi.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Common Properties for Synopsys DesignWare HDMI TX Controller
8
9maintainers:
10  - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
11
12description: |
13  This document defines device tree properties for the Synopsys DesignWare HDMI
14  TX controller (DWC HDMI TX) IP core. It doesn't constitute a full device tree
15  binding specification by itself but is meant to be referenced by device tree
16  bindings for the platform-specific integrations of the DWC HDMI TX.
17
18  When referenced from platform device tree bindings the properties defined in
19  this document are defined as follows. The platform device tree bindings are
20  responsible for defining whether each property is required or optional.
21
22properties:
23  reg:
24    maxItems: 1
25
26  reg-io-width:
27    description:
28      Width (in bytes) of the registers specified by the reg property.
29    $ref: /schemas/types.yaml#/definitions/uint32
30    enum: [1, 4]
31    default: 1
32
33  clocks:
34    minItems: 2
35    maxItems: 5
36    items:
37      - description: The bus clock for either AHB and APB
38      - description: The internal register configuration clock
39    additionalItems: true
40
41  clock-names:
42    minItems: 2
43    maxItems: 5
44    items:
45      - const: iahb
46      - const: isfr
47    additionalItems: true
48
49  interrupts:
50    maxItems: 1
51
52additionalProperties: true
53
54...
55