1Exynos MIPI DSI Master
2
3Required properties:
4  - compatible: value should be one of the following
5		"samsung,exynos3250-mipi-dsi" /* for Exynos3250/3472 SoCs */
6		"samsung,exynos4210-mipi-dsi" /* for Exynos4 SoCs */
7		"samsung,exynos5410-mipi-dsi" /* for Exynos5410/5420/5440 SoCs */
8		"samsung,exynos5422-mipi-dsi" /* for Exynos5422/5800 SoCs */
9		"samsung,exynos5433-mipi-dsi" /* for Exynos5433 SoCs */
10  - reg: physical base address and length of the registers set for the device
11  - interrupts: should contain DSI interrupt
12  - clocks: list of clock specifiers, must contain an entry for each required
13    entry in clock-names
14  - clock-names: should include "bus_clk"and "sclk_mipi" entries
15		 the use of "pll_clk" is deprecated
16  - phys: list of phy specifiers, must contain an entry for each required
17    entry in phy-names
18  - phy-names: should include "dsim" entry
19  - vddcore-supply: MIPI DSIM Core voltage supply (e.g. 1.1V)
20  - vddio-supply: MIPI DSIM I/O and PLL voltage supply (e.g. 1.8V)
21  - samsung,pll-clock-frequency: specifies frequency of the oscillator clock
22  - #address-cells, #size-cells: should be set respectively to <1> and <0>
23    according to DSI host bindings (see MIPI DSI bindings [1])
24  - samsung,burst-clock-frequency: specifies DSI frequency in high-speed burst
25    mode
26  - samsung,esc-clock-frequency: specifies DSI frequency in escape mode
27
28Optional properties:
29  - power-domains: a phandle to DSIM power domain node
30
31Child nodes:
32  Should contain DSI peripheral nodes (see MIPI DSI bindings [1]).
33
34Video interfaces:
35  Device node can contain following video interface port nodes according to [2]:
36  0: RGB input,
37  1: DSI output
38
39[1]: Documentation/devicetree/bindings/display/mipi-dsi-bus.txt
40[2]: Documentation/devicetree/bindings/media/video-interfaces.txt
41
42Example:
43
44	dsi@11c80000 {
45		compatible = "samsung,exynos4210-mipi-dsi";
46		reg = <0x11C80000 0x10000>;
47		interrupts = <0 79 0>;
48		clocks = <&clock 286>, <&clock 143>;
49		clock-names = "bus_clk", "sclk_mipi";
50		phys = <&mipi_phy 1>;
51		phy-names = "dsim";
52		vddcore-supply = <&vusb_reg>;
53		vddio-supply = <&vmipi_reg>;
54		power-domains = <&pd_lcd0>;
55		#address-cells = <1>;
56		#size-cells = <0>;
57		samsung,pll-clock-frequency = <24000000>;
58
59		panel@1 {
60			reg = <0>;
61			...
62			port {
63				panel_ep: endpoint {
64					remote-endpoint = <&dsi_ep>;
65				};
66			};
67		};
68
69		ports {
70			#address-cells = <1>;
71			#size-cells = <0>;
72
73			port@0 {
74				reg = <0>;
75				decon_to_mic: endpoint {
76					remote-endpoint = <&mic_to_decon>;
77				};
78			};
79
80			port@1 {
81				reg = <1>;
82				dsi_ep: endpoint {
83					reg = <0>;
84					samsung,burst-clock-frequency = <500000000>;
85					samsung,esc-clock-frequency = <20000000>;
86					remote-endpoint = <&panel_ep>;
87				};
88			};
89		};
90	};
91