1Mediatek display subsystem 2========================== 3 4The Mediatek display subsystem consists of various DISP function blocks in the 5MMSYS register space. The connections between them can be configured by output 6and input selectors in the MMSYS_CONFIG register space. Pixel clock and start 7of frame signal are distributed to the other function blocks by a DISP_MUTEX 8function block. 9 10All DISP device tree nodes must be siblings to the central MMSYS_CONFIG node. 11For a description of the MMSYS_CONFIG binding, see 12Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt. 13 14DISP function blocks 15==================== 16 17A display stream starts at a source function block that reads pixel data from 18memory and ends with a sink function block that drives pixels on a display 19interface, or writes pixels back to memory. All DISP function blocks have 20their own register space, interrupt, and clock gate. The blocks that can 21access memory additionally have to list the IOMMU and local arbiter they are 22connected to. 23 24For a description of the display interface sink function blocks, see 25Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt and 26Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt. 27 28Required properties (all function blocks): 29- compatible: "mediatek,<chip>-disp-<function>", one of 30 "mediatek,<chip>-disp-ovl" - overlay (4 layers, blending, csc) 31 "mediatek,<chip>-disp-ovl-2l" - overlay (2 layers, blending, csc) 32 "mediatek,<chip>-disp-rdma" - read DMA / line buffer 33 "mediatek,<chip>-disp-wdma" - write DMA 34 "mediatek,<chip>-disp-ccorr" - color correction 35 "mediatek,<chip>-disp-color" - color processor 36 "mediatek,<chip>-disp-dither" - dither 37 "mediatek,<chip>-disp-aal" - adaptive ambient light controller 38 "mediatek,<chip>-disp-gamma" - gamma correction 39 "mediatek,<chip>-disp-merge" - merge streams from two RDMA sources 40 "mediatek,<chip>-disp-split" - split stream to two encoders 41 "mediatek,<chip>-disp-ufoe" - data compression engine 42 "mediatek,<chip>-dsi" - DSI controller, see mediatek,dsi.txt 43 "mediatek,<chip>-dpi" - DPI controller, see mediatek,dpi.txt 44 "mediatek,<chip>-disp-mutex" - display mutex 45 "mediatek,<chip>-disp-od" - overdrive 46 the supported chips are mt2701, mt2712 and mt8173. 47- reg: Physical base address and length of the function block register space 48- interrupts: The interrupt signal from the function block (required, except for 49 merge and split function blocks). 50- clocks: device clocks 51 See Documentation/devicetree/bindings/clock/clock-bindings.txt for details. 52 For most function blocks this is just a single clock input. Only the DSI and 53 DPI controller nodes have multiple clock inputs. These are documented in 54 mediatek,dsi.txt and mediatek,dpi.txt, respectively. 55 An exception is that the mt8183 mutex is always free running with no clocks property. 56 57Required properties (DMA function blocks): 58- compatible: Should be one of 59 "mediatek,<chip>-disp-ovl" 60 "mediatek,<chip>-disp-rdma" 61 "mediatek,<chip>-disp-wdma" 62 the supported chips are mt2701 and mt8173. 63- larb: Should contain a phandle pointing to the local arbiter device as defined 64 in Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt 65- iommus: Should point to the respective IOMMU block with master port as 66 argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt 67 for details. 68 69Examples: 70 71mmsys: clock-controller@14000000 { 72 compatible = "mediatek,mt8173-mmsys", "syscon"; 73 reg = <0 0x14000000 0 0x1000>; 74 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 75 #clock-cells = <1>; 76}; 77 78ovl0: ovl@1400c000 { 79 compatible = "mediatek,mt8173-disp-ovl"; 80 reg = <0 0x1400c000 0 0x1000>; 81 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>; 82 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 83 clocks = <&mmsys CLK_MM_DISP_OVL0>; 84 iommus = <&iommu M4U_PORT_DISP_OVL0>; 85 mediatek,larb = <&larb0>; 86}; 87 88ovl1: ovl@1400d000 { 89 compatible = "mediatek,mt8173-disp-ovl"; 90 reg = <0 0x1400d000 0 0x1000>; 91 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_LOW>; 92 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 93 clocks = <&mmsys CLK_MM_DISP_OVL1>; 94 iommus = <&iommu M4U_PORT_DISP_OVL1>; 95 mediatek,larb = <&larb4>; 96}; 97 98rdma0: rdma@1400e000 { 99 compatible = "mediatek,mt8173-disp-rdma"; 100 reg = <0 0x1400e000 0 0x1000>; 101 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>; 102 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 103 clocks = <&mmsys CLK_MM_DISP_RDMA0>; 104 iommus = <&iommu M4U_PORT_DISP_RDMA0>; 105 mediatek,larb = <&larb0>; 106}; 107 108rdma1: rdma@1400f000 { 109 compatible = "mediatek,mt8173-disp-rdma"; 110 reg = <0 0x1400f000 0 0x1000>; 111 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_LOW>; 112 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 113 clocks = <&mmsys CLK_MM_DISP_RDMA1>; 114 iommus = <&iommu M4U_PORT_DISP_RDMA1>; 115 mediatek,larb = <&larb4>; 116}; 117 118rdma2: rdma@14010000 { 119 compatible = "mediatek,mt8173-disp-rdma"; 120 reg = <0 0x14010000 0 0x1000>; 121 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>; 122 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 123 clocks = <&mmsys CLK_MM_DISP_RDMA2>; 124 iommus = <&iommu M4U_PORT_DISP_RDMA2>; 125 mediatek,larb = <&larb4>; 126}; 127 128wdma0: wdma@14011000 { 129 compatible = "mediatek,mt8173-disp-wdma"; 130 reg = <0 0x14011000 0 0x1000>; 131 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>; 132 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 133 clocks = <&mmsys CLK_MM_DISP_WDMA0>; 134 iommus = <&iommu M4U_PORT_DISP_WDMA0>; 135 mediatek,larb = <&larb0>; 136}; 137 138wdma1: wdma@14012000 { 139 compatible = "mediatek,mt8173-disp-wdma"; 140 reg = <0 0x14012000 0 0x1000>; 141 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>; 142 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 143 clocks = <&mmsys CLK_MM_DISP_WDMA1>; 144 iommus = <&iommu M4U_PORT_DISP_WDMA1>; 145 mediatek,larb = <&larb4>; 146}; 147 148color0: color@14013000 { 149 compatible = "mediatek,mt8173-disp-color"; 150 reg = <0 0x14013000 0 0x1000>; 151 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>; 152 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 153 clocks = <&mmsys CLK_MM_DISP_COLOR0>; 154}; 155 156color1: color@14014000 { 157 compatible = "mediatek,mt8173-disp-color"; 158 reg = <0 0x14014000 0 0x1000>; 159 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>; 160 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 161 clocks = <&mmsys CLK_MM_DISP_COLOR1>; 162}; 163 164aal@14015000 { 165 compatible = "mediatek,mt8173-disp-aal"; 166 reg = <0 0x14015000 0 0x1000>; 167 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>; 168 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 169 clocks = <&mmsys CLK_MM_DISP_AAL>; 170}; 171 172gamma@14016000 { 173 compatible = "mediatek,mt8173-disp-gamma"; 174 reg = <0 0x14016000 0 0x1000>; 175 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>; 176 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 177 clocks = <&mmsys CLK_MM_DISP_GAMMA>; 178}; 179 180ufoe@1401a000 { 181 compatible = "mediatek,mt8173-disp-ufoe"; 182 reg = <0 0x1401a000 0 0x1000>; 183 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>; 184 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 185 clocks = <&mmsys CLK_MM_DISP_UFOE>; 186}; 187 188dsi0: dsi@1401b000 { 189 /* See mediatek,dsi.txt for details */ 190}; 191 192dpi0: dpi@1401d000 { 193 /* See mediatek,dpi.txt for details */ 194}; 195 196mutex: mutex@14020000 { 197 compatible = "mediatek,mt8173-disp-mutex"; 198 reg = <0 0x14020000 0 0x1000>; 199 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>; 200 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 201 clocks = <&mmsys CLK_MM_MUTEX_32K>; 202}; 203 204od@14023000 { 205 compatible = "mediatek,mt8173-disp-od"; 206 reg = <0 0x14023000 0 0x1000>; 207 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 208 clocks = <&mmsys CLK_MM_DISP_OD>; 209}; 210