15956d97fSEmmanuel Vadot# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause 25956d97fSEmmanuel Vadot%YAML 1.2 35956d97fSEmmanuel Vadot--- 45956d97fSEmmanuel Vadot$id: http://devicetree.org/schemas/display/msm/dpu-sdm845.yaml# 55956d97fSEmmanuel Vadot$schema: http://devicetree.org/meta-schemas/core.yaml# 65956d97fSEmmanuel Vadot 75956d97fSEmmanuel Vadottitle: Qualcomm Display DPU dt properties for SDM845 target 85956d97fSEmmanuel Vadot 95956d97fSEmmanuel Vadotmaintainers: 10d5b0e70fSEmmanuel Vadot - Krishna Manikandan <quic_mkrishn@quicinc.com> 115956d97fSEmmanuel Vadot 125956d97fSEmmanuel Vadotdescription: | 135956d97fSEmmanuel Vadot Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates 145956d97fSEmmanuel Vadot sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree 155956d97fSEmmanuel Vadot bindings of MDSS and DPU are mentioned for SDM845 target. 165956d97fSEmmanuel Vadot 175956d97fSEmmanuel Vadotproperties: 185956d97fSEmmanuel Vadot compatible: 195956d97fSEmmanuel Vadot items: 205956d97fSEmmanuel Vadot - const: qcom,sdm845-mdss 215956d97fSEmmanuel Vadot 225956d97fSEmmanuel Vadot reg: 235956d97fSEmmanuel Vadot maxItems: 1 245956d97fSEmmanuel Vadot 255956d97fSEmmanuel Vadot reg-names: 265956d97fSEmmanuel Vadot const: mdss 275956d97fSEmmanuel Vadot 285956d97fSEmmanuel Vadot power-domains: 295956d97fSEmmanuel Vadot maxItems: 1 305956d97fSEmmanuel Vadot 315956d97fSEmmanuel Vadot clocks: 325956d97fSEmmanuel Vadot items: 335956d97fSEmmanuel Vadot - description: Display AHB clock from gcc 345956d97fSEmmanuel Vadot - description: Display core clock 355956d97fSEmmanuel Vadot 365956d97fSEmmanuel Vadot clock-names: 375956d97fSEmmanuel Vadot items: 385956d97fSEmmanuel Vadot - const: iface 395956d97fSEmmanuel Vadot - const: core 405956d97fSEmmanuel Vadot 415956d97fSEmmanuel Vadot interrupts: 425956d97fSEmmanuel Vadot maxItems: 1 435956d97fSEmmanuel Vadot 445956d97fSEmmanuel Vadot interrupt-controller: true 455956d97fSEmmanuel Vadot 465956d97fSEmmanuel Vadot "#address-cells": true 475956d97fSEmmanuel Vadot 485956d97fSEmmanuel Vadot "#size-cells": true 495956d97fSEmmanuel Vadot 505956d97fSEmmanuel Vadot "#interrupt-cells": 515956d97fSEmmanuel Vadot const: 1 525956d97fSEmmanuel Vadot 535956d97fSEmmanuel Vadot iommus: 545956d97fSEmmanuel Vadot items: 555956d97fSEmmanuel Vadot - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0 565956d97fSEmmanuel Vadot - description: Phandle to apps_smmu node with SID mask for Hard-Fail port1 575956d97fSEmmanuel Vadot 585956d97fSEmmanuel Vadot ranges: true 595956d97fSEmmanuel Vadot 60d5b0e70fSEmmanuel Vadot resets: 61d5b0e70fSEmmanuel Vadot items: 62d5b0e70fSEmmanuel Vadot - description: MDSS_CORE reset 63d5b0e70fSEmmanuel Vadot 645956d97fSEmmanuel VadotpatternProperties: 655956d97fSEmmanuel Vadot "^display-controller@[0-9a-f]+$": 665956d97fSEmmanuel Vadot type: object 675956d97fSEmmanuel Vadot description: Node containing the properties of DPU. 68*7ef62cebSEmmanuel Vadot additionalProperties: false 695956d97fSEmmanuel Vadot 705956d97fSEmmanuel Vadot properties: 715956d97fSEmmanuel Vadot compatible: 725956d97fSEmmanuel Vadot items: 735956d97fSEmmanuel Vadot - const: qcom,sdm845-dpu 745956d97fSEmmanuel Vadot 755956d97fSEmmanuel Vadot reg: 765956d97fSEmmanuel Vadot items: 775956d97fSEmmanuel Vadot - description: Address offset and size for mdp register set 785956d97fSEmmanuel Vadot - description: Address offset and size for vbif register set 795956d97fSEmmanuel Vadot 805956d97fSEmmanuel Vadot reg-names: 815956d97fSEmmanuel Vadot items: 825956d97fSEmmanuel Vadot - const: mdp 835956d97fSEmmanuel Vadot - const: vbif 845956d97fSEmmanuel Vadot 855956d97fSEmmanuel Vadot clocks: 865956d97fSEmmanuel Vadot items: 875956d97fSEmmanuel Vadot - description: Display ahb clock 885956d97fSEmmanuel Vadot - description: Display axi clock 895956d97fSEmmanuel Vadot - description: Display core clock 905956d97fSEmmanuel Vadot - description: Display vsync clock 915956d97fSEmmanuel Vadot 925956d97fSEmmanuel Vadot clock-names: 935956d97fSEmmanuel Vadot items: 945956d97fSEmmanuel Vadot - const: iface 955956d97fSEmmanuel Vadot - const: bus 965956d97fSEmmanuel Vadot - const: core 975956d97fSEmmanuel Vadot - const: vsync 985956d97fSEmmanuel Vadot 995956d97fSEmmanuel Vadot interrupts: 1005956d97fSEmmanuel Vadot maxItems: 1 1015956d97fSEmmanuel Vadot 1025956d97fSEmmanuel Vadot power-domains: 1035956d97fSEmmanuel Vadot maxItems: 1 1045956d97fSEmmanuel Vadot 1055956d97fSEmmanuel Vadot operating-points-v2: true 106*7ef62cebSEmmanuel Vadot opp-table: 107*7ef62cebSEmmanuel Vadot type: object 108*7ef62cebSEmmanuel Vadot 1095956d97fSEmmanuel Vadot ports: 1105956d97fSEmmanuel Vadot $ref: /schemas/graph.yaml#/properties/ports 1115956d97fSEmmanuel Vadot description: | 1125956d97fSEmmanuel Vadot Contains the list of output ports from DPU device. These ports 1135956d97fSEmmanuel Vadot connect to interfaces that are external to the DPU hardware, 1145956d97fSEmmanuel Vadot such as DSI, DP etc. Each output port contains an endpoint that 1155956d97fSEmmanuel Vadot describes how it is connected to an external interface. 1165956d97fSEmmanuel Vadot 1175956d97fSEmmanuel Vadot properties: 1185956d97fSEmmanuel Vadot port@0: 1195956d97fSEmmanuel Vadot $ref: /schemas/graph.yaml#/properties/port 1205956d97fSEmmanuel Vadot description: DPU_INTF1 (DSI1) 1215956d97fSEmmanuel Vadot 1225956d97fSEmmanuel Vadot port@1: 1235956d97fSEmmanuel Vadot $ref: /schemas/graph.yaml#/properties/port 1245956d97fSEmmanuel Vadot description: DPU_INTF2 (DSI2) 1255956d97fSEmmanuel Vadot 1265956d97fSEmmanuel Vadot required: 1275956d97fSEmmanuel Vadot - port@0 1285956d97fSEmmanuel Vadot - port@1 1295956d97fSEmmanuel Vadot 1305956d97fSEmmanuel Vadot required: 1315956d97fSEmmanuel Vadot - compatible 1325956d97fSEmmanuel Vadot - reg 1335956d97fSEmmanuel Vadot - reg-names 1345956d97fSEmmanuel Vadot - clocks 1355956d97fSEmmanuel Vadot - interrupts 1365956d97fSEmmanuel Vadot - power-domains 1375956d97fSEmmanuel Vadot - operating-points-v2 1385956d97fSEmmanuel Vadot - ports 1395956d97fSEmmanuel Vadot 1405956d97fSEmmanuel Vadotrequired: 1415956d97fSEmmanuel Vadot - compatible 1425956d97fSEmmanuel Vadot - reg 1435956d97fSEmmanuel Vadot - reg-names 1445956d97fSEmmanuel Vadot - power-domains 1455956d97fSEmmanuel Vadot - clocks 1465956d97fSEmmanuel Vadot - interrupts 1475956d97fSEmmanuel Vadot - interrupt-controller 1485956d97fSEmmanuel Vadot - iommus 1495956d97fSEmmanuel Vadot - ranges 1505956d97fSEmmanuel Vadot 1515956d97fSEmmanuel VadotadditionalProperties: false 1525956d97fSEmmanuel Vadot 1535956d97fSEmmanuel Vadotexamples: 1545956d97fSEmmanuel Vadot - | 1555956d97fSEmmanuel Vadot #include <dt-bindings/clock/qcom,dispcc-sdm845.h> 1565956d97fSEmmanuel Vadot #include <dt-bindings/clock/qcom,gcc-sdm845.h> 1575956d97fSEmmanuel Vadot #include <dt-bindings/interrupt-controller/arm-gic.h> 1585956d97fSEmmanuel Vadot #include <dt-bindings/power/qcom-rpmpd.h> 1595956d97fSEmmanuel Vadot 1605956d97fSEmmanuel Vadot display-subsystem@ae00000 { 1615956d97fSEmmanuel Vadot #address-cells = <1>; 1625956d97fSEmmanuel Vadot #size-cells = <1>; 1635956d97fSEmmanuel Vadot compatible = "qcom,sdm845-mdss"; 1645956d97fSEmmanuel Vadot reg = <0x0ae00000 0x1000>; 1655956d97fSEmmanuel Vadot reg-names = "mdss"; 1665956d97fSEmmanuel Vadot power-domains = <&dispcc MDSS_GDSC>; 1675956d97fSEmmanuel Vadot 1685956d97fSEmmanuel Vadot clocks = <&gcc GCC_DISP_AHB_CLK>, 1695956d97fSEmmanuel Vadot <&dispcc DISP_CC_MDSS_MDP_CLK>; 170e67e8565SEmmanuel Vadot clock-names = "iface", "core"; 1715956d97fSEmmanuel Vadot 1725956d97fSEmmanuel Vadot interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 1735956d97fSEmmanuel Vadot interrupt-controller; 1745956d97fSEmmanuel Vadot #interrupt-cells = <1>; 1755956d97fSEmmanuel Vadot 1765956d97fSEmmanuel Vadot iommus = <&apps_smmu 0x880 0x8>, 1775956d97fSEmmanuel Vadot <&apps_smmu 0xc80 0x8>; 1785956d97fSEmmanuel Vadot ranges; 1795956d97fSEmmanuel Vadot 1805956d97fSEmmanuel Vadot display-controller@ae01000 { 1815956d97fSEmmanuel Vadot compatible = "qcom,sdm845-dpu"; 1825956d97fSEmmanuel Vadot reg = <0x0ae01000 0x8f000>, 1835956d97fSEmmanuel Vadot <0x0aeb0000 0x2008>; 1845956d97fSEmmanuel Vadot reg-names = "mdp", "vbif"; 1855956d97fSEmmanuel Vadot 1865956d97fSEmmanuel Vadot clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 1875956d97fSEmmanuel Vadot <&dispcc DISP_CC_MDSS_AXI_CLK>, 1885956d97fSEmmanuel Vadot <&dispcc DISP_CC_MDSS_MDP_CLK>, 1895956d97fSEmmanuel Vadot <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 1905956d97fSEmmanuel Vadot clock-names = "iface", "bus", "core", "vsync"; 1915956d97fSEmmanuel Vadot 1925956d97fSEmmanuel Vadot interrupt-parent = <&mdss>; 1935956d97fSEmmanuel Vadot interrupts = <0>; 1945956d97fSEmmanuel Vadot power-domains = <&rpmhpd SDM845_CX>; 1955956d97fSEmmanuel Vadot operating-points-v2 = <&mdp_opp_table>; 1965956d97fSEmmanuel Vadot 1975956d97fSEmmanuel Vadot ports { 1985956d97fSEmmanuel Vadot #address-cells = <1>; 1995956d97fSEmmanuel Vadot #size-cells = <0>; 2005956d97fSEmmanuel Vadot 2015956d97fSEmmanuel Vadot port@0 { 2025956d97fSEmmanuel Vadot reg = <0>; 2035956d97fSEmmanuel Vadot dpu_intf1_out: endpoint { 2045956d97fSEmmanuel Vadot remote-endpoint = <&dsi0_in>; 2055956d97fSEmmanuel Vadot }; 2065956d97fSEmmanuel Vadot }; 2075956d97fSEmmanuel Vadot 2085956d97fSEmmanuel Vadot port@1 { 2095956d97fSEmmanuel Vadot reg = <1>; 2105956d97fSEmmanuel Vadot dpu_intf2_out: endpoint { 2115956d97fSEmmanuel Vadot remote-endpoint = <&dsi1_in>; 2125956d97fSEmmanuel Vadot }; 2135956d97fSEmmanuel Vadot }; 2145956d97fSEmmanuel Vadot }; 2155956d97fSEmmanuel Vadot }; 2165956d97fSEmmanuel Vadot }; 2175956d97fSEmmanuel Vadot... 218