1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4
5$id: http://devicetree.org/schemas/display/msm/gpu.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: Adreno or Snapdragon GPUs
9
10maintainers:
11  - Rob Clark <robdclark@gmail.com>
12
13properties:
14  compatible:
15    oneOf:
16      - description: |
17          The driver is parsing the compat string for Adreno to
18          figure out the gpu-id and patch level.
19        items:
20          - pattern: '^qcom,adreno-[3-6][0-9][0-9]\.[0-9]$'
21          - const: qcom,adreno
22      - description: |
23          The driver is parsing the compat string for Imageon to
24          figure out the gpu-id and patch level.
25        items:
26          - pattern: '^amd,imageon-200\.[0-1]$'
27          - const: amd,imageon
28
29  clocks: true
30
31  clock-names: true
32
33  reg:
34    minItems: 1
35    maxItems: 3
36
37  reg-names:
38    minItems: 1
39    maxItems: 3
40
41  interrupts:
42    maxItems: 1
43
44  interrupt-names:
45    maxItems: 1
46
47  interconnects:
48    minItems: 1
49    maxItems: 2
50
51  interconnect-names:
52    minItems: 1
53    items:
54      - const: gfx-mem
55      - const: ocmem
56
57  iommus:
58    minItems: 1
59    maxItems: 64
60
61  sram:
62    $ref: /schemas/types.yaml#/definitions/phandle-array
63    minItems: 1
64    maxItems: 4
65    items:
66      maxItems: 1
67    description: |
68      phandles to one or more reserved on-chip SRAM regions.
69      phandle to the On Chip Memory (OCMEM) that's present on some a3xx and
70      a4xx Snapdragon SoCs. See
71      Documentation/devicetree/bindings/sram/qcom,ocmem.yaml
72
73  operating-points-v2: true
74  opp-table:
75    type: object
76
77  power-domains:
78    maxItems: 1
79
80  zap-shader:
81    type: object
82    additionalProperties: false
83    description: |
84      For a5xx and a6xx devices this node contains a memory-region that
85      points to reserved memory to store the zap shader that can be used to
86      help bring the GPU out of secure mode.
87    properties:
88      memory-region:
89        maxItems: 1
90
91      firmware-name:
92        description: |
93          Default name of the firmware to load to the remote processor.
94
95  "#cooling-cells":
96    const: 2
97
98  nvmem-cell-names:
99    maxItems: 1
100
101  nvmem-cells:
102    description: efuse registers
103    maxItems: 1
104
105  qcom,gmu:
106    $ref: /schemas/types.yaml#/definitions/phandle
107    description: |
108      For GMU attached devices a phandle to the GMU device that will
109      control the power for the GPU.
110
111
112required:
113  - compatible
114  - reg
115  - interrupts
116
117additionalProperties: false
118
119allOf:
120  - if:
121      properties:
122        compatible:
123          contains:
124            pattern: '^qcom,adreno-[3-5][0-9][0-9]\.[0-9]$'
125
126    then:
127      properties:
128        clocks:
129          minItems: 2
130          maxItems: 7
131
132        clock-names:
133          items:
134            anyOf:
135              - const: core
136                description: GPU Core clock
137              - const: iface
138                description: GPU Interface clock
139              - const: mem
140                description: GPU Memory clock
141              - const: mem_iface
142                description: GPU Memory Interface clock
143              - const: alt_mem_iface
144                description: GPU Alternative Memory Interface clock
145              - const: gfx3d
146                description: GPU 3D engine clock
147              - const: rbbmtimer
148                description: GPU RBBM Timer for Adreno 5xx series
149              - const: rbcpr
150                description: GPU RB Core Power Reduction clock
151          minItems: 2
152          maxItems: 7
153
154      required:
155        - clocks
156        - clock-names
157
158  - if:
159      properties:
160        compatible:
161          contains:
162            enum:
163              - qcom,adreno-610.0
164              - qcom,adreno-619.1
165    then:
166      properties:
167        clocks:
168          minItems: 6
169          maxItems: 6
170
171        clock-names:
172          items:
173            - const: core
174              description: GPU Core clock
175            - const: iface
176              description: GPU Interface clock
177            - const: mem_iface
178              description: GPU Memory Interface clock
179            - const: alt_mem_iface
180              description: GPU Alternative Memory Interface clock
181            - const: gmu
182              description: CX GMU clock
183            - const: xo
184              description: GPUCC clocksource clock
185
186        reg-names:
187          minItems: 1
188          items:
189            - const: kgsl_3d0_reg_memory
190            - const: cx_dbgc
191
192      required:
193        - clocks
194        - clock-names
195    else:
196      if:
197        properties:
198          compatible:
199            contains:
200              pattern: '^qcom,adreno-6[0-9][0-9]\.[0-9]$'
201
202      then: # Starting with A6xx, the clocks are usually defined in the GMU node
203        properties:
204          clocks: false
205          clock-names: false
206
207          reg-names:
208            minItems: 1
209            items:
210              - const: kgsl_3d0_reg_memory
211              - const: cx_mem
212              - const: cx_dbgc
213
214examples:
215  - |
216
217    // Example a3xx/4xx:
218
219    #include <dt-bindings/clock/qcom,mmcc-msm8974.h>
220    #include <dt-bindings/clock/qcom,rpmcc.h>
221    #include <dt-bindings/interrupt-controller/irq.h>
222    #include <dt-bindings/interrupt-controller/arm-gic.h>
223
224    gpu: gpu@fdb00000 {
225        compatible = "qcom,adreno-330.2", "qcom,adreno";
226
227        reg = <0xfdb00000 0x10000>;
228        reg-names = "kgsl_3d0_reg_memory";
229
230        clock-names = "core", "iface", "mem_iface";
231        clocks = <&mmcc OXILI_GFX3D_CLK>,
232                 <&mmcc OXILICX_AHB_CLK>,
233                 <&mmcc OXILICX_AXI_CLK>;
234
235        interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
236        interrupt-names = "kgsl_3d0_irq";
237
238        sram = <&gpu_sram>;
239        power-domains = <&mmcc OXILICX_GDSC>;
240        operating-points-v2 = <&gpu_opp_table>;
241        iommus = <&gpu_iommu 0>;
242        #cooling-cells = <2>;
243    };
244
245    ocmem@fdd00000 {
246        compatible = "qcom,msm8974-ocmem";
247
248        reg = <0xfdd00000 0x2000>,
249              <0xfec00000 0x180000>;
250        reg-names = "ctrl", "mem";
251
252        clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>,
253                 <&mmcc OCMEMCX_OCMEMNOC_CLK>;
254        clock-names = "core", "iface";
255
256        #address-cells = <1>;
257        #size-cells = <1>;
258        ranges = <0 0xfec00000 0x100000>;
259
260        gpu_sram: gpu-sram@0 {
261            reg = <0x0 0x100000>;
262        };
263    };
264  - |
265
266    // Example a6xx (with GMU):
267
268    #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
269    #include <dt-bindings/clock/qcom,gcc-sdm845.h>
270    #include <dt-bindings/power/qcom-rpmpd.h>
271    #include <dt-bindings/interrupt-controller/irq.h>
272    #include <dt-bindings/interrupt-controller/arm-gic.h>
273    #include <dt-bindings/interconnect/qcom,sdm845.h>
274
275    reserved-memory {
276        #address-cells = <2>;
277        #size-cells = <2>;
278
279        zap_shader_region: gpu@8f200000 {
280            compatible = "shared-dma-pool";
281            reg = <0x0 0x90b00000 0x0 0xa00000>;
282            no-map;
283        };
284    };
285
286    gpu@5000000 {
287        compatible = "qcom,adreno-630.2", "qcom,adreno";
288
289        reg = <0x5000000 0x40000>, <0x509e000 0x10>;
290        reg-names = "kgsl_3d0_reg_memory", "cx_mem";
291
292        #cooling-cells = <2>;
293
294        interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
295
296        iommus = <&adreno_smmu 0>;
297
298        operating-points-v2 = <&gpu_opp_table>;
299
300        interconnects = <&rsc_hlos MASTER_GFX3D &rsc_hlos SLAVE_EBI1>;
301        interconnect-names = "gfx-mem";
302
303        qcom,gmu = <&gmu>;
304
305        gpu_opp_table: opp-table {
306            compatible = "operating-points-v2";
307
308            opp-430000000 {
309                opp-hz = /bits/ 64 <430000000>;
310                opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
311                opp-peak-kBps = <5412000>;
312            };
313
314            opp-355000000 {
315                opp-hz = /bits/ 64 <355000000>;
316                opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
317                opp-peak-kBps = <3072000>;
318            };
319
320            opp-267000000 {
321                opp-hz = /bits/ 64 <267000000>;
322                opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
323                opp-peak-kBps = <3072000>;
324            };
325
326            opp-180000000 {
327                opp-hz = /bits/ 64 <180000000>;
328                opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
329                opp-peak-kBps = <1804000>;
330            };
331        };
332
333        zap-shader {
334            memory-region = <&zap_shader_region>;
335            firmware-name = "qcom/LENOVO/81JL/qcdxkmsuc850.mbn";
336        };
337    };
338