1Rockchip specific extensions to the Synopsys Designware MIPI DSI
2================================
3
4Required properties:
5- #address-cells: Should be <1>.
6- #size-cells: Should be <0>.
7- compatible: one of
8	"rockchip,px30-mipi-dsi", "snps,dw-mipi-dsi"
9	"rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi"
10	"rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"
11	"rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi"
12- reg: Represent the physical address range of the controller.
13- interrupts: Represent the controller's interrupt to the CPU(s).
14- clocks, clock-names: Phandles to the controller's pll reference
15  clock(ref) when using an internal dphy and APB clock(pclk).
16  For RK3399, a phy config clock (phy_cfg) and a grf clock(grf)
17  are required. As described in [1].
18- rockchip,grf: this soc should set GRF regs to mux vopl/vopb.
19- ports: contain a port node with endpoint definitions as defined in [2].
20  For vopb,set the reg = <0> and set the reg = <1> for vopl.
21- video port 0 for the VOP input, the remote endpoint maybe vopb or vopl
22- video port 1 for either a panel or subsequent encoder
23
24Optional properties:
25- phys: from general PHY binding: the phandle for the PHY device.
26- phy-names: Should be "dphy" if phys references an external phy.
27- #phy-cells: Defined when used as ISP phy, should be 0.
28- power-domains: a phandle to mipi dsi power domain node.
29- resets: list of phandle + reset specifier pairs, as described in [3].
30- reset-names: string reset name, must be "apb".
31
32[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
33[2] Documentation/devicetree/bindings/media/video-interfaces.txt
34[3] Documentation/devicetree/bindings/reset/reset.txt
35
36Example:
37	mipi_dsi: mipi@ff960000 {
38		#address-cells = <1>;
39		#size-cells = <0>;
40		compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
41		reg = <0xff960000 0x4000>;
42		interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
43		clocks = <&cru SCLK_MIPI_24M>, <&cru PCLK_MIPI_DSI0>;
44		clock-names = "ref", "pclk";
45		resets = <&cru SRST_MIPIDSI0>;
46		reset-names = "apb";
47		rockchip,grf = <&grf>;
48
49		ports {
50			#address-cells = <1>;
51			#size-cells = <0>;
52
53			mipi_in: port@0 {
54				reg = <0>;
55				#address-cells = <1>;
56				#size-cells = <0>;
57
58				mipi_in_vopb: endpoint@0 {
59					reg = <0>;
60					remote-endpoint = <&vopb_out_mipi>;
61				};
62				mipi_in_vopl: endpoint@1 {
63					reg = <1>;
64					remote-endpoint = <&vopl_out_mipi>;
65				};
66			};
67
68			mipi_out: port@1 {
69				reg = <1>;
70				#address-cells = <1>;
71				#size-cells = <0>;
72
73				mipi_out_panel: endpoint {
74					remote-endpoint = <&panel_in_mipi>;
75				};
76			};
77		};
78
79		panel {
80			compatible ="boe,tv080wum-nl0";
81			reg = <0>;
82
83			enable-gpios = <&gpio7 3 GPIO_ACTIVE_HIGH>;
84			pinctrl-names = "default";
85			pinctrl-0 = <&lcd_en>;
86			backlight = <&backlight>;
87
88			port {
89				panel_in_mipi: endpoint {
90					remote-endpoint = <&mipi_out_panel>;
91				};
92			};
93		};
94	};
95