1Rockchip specific extensions to the Synopsys Designware MIPI DSI
2================================
3
4Required properties:
5- #address-cells: Should be <1>.
6- #size-cells: Should be <0>.
7- compatible: one of
8	"rockchip,px30-mipi-dsi", "snps,dw-mipi-dsi"
9	"rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi"
10	"rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"
11- reg: Represent the physical address range of the controller.
12- interrupts: Represent the controller's interrupt to the CPU(s).
13- clocks, clock-names: Phandles to the controller's pll reference
14  clock(ref) when using an internal dphy and APB clock(pclk).
15  For RK3399, a phy config clock (phy_cfg) and a grf clock(grf)
16  are required. As described in [1].
17- rockchip,grf: this soc should set GRF regs to mux vopl/vopb.
18- ports: contain a port node with endpoint definitions as defined in [2].
19  For vopb,set the reg = <0> and set the reg = <1> for vopl.
20- video port 0 for the VOP input, the remote endpoint maybe vopb or vopl
21- video port 1 for either a panel or subsequent encoder
22
23Optional properties:
24- phys: from general PHY binding: the phandle for the PHY device.
25- phy-names: Should be "dphy" if phys references an external phy.
26- #phy-cells: Defined when used as ISP phy, should be 0.
27- power-domains: a phandle to mipi dsi power domain node.
28- resets: list of phandle + reset specifier pairs, as described in [3].
29- reset-names: string reset name, must be "apb".
30
31[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
32[2] Documentation/devicetree/bindings/media/video-interfaces.txt
33[3] Documentation/devicetree/bindings/reset/reset.txt
34
35Example:
36	mipi_dsi: mipi@ff960000 {
37		#address-cells = <1>;
38		#size-cells = <0>;
39		compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
40		reg = <0xff960000 0x4000>;
41		interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
42		clocks = <&cru SCLK_MIPI_24M>, <&cru PCLK_MIPI_DSI0>;
43		clock-names = "ref", "pclk";
44		resets = <&cru SRST_MIPIDSI0>;
45		reset-names = "apb";
46		rockchip,grf = <&grf>;
47
48		ports {
49			#address-cells = <1>;
50			#size-cells = <0>;
51
52			mipi_in: port@0 {
53				reg = <0>;
54				#address-cells = <1>;
55				#size-cells = <0>;
56
57				mipi_in_vopb: endpoint@0 {
58					reg = <0>;
59					remote-endpoint = <&vopb_out_mipi>;
60				};
61				mipi_in_vopl: endpoint@1 {
62					reg = <1>;
63					remote-endpoint = <&vopl_out_mipi>;
64				};
65			};
66
67			mipi_out: port@1 {
68				reg = <1>;
69				#address-cells = <1>;
70				#size-cells = <0>;
71
72				mipi_out_panel: endpoint {
73					remote-endpoint = <&panel_in_mipi>;
74				};
75			};
76		};
77
78		panel {
79			compatible ="boe,tv080wum-nl0";
80			reg = <0>;
81
82			enable-gpios = <&gpio7 3 GPIO_ACTIVE_HIGH>;
83			pinctrl-names = "default";
84			pinctrl-0 = <&lcd_en>;
85			backlight = <&backlight>;
86
87			port {
88				panel_in_mipi: endpoint {
89					remote-endpoint = <&mipi_out_panel>;
90				};
91			};
92		};
93	};
94