1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/xlnx/xlnx,zynqmp-dpsub.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Xilinx ZynqMP DisplayPort Subsystem
8
9description: |
10  The DisplayPort subsystem of Xilinx ZynqMP (Zynq UltraScale+ MPSoC)
11  implements the display and audio pipelines based on the DisplayPort v1.2
12  standard. The subsystem includes multiple functional blocks as below:
13
14               +------------------------------------------------------------+
15  +--------+   | +----------------+     +-----------+                       |
16  | DPDMA  | --->|                | --> |   Video   | Video +-------------+ |
17  | 4x vid |   | |                |     | Rendering | -+--> |             | |   +------+
18  | 2x aud |   | |  Audio/Video   | --> | Pipeline  |  |    | DisplayPort |---> | PHY0 |
19  +--------+   | | Buffer Manager |     +-----------+  |    |   Source    | |   +------+
20               | |    and STC     |     +-----------+  |    | Controller  | |   +------+
21  Live Video --->|                | --> |   Audio   | Audio |             |---> | PHY1 |
22               | |                |     |   Mixer   | --+-> |             | |   +------+
23  Live Audio --->|                | --> |           |  ||   +-------------+ |
24               | +----------------+     +-----------+  ||                   |
25               +---------------------------------------||-------------------+
26                                                       vv
27                                                 Blended Video and
28                                                 Mixed Audio to PL
29
30  The Buffer Manager interacts with external interface such as DMA engines or
31  live audio/video streams from the programmable logic. The Video Rendering
32  Pipeline blends the video and graphics layers and performs colorspace
33  conversion. The Audio Mixer mixes the incoming audio streams. The DisplayPort
34  Source Controller handles the DisplayPort protocol and connects to external
35  PHYs.
36
37  The subsystem supports 2 video and 2 audio streams, and various pixel formats
38  and depths up to 4K@30 resolution.
39
40  Please refer to "Zynq UltraScale+ Device Technical Reference Manual"
41  (https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf)
42  for more details.
43
44maintainers:
45  - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
46
47properties:
48  compatible:
49    const: xlnx,zynqmp-dpsub-1.7
50
51  reg:
52    maxItems: 4
53  reg-names:
54    items:
55      - const: dp
56      - const: blend
57      - const: av_buf
58      - const: aud
59
60  interrupts:
61    maxItems: 1
62
63  clocks:
64    description:
65      The APB clock and at least one video clock are mandatory, the audio clock
66      is optional.
67    minItems: 2
68    items:
69      - description: dp_apb_clk is the APB clock
70      - description: dp_aud_clk is the Audio clock
71      - description:
72          dp_vtc_pixel_clk_in is the non-live video clock (from Processing
73          System)
74      - description:
75          dp_live_video_in_clk is the live video clock (from Programmable
76          Logic)
77  clock-names:
78    oneOf:
79      - minItems: 2
80        items:
81          - const: dp_apb_clk
82          - enum: [ dp_vtc_pixel_clk_in, dp_live_video_in_clk ]
83          - enum: [ dp_vtc_pixel_clk_in, dp_live_video_in_clk ]
84      - minItems: 3
85        items:
86          - const: dp_apb_clk
87          - const: dp_aud_clk
88          - enum: [ dp_vtc_pixel_clk_in, dp_live_video_in_clk ]
89          - enum: [ dp_vtc_pixel_clk_in, dp_live_video_in_clk ]
90
91  power-domains:
92    maxItems: 1
93
94  resets:
95    maxItems: 1
96
97  dmas:
98    items:
99      - description: Video layer, plane 0 (RGB or luma)
100      - description: Video layer, plane 1 (U/V or U)
101      - description: Video layer, plane 2 (V)
102      - description: Graphics layer
103  dma-names:
104    items:
105      - const: vid0
106      - const: vid1
107      - const: vid2
108      - const: gfx0
109
110  phys:
111    description: PHYs for the DP data lanes
112    minItems: 1
113    maxItems: 2
114  phy-names:
115    minItems: 1
116    items:
117      - const: dp-phy0
118      - const: dp-phy1
119
120  ports:
121    $ref: /schemas/graph.yaml#/properties/ports
122    description: |
123      Connections to the programmable logic and the DisplayPort PHYs. Each port
124      shall have a single endpoint.
125
126    properties:
127      port@0:
128        $ref: /schemas/graph.yaml#/properties/port
129        description: The live video input from the programmable logic
130
131      port@1:
132        $ref: /schemas/graph.yaml#/properties/port
133        description: The live graphics input from the programmable logic
134
135      port@2:
136        $ref: /schemas/graph.yaml#/properties/port
137        description: The live audio input from the programmable logic
138
139      port@3:
140        $ref: /schemas/graph.yaml#/properties/port
141        description: The blended video output to the programmable logic
142
143      port@4:
144        $ref: /schemas/graph.yaml#/properties/port
145        description: The mixed audio output to the programmable logic
146
147      port@5:
148        $ref: /schemas/graph.yaml#/properties/port
149        description: The DisplayPort output
150
151    required:
152      - port@0
153      - port@1
154      - port@2
155      - port@3
156      - port@4
157      - port@5
158
159required:
160  - compatible
161  - reg
162  - reg-names
163  - interrupts
164  - clocks
165  - clock-names
166  - power-domains
167  - resets
168  - dmas
169  - dma-names
170  - phys
171  - phy-names
172  - ports
173
174additionalProperties: false
175
176examples:
177  - |
178    #include <dt-bindings/phy/phy.h>
179    #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
180
181    display@fd4a0000 {
182        compatible = "xlnx,zynqmp-dpsub-1.7";
183        reg = <0xfd4a0000 0x1000>,
184              <0xfd4aa000 0x1000>,
185              <0xfd4ab000 0x1000>,
186              <0xfd4ac000 0x1000>;
187        reg-names = "dp", "blend", "av_buf", "aud";
188        interrupts = <0 119 4>;
189        interrupt-parent = <&gic>;
190
191        clock-names = "dp_apb_clk", "dp_aud_clk", "dp_live_video_in_clk";
192        clocks = <&dp_aclk>, <&clkc 17>, <&si570_1>;
193
194        power-domains = <&pd_dp>;
195        resets = <&reset ZYNQMP_RESET_DP>;
196
197        dma-names = "vid0", "vid1", "vid2", "gfx0";
198        dmas = <&xlnx_dpdma 0>,
199               <&xlnx_dpdma 1>,
200               <&xlnx_dpdma 2>,
201               <&xlnx_dpdma 3>;
202
203        phys = <&psgtr 1 PHY_TYPE_DP 0 3>,
204               <&psgtr 0 PHY_TYPE_DP 1 3>;
205
206        phy-names = "dp-phy0", "dp-phy1";
207
208        ports {
209            #address-cells = <1>;
210            #size-cells = <0>;
211
212            port@0 {
213                reg = <0>;
214            };
215            port@1 {
216                reg = <1>;
217            };
218            port@2 {
219                reg = <2>;
220            };
221            port@3 {
222                reg = <3>;
223            };
224            port@4 {
225                reg = <4>;
226            };
227            port@5 {
228                reg = <5>;
229                dpsub_dp_out: endpoint {
230                    remote-endpoint = <&dp_connector>;
231                };
232            };
233        };
234    };
235
236...
237