1ZTE VOU Display Controller
2
3This is a display controller found on ZTE ZX296718 SoC.  It includes multiple
4Graphic Layer (GL) and Video Layer (VL), two Mixers/Channels, and a few blocks
5handling scaling, color space conversion etc.  VOU also integrates the support
6for typical output devices, like HDMI, TV Encoder, VGA, and RGB LCD.
7
8* Master VOU node
9
10It must be the parent node of all the sub-device nodes.
11
12Required properties:
13 - compatible: should be "zte,zx296718-vou"
14 - #address-cells: should be <1>
15 - #size-cells: should be <1>
16 - ranges: list of address translations between VOU and sub-devices
17
18* VOU DPC device
19
20Required properties:
21 - compatible: should be "zte,zx296718-dpc"
22 - reg: Physical base address and length of DPC register regions, one for each
23   entry in 'reg-names'
24 - reg-names: The names of register regions. The following regions are required:
25	"osd"
26	"timing_ctrl"
27	"dtrc"
28	"vou_ctrl"
29	"otfppu"
30 - interrupts: VOU DPC interrupt number to CPU
31 - clocks: A list of phandle + clock-specifier pairs, one for each entry
32   in 'clock-names'
33 - clock-names: A list of clock names.  The following clocks are required:
34	"aclk"
35	"ppu_wclk"
36	"main_wclk"
37	"aux_wclk"
38
39* HDMI output device
40
41Required properties:
42 - compatible: should be "zte,zx296718-hdmi"
43 - reg: Physical base address and length of the HDMI device IO region
44 - interrupts : HDMI interrupt number to CPU
45 - clocks: A list of phandle + clock-specifier pairs, one for each entry
46   in 'clock-names'
47 - clock-names: A list of clock names.  The following clocks are required:
48	"osc_cec"
49	"osc_clk"
50	"xclk"
51
52* TV Encoder output device
53
54Required properties:
55 - compatible: should be "zte,zx296718-tvenc"
56 - reg: Physical base address and length of the TVENC device IO region
57 - zte,tvenc-power-control: the phandle to SYSCTRL block followed by two
58   integer cells.  The first cell is the offset of SYSCTRL register used
59   to control TV Encoder DAC power, and the second cell is the bit mask.
60
61* VGA output device
62
63Required properties:
64 - compatible: should be "zte,zx296718-vga"
65 - reg: Physical base address and length of the VGA device IO region
66 - interrupts : VGA interrupt number to CPU
67 - clocks: Phandle with clock-specifier pointing to VGA I2C clock.
68 - clock-names: Must be "i2c_wclk".
69 - zte,vga-power-control: the phandle to SYSCTRL block followed by two
70   integer cells.  The first cell is the offset of SYSCTRL register used
71   to control VGA DAC power, and the second cell is the bit mask.
72
73Example:
74
75vou: vou@1440000 {
76	compatible = "zte,zx296718-vou";
77	#address-cells = <1>;
78	#size-cells = <1>;
79	ranges = <0 0x1440000 0x10000>;
80
81	dpc: dpc@0 {
82		compatible = "zte,zx296718-dpc";
83		reg = <0x0000 0x1000>, <0x1000 0x1000>,
84		      <0x5000 0x1000>, <0x6000 0x1000>,
85		      <0xa000 0x1000>;
86		reg-names = "osd", "timing_ctrl",
87			    "dtrc", "vou_ctrl",
88			    "otfppu";
89		interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
90		clocks = <&topcrm VOU_ACLK>, <&topcrm VOU_PPU_WCLK>,
91			 <&topcrm VOU_MAIN_WCLK>, <&topcrm VOU_AUX_WCLK>;
92		clock-names = "aclk", "ppu_wclk",
93			      "main_wclk", "aux_wclk";
94	};
95
96	vga: vga@8000 {
97		compatible = "zte,zx296718-vga";
98		reg = <0x8000 0x1000>;
99		interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
100		clocks = <&topcrm VGA_I2C_WCLK>;
101		clock-names = "i2c_wclk";
102		zte,vga-power-control = <&sysctrl 0x170 0xe0>;
103	};
104
105	hdmi: hdmi@c000 {
106		compatible = "zte,zx296718-hdmi";
107		reg = <0xc000 0x4000>;
108		interrupts = <GIC_SPI 82 IRQ_TYPE_EDGE_RISING>;
109		clocks = <&topcrm HDMI_OSC_CEC>,
110			 <&topcrm HDMI_OSC_CLK>,
111			 <&topcrm HDMI_XCLK>;
112		clock-names = "osc_cec", "osc_clk", "xclk";
113	};
114
115	tvenc: tvenc@2000 {
116		compatible = "zte,zx296718-tvenc";
117		reg = <0x2000 0x1000>;
118		zte,tvenc-power-control = <&sysctrl 0x170 0x10>;
119	};
120};
121