1* Freescale Smart Direct Memory Access (SDMA) Controller for i.MX
2
3Required properties:
4- compatible : Should be one of
5      "fsl,imx25-sdma"
6      "fsl,imx31-sdma", "fsl,imx31-to1-sdma", "fsl,imx31-to2-sdma"
7      "fsl,imx35-sdma", "fsl,imx35-to1-sdma", "fsl,imx35-to2-sdma"
8      "fsl,imx51-sdma"
9      "fsl,imx53-sdma"
10      "fsl,imx6q-sdma"
11      "fsl,imx7d-sdma"
12      "fsl,imx6ul-sdma"
13      "fsl,imx8mq-sdma"
14      "fsl,imx8mm-sdma"
15      "fsl,imx8mn-sdma"
16      "fsl,imx8mp-sdma"
17  The -to variants should be preferred since they allow to determine the
18  correct ROM script addresses needed for the driver to work without additional
19  firmware.
20- reg : Should contain SDMA registers location and length
21- interrupts : Should contain SDMA interrupt
22- #dma-cells : Must be <3>.
23  The first cell specifies the DMA request/event ID.  See details below
24  about the second and third cell.
25- fsl,sdma-ram-script-name : Should contain the full path of SDMA RAM
26  scripts firmware
27
28The second cell of dma phandle specifies the peripheral type of DMA transfer.
29The full ID of peripheral types can be found below.
30
31	ID	transfer type
32	---------------------
33	0	MCU domain SSI
34	1	Shared SSI
35	2	MMC
36	3	SDHC
37	4	MCU domain UART
38	5	Shared UART
39	6	FIRI
40	7	MCU domain CSPI
41	8	Shared CSPI
42	9	SIM
43	10	ATA
44	11	CCM
45	12	External peripheral
46	13	Memory Stick Host Controller
47	14	Shared Memory Stick Host Controller
48	15	DSP
49	16	Memory
50	17	FIFO type Memory
51	18	SPDIF
52	19	IPU Memory
53	20	ASRC
54	21	ESAI
55	22	SSI Dual FIFO	(needs firmware ver >= 2)
56	23	Shared ASRC
57	24	SAI
58
59The third cell specifies the transfer priority as below.
60
61	ID	transfer priority
62	-------------------------
63	0	High
64	1	Medium
65	2	Low
66
67Optional properties:
68
69- gpr : The phandle to the General Purpose Register (GPR) node.
70- fsl,sdma-event-remap : Register bits of sdma event remap, the format is
71  <reg shift val>.
72    reg is the GPR register offset.
73    shift is the bit position inside the GPR register.
74    val is the value of the bit (0 or 1).
75
76Examples:
77
78sdma@83fb0000 {
79	compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
80	reg = <0x83fb0000 0x4000>;
81	interrupts = <6>;
82	#dma-cells = <3>;
83	fsl,sdma-ram-script-name = "sdma-imx51.bin";
84};
85
86DMA clients connected to the i.MX SDMA controller must use the format
87described in the dma.txt file.
88
89Examples:
90
91ssi2: ssi@70014000 {
92	compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
93	reg = <0x70014000 0x4000>;
94	interrupts = <30>;
95	clocks = <&clks 49>;
96	dmas = <&sdma 24 1 0>,
97	       <&sdma 25 1 0>;
98	dma-names = "rx", "tx";
99	fsl,fifo-depth = <15>;
100};
101
102Using the fsl,sdma-event-remap property:
103
104If we want to use SDMA on the SAI1 port on a MX6SX:
105
106&sdma {
107	gpr = <&gpr>;
108	/* SDMA events remap for SAI1_RX and SAI1_TX */
109	fsl,sdma-event-remap = <0 15 1>, <0 16 1>;
110};
111
112The fsl,sdma-event-remap property in this case has two values:
113- <0 15 1> means that the offset is 0, so GPR0 is the register of the
114SDMA remap. Bit 15 of GPR0 selects between UART4_RX and SAI1_RX.
115Setting bit 15 to 1 selects SAI1_RX.
116- <0 16 1> means that the offset is 0, so GPR0 is the register of the
117SDMA remap. Bit 16 of GPR0 selects between UART4_TX and SAI1_TX.
118Setting bit 16 to 1 selects SAI1_TX.
119