1*c66ec88fSEmmanuel VadotQualcomm Technologies HIDMA Management interface 2*c66ec88fSEmmanuel Vadot 3*c66ec88fSEmmanuel VadotQualcomm Technologies HIDMA is a high speed DMA device. It only supports 4*c66ec88fSEmmanuel Vadotmemcpy and memset capabilities. It has been designed for virtualized 5*c66ec88fSEmmanuel Vadotenvironments. 6*c66ec88fSEmmanuel Vadot 7*c66ec88fSEmmanuel VadotEach HIDMA HW instance consists of multiple DMA channels. These channels 8*c66ec88fSEmmanuel Vadotshare the same bandwidth. The bandwidth utilization can be partitioned 9*c66ec88fSEmmanuel Vadotamong channels based on the priority and weight assignments. 10*c66ec88fSEmmanuel Vadot 11*c66ec88fSEmmanuel VadotThere are only two priority levels and 15 weigh assignments possible. 12*c66ec88fSEmmanuel Vadot 13*c66ec88fSEmmanuel VadotOther parameters here determine how much of the system bus this HIDMA 14*c66ec88fSEmmanuel Vadotinstance can use like maximum read/write request and number of bytes to 15*c66ec88fSEmmanuel Vadotread/write in a single burst. 16*c66ec88fSEmmanuel Vadot 17*c66ec88fSEmmanuel VadotMain node required properties: 18*c66ec88fSEmmanuel Vadot- compatible: "qcom,hidma-mgmt-1.0"; 19*c66ec88fSEmmanuel Vadot- reg: Address range for DMA device 20*c66ec88fSEmmanuel Vadot- dma-channels: Number of channels supported by this DMA controller. 21*c66ec88fSEmmanuel Vadot- max-write-burst-bytes: Maximum write burst in bytes that HIDMA can 22*c66ec88fSEmmanuel Vadot occupy the bus for in a single transaction. A memcpy requested is 23*c66ec88fSEmmanuel Vadot fragmented to multiples of this amount. This parameter is used while 24*c66ec88fSEmmanuel Vadot writing into destination memory. Setting this value incorrectly can 25*c66ec88fSEmmanuel Vadot starve other peripherals in the system. 26*c66ec88fSEmmanuel Vadot- max-read-burst-bytes: Maximum read burst in bytes that HIDMA can 27*c66ec88fSEmmanuel Vadot occupy the bus for in a single transaction. A memcpy request is 28*c66ec88fSEmmanuel Vadot fragmented to multiples of this amount. This parameter is used while 29*c66ec88fSEmmanuel Vadot reading the source memory. Setting this value incorrectly can starve 30*c66ec88fSEmmanuel Vadot other peripherals in the system. 31*c66ec88fSEmmanuel Vadot- max-write-transactions: This value is how many times a write burst is 32*c66ec88fSEmmanuel Vadot applied back to back while writing to the destination before yielding 33*c66ec88fSEmmanuel Vadot the bus. 34*c66ec88fSEmmanuel Vadot- max-read-transactions: This value is how many times a read burst is 35*c66ec88fSEmmanuel Vadot applied back to back while reading the source before yielding the bus. 36*c66ec88fSEmmanuel Vadot- channel-reset-timeout-cycles: Channel reset timeout in cycles for this SOC. 37*c66ec88fSEmmanuel Vadot Once a reset is applied to the HW, HW starts a timer for reset operation 38*c66ec88fSEmmanuel Vadot to confirm. If reset is not completed within this time, HW reports reset 39*c66ec88fSEmmanuel Vadot failure. 40*c66ec88fSEmmanuel Vadot 41*c66ec88fSEmmanuel VadotSub-nodes: 42*c66ec88fSEmmanuel Vadot 43*c66ec88fSEmmanuel VadotHIDMA has one or more DMA channels that are used to move data from one 44*c66ec88fSEmmanuel Vadotmemory location to another. 45*c66ec88fSEmmanuel Vadot 46*c66ec88fSEmmanuel VadotWhen the OS is not in control of the management interface (i.e. it's a guest), 47*c66ec88fSEmmanuel Vadotthe channel nodes appear on their own, not under a management node. 48*c66ec88fSEmmanuel Vadot 49*c66ec88fSEmmanuel VadotRequired properties: 50*c66ec88fSEmmanuel Vadot- compatible: must contain "qcom,hidma-1.0" for initial HW or 51*c66ec88fSEmmanuel Vadot "qcom,hidma-1.1"/"qcom,hidma-1.2" for MSI capable HW. 52*c66ec88fSEmmanuel Vadot- reg: Addresses for the transfer and event channel 53*c66ec88fSEmmanuel Vadot- interrupts: Should contain the event interrupt 54*c66ec88fSEmmanuel Vadot- desc-count: Number of asynchronous requests this channel can handle 55*c66ec88fSEmmanuel Vadot- iommus: required a iommu node 56*c66ec88fSEmmanuel Vadot 57*c66ec88fSEmmanuel VadotOptional properties for MSI: 58*c66ec88fSEmmanuel Vadot- msi-parent : See the generic MSI binding described in 59*c66ec88fSEmmanuel Vadot devicetree/bindings/interrupt-controller/msi.txt for a description of the 60*c66ec88fSEmmanuel Vadot msi-parent property. 61*c66ec88fSEmmanuel Vadot 62*c66ec88fSEmmanuel VadotExample: 63*c66ec88fSEmmanuel Vadot 64*c66ec88fSEmmanuel VadotHypervisor OS configuration: 65*c66ec88fSEmmanuel Vadot 66*c66ec88fSEmmanuel Vadot hidma-mgmt@f9984000 = { 67*c66ec88fSEmmanuel Vadot compatible = "qcom,hidma-mgmt-1.0"; 68*c66ec88fSEmmanuel Vadot reg = <0xf9984000 0x15000>; 69*c66ec88fSEmmanuel Vadot dma-channels = <6>; 70*c66ec88fSEmmanuel Vadot max-write-burst-bytes = <1024>; 71*c66ec88fSEmmanuel Vadot max-read-burst-bytes = <1024>; 72*c66ec88fSEmmanuel Vadot max-write-transactions = <31>; 73*c66ec88fSEmmanuel Vadot max-read-transactions = <31>; 74*c66ec88fSEmmanuel Vadot channel-reset-timeout-cycles = <0x500>; 75*c66ec88fSEmmanuel Vadot 76*c66ec88fSEmmanuel Vadot hidma_24: dma-controller@5c050000 { 77*c66ec88fSEmmanuel Vadot compatible = "qcom,hidma-1.0"; 78*c66ec88fSEmmanuel Vadot reg = <0 0x5c050000 0x0 0x1000>, 79*c66ec88fSEmmanuel Vadot <0 0x5c0b0000 0x0 0x1000>; 80*c66ec88fSEmmanuel Vadot interrupts = <0 389 0>; 81*c66ec88fSEmmanuel Vadot desc-count = <10>; 82*c66ec88fSEmmanuel Vadot iommus = <&system_mmu>; 83*c66ec88fSEmmanuel Vadot }; 84*c66ec88fSEmmanuel Vadot }; 85*c66ec88fSEmmanuel Vadot 86*c66ec88fSEmmanuel VadotGuest OS configuration: 87*c66ec88fSEmmanuel Vadot 88*c66ec88fSEmmanuel Vadot hidma_24: dma-controller@5c050000 { 89*c66ec88fSEmmanuel Vadot compatible = "qcom,hidma-1.0"; 90*c66ec88fSEmmanuel Vadot reg = <0 0x5c050000 0x0 0x1000>, 91*c66ec88fSEmmanuel Vadot <0 0x5c0b0000 0x0 0x1000>; 92*c66ec88fSEmmanuel Vadot interrupts = <0 389 0>; 93*c66ec88fSEmmanuel Vadot desc-count = <10>; 94*c66ec88fSEmmanuel Vadot iommus = <&system_mmu>; 95*c66ec88fSEmmanuel Vadot }; 96