1*c66ec88fSEmmanuel Vadot* Synopsys Designware DMA Controller 2*c66ec88fSEmmanuel Vadot 3*c66ec88fSEmmanuel VadotRequired properties: 4*c66ec88fSEmmanuel Vadot- compatible: "snps,dma-spear1340" 5*c66ec88fSEmmanuel Vadot- reg: Address range of the DMAC registers 6*c66ec88fSEmmanuel Vadot- interrupt: Should contain the DMAC interrupt number 7*c66ec88fSEmmanuel Vadot- dma-channels: Number of channels supported by hardware 8*c66ec88fSEmmanuel Vadot- dma-requests: Number of DMA request lines supported, up to 16 9*c66ec88fSEmmanuel Vadot- dma-masters: Number of AHB masters supported by the controller 10*c66ec88fSEmmanuel Vadot- #dma-cells: must be <3> 11*c66ec88fSEmmanuel Vadot- chan_allocation_order: order of allocation of channel, 0 (default): ascending, 12*c66ec88fSEmmanuel Vadot 1: descending 13*c66ec88fSEmmanuel Vadot- chan_priority: priority of channels. 0 (default): increase from chan 0->n, 1: 14*c66ec88fSEmmanuel Vadot increase from chan n->0 15*c66ec88fSEmmanuel Vadot- block_size: Maximum block size supported by the controller 16*c66ec88fSEmmanuel Vadot- data-width: Maximum data width supported by hardware per AHB master 17*c66ec88fSEmmanuel Vadot (in bytes, power of 2) 18*c66ec88fSEmmanuel Vadot 19*c66ec88fSEmmanuel Vadot 20*c66ec88fSEmmanuel VadotDeprecated properties: 21*c66ec88fSEmmanuel Vadot- data_width: Maximum data width supported by hardware per AHB master 22*c66ec88fSEmmanuel Vadot (0 - 8bits, 1 - 16bits, ..., 5 - 256bits) 23*c66ec88fSEmmanuel Vadot 24*c66ec88fSEmmanuel Vadot 25*c66ec88fSEmmanuel VadotOptional properties: 26*c66ec88fSEmmanuel Vadot- multi-block: Multi block transfers supported by hardware. Array property with 27*c66ec88fSEmmanuel Vadot one cell per channel. 0: not supported, 1 (default): supported. 28*c66ec88fSEmmanuel Vadot- snps,dma-protection-control: AHB HPROT[3:1] protection setting. 29*c66ec88fSEmmanuel Vadot The default value is 0 (for non-cacheable, non-buffered, 30*c66ec88fSEmmanuel Vadot unprivileged data access). 31*c66ec88fSEmmanuel Vadot Refer to include/dt-bindings/dma/dw-dmac.h for possible values. 32*c66ec88fSEmmanuel Vadot 33*c66ec88fSEmmanuel VadotExample: 34*c66ec88fSEmmanuel Vadot 35*c66ec88fSEmmanuel Vadot dmahost: dma@fc000000 { 36*c66ec88fSEmmanuel Vadot compatible = "snps,dma-spear1340"; 37*c66ec88fSEmmanuel Vadot reg = <0xfc000000 0x1000>; 38*c66ec88fSEmmanuel Vadot interrupt-parent = <&vic1>; 39*c66ec88fSEmmanuel Vadot interrupts = <12>; 40*c66ec88fSEmmanuel Vadot 41*c66ec88fSEmmanuel Vadot dma-channels = <8>; 42*c66ec88fSEmmanuel Vadot dma-requests = <16>; 43*c66ec88fSEmmanuel Vadot dma-masters = <2>; 44*c66ec88fSEmmanuel Vadot #dma-cells = <3>; 45*c66ec88fSEmmanuel Vadot chan_allocation_order = <1>; 46*c66ec88fSEmmanuel Vadot chan_priority = <1>; 47*c66ec88fSEmmanuel Vadot block_size = <0xfff>; 48*c66ec88fSEmmanuel Vadot data-width = <8 8>; 49*c66ec88fSEmmanuel Vadot }; 50*c66ec88fSEmmanuel Vadot 51*c66ec88fSEmmanuel VadotDMA clients connected to the Designware DMA controller must use the format 52*c66ec88fSEmmanuel Vadotdescribed in the dma.txt file, using a four-cell specifier for each channel. 53*c66ec88fSEmmanuel VadotThe four cells in order are: 54*c66ec88fSEmmanuel Vadot 55*c66ec88fSEmmanuel Vadot1. A phandle pointing to the DMA controller 56*c66ec88fSEmmanuel Vadot2. The DMA request line number 57*c66ec88fSEmmanuel Vadot3. Memory master for transfers on allocated channel 58*c66ec88fSEmmanuel Vadot4. Peripheral master for transfers on allocated channel 59*c66ec88fSEmmanuel Vadot 60*c66ec88fSEmmanuel VadotExample: 61*c66ec88fSEmmanuel Vadot 62*c66ec88fSEmmanuel Vadot serial@e0000000 { 63*c66ec88fSEmmanuel Vadot compatible = "arm,pl011", "arm,primecell"; 64*c66ec88fSEmmanuel Vadot reg = <0xe0000000 0x1000>; 65*c66ec88fSEmmanuel Vadot interrupts = <0 35 0x4>; 66*c66ec88fSEmmanuel Vadot dmas = <&dmahost 12 0 1>, 67*c66ec88fSEmmanuel Vadot <&dmahost 13 1 0>; 68*c66ec88fSEmmanuel Vadot dma-names = "rx", "rx"; 69*c66ec88fSEmmanuel Vadot }; 70