1Xilinx ZynqMP DMA engine, it does support memory to memory transfers,
2memory to device and device to memory transfers. It also has flow
3control and rate control support for slave/peripheral dma access.
4
5Required properties:
6- compatible		: Should be "xlnx,zynqmp-dma-1.0"
7- reg			: Memory map for gdma/adma module access.
8- interrupts		: Should contain DMA channel interrupt.
9- xlnx,bus-width	: Axi buswidth in bits. Should contain 128 or 64
10- clock-names		: List of input clocks "clk_main", "clk_apb"
11			  (see clock bindings for details)
12
13Optional properties:
14- dma-coherent		: Present if dma operations are coherent.
15
16Example:
17++++++++
18fpd_dma_chan1: dma@fd500000 {
19	compatible = "xlnx,zynqmp-dma-1.0";
20	reg = <0x0 0xFD500000 0x1000>;
21	interrupt-parent = <&gic>;
22	interrupts = <0 117 4>;
23	clock-names = "clk_main", "clk_apb";
24	xlnx,bus-width = <128>;
25	dma-coherent;
26};
27