1*c66ec88fSEmmanuel Vadot* Altera I2C Controller 2*c66ec88fSEmmanuel Vadot* This is Altera's synthesizable logic block I2C Controller for use 3*c66ec88fSEmmanuel Vadot* in Altera's FPGAs. 4*c66ec88fSEmmanuel Vadot 5*c66ec88fSEmmanuel VadotRequired properties : 6*c66ec88fSEmmanuel Vadot - compatible : should be "altr,softip-i2c-v1.0" 7*c66ec88fSEmmanuel Vadot - reg : Offset and length of the register set for the device 8*c66ec88fSEmmanuel Vadot - interrupts : <IRQ> where IRQ is the interrupt number. 9*c66ec88fSEmmanuel Vadot - clocks : phandle to input clock. 10*c66ec88fSEmmanuel Vadot - #address-cells = <1>; 11*c66ec88fSEmmanuel Vadot - #size-cells = <0>; 12*c66ec88fSEmmanuel Vadot 13*c66ec88fSEmmanuel VadotRecommended properties : 14*c66ec88fSEmmanuel Vadot - clock-frequency : desired I2C bus clock frequency in Hz. 15*c66ec88fSEmmanuel Vadot 16*c66ec88fSEmmanuel VadotOptional properties : 17*c66ec88fSEmmanuel Vadot - fifo-size : Size of the RX and TX FIFOs in bytes. 18*c66ec88fSEmmanuel Vadot - Child nodes conforming to i2c bus binding 19*c66ec88fSEmmanuel Vadot 20*c66ec88fSEmmanuel VadotExample : 21*c66ec88fSEmmanuel Vadot 22*c66ec88fSEmmanuel Vadot i2c@100080000 { 23*c66ec88fSEmmanuel Vadot compatible = "altr,softip-i2c-v1.0"; 24*c66ec88fSEmmanuel Vadot reg = <0x00000001 0x00080000 0x00000040>; 25*c66ec88fSEmmanuel Vadot interrupt-parent = <&intc>; 26*c66ec88fSEmmanuel Vadot interrupts = <0 43 4>; 27*c66ec88fSEmmanuel Vadot clocks = <&clk_0>; 28*c66ec88fSEmmanuel Vadot clock-frequency = <100000>; 29*c66ec88fSEmmanuel Vadot #address-cells = <1>; 30*c66ec88fSEmmanuel Vadot #size-cells = <0>; 31*c66ec88fSEmmanuel Vadot fifo-size = <4>; 32*c66ec88fSEmmanuel Vadot 33*c66ec88fSEmmanuel Vadot eeprom@51 { 34*c66ec88fSEmmanuel Vadot compatible = "atmel,24c32"; 35*c66ec88fSEmmanuel Vadot reg = <0x51>; 36*c66ec88fSEmmanuel Vadot pagesize = <32>; 37*c66ec88fSEmmanuel Vadot }; 38*c66ec88fSEmmanuel Vadot }; 39*c66ec88fSEmmanuel Vadot 40