1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/iio/adc/atmel,sama5d2-adc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: AT91 SAMA5D2 Analog to Digital Converter (ADC)
8
9maintainers:
10  - Ludovic Desroches <ludovic.desroches@atmel.com>
11  - Eugen Hristev <eugen.hristev@microchip.com>
12
13properties:
14  compatible:
15    enum:
16      - atmel,sama5d2-adc
17      - microchip,sam9x60-adc
18
19  reg:
20    maxItems: 1
21
22  interrupts:
23    maxItems: 1
24
25  clocks:
26    maxItems: 1
27
28  clock-names:
29    const: adc_clk
30
31  vref-supply: true
32  vddana-supply: true
33
34  atmel,min-sample-rate-hz:
35    description: Minimum sampling rate, it depends on SoC.
36
37  atmel,max-sample-rate-hz:
38    description: Maximum sampling rate, it depends on SoC.
39
40  atmel,startup-time-ms:
41    description: Startup time expressed in ms, it depends on SoC.
42
43  atmel,trigger-edge-type:
44    $ref: '/schemas/types.yaml#/definitions/uint32'
45    description:
46      One of possible edge types for the ADTRG hardware trigger pin.
47      When the specific edge type is detected, the conversion will
48      start. Should be one of IRQ_TYPE_EDGE_RISING, IRQ_TYPE_EDGE_FALLING
49      or IRQ_TYPE_EDGE_BOTH.
50    enum: [1, 2, 3]
51
52  dmas:
53    maxItems: 1
54
55  dma-names:
56    const: rx
57
58  "#io-channel-cells":
59    const: 1
60
61additionalProperties: false
62
63required:
64  - compatible
65  - reg
66  - interrupts
67  - clocks
68  - clock-names
69  - vref-supply
70  - vddana-supply
71  - atmel,min-sample-rate-hz
72  - atmel,max-sample-rate-hz
73  - atmel,startup-time-ms
74  - atmel,trigger-edge-type
75
76examples:
77  - |
78    #include <dt-bindings/dma/at91.h>
79    #include <dt-bindings/interrupt-controller/irq.h>
80    soc {
81        #address-cells = <1>;
82        #size-cells = <1>;
83
84        adc@fc030000 {
85            compatible = "atmel,sama5d2-adc";
86            reg = <0xfc030000 0x100>;
87            interrupts = <40 IRQ_TYPE_LEVEL_HIGH 7>;
88            clocks = <&adc_clk>;
89            clock-names = "adc_clk";
90            atmel,min-sample-rate-hz = <200000>;
91            atmel,max-sample-rate-hz = <20000000>;
92            atmel,startup-time-ms = <4>;
93            vddana-supply = <&vdd_3v3_lp_reg>;
94            vref-supply = <&vdd_3v3_lp_reg>;
95            atmel,trigger-edge-type = <IRQ_TYPE_EDGE_BOTH>;
96            dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(25))>;
97            dma-names = "rx";
98            #io-channel-cells = <1>;
99        };
100    };
101...
102