1Broadcom BCM7038-style Level 1 interrupt controller
2
3This block is a first level interrupt controller that is typically connected
4directly to one of the HW INT lines on each CPU.  Every BCM7xxx set-top chip
5since BCM7038 has contained this hardware.
6
7Key elements of the hardware design include:
8
9- 64, 96, 128, or 160 incoming level IRQ lines
10
11- Most onchip peripherals are wired directly to an L1 input
12
13- A separate instance of the register set for each CPU, allowing individual
14  peripheral IRQs to be routed to any CPU
15
16- Atomic mask/unmask operations
17
18- No polarity/level/edge settings
19
20- No FIFO or priority encoder logic; software is expected to read all
21  2-5 status words to determine which IRQs are pending
22
23Required properties:
24
25- compatible: should be "brcm,bcm7038-l1-intc"
26- reg: specifies the base physical address and size of the registers;
27  the number of supported IRQs is inferred from the size argument
28- interrupt-controller: identifies the node as an interrupt controller
29- #interrupt-cells: specifies the number of cells needed to encode an interrupt
30  source, should be 1.
31- interrupts: specifies the interrupt line(s) in the interrupt-parent controller
32  node; valid values depend on the type of parent interrupt controller
33
34Optional properties:
35
36- brcm,irq-can-wake: If present, this means the L1 controller can be used as a
37  wakeup source for system suspend/resume.
38
39Optional properties:
40
41- brcm,int-fwd-mask: if present, a bit mask to indicate which interrupts
42  have already been configured by the firmware and should be left unmanaged.
43  This should have one 32-bit word per status/set/clear/mask group.
44
45If multiple reg ranges and interrupt-parent entries are present on an SMP
46system, the driver will allow IRQ SMP affinity to be set up through the
47/proc/irq/ interface.  In the simplest possible configuration, only one
48reg range and one interrupt-parent is needed.
49
50Example:
51
52periph_intc: periph_intc@1041a400 {
53        compatible = "brcm,bcm7038-l1-intc";
54        reg = <0x1041a400 0x30 0x1041a600 0x30>;
55
56        interrupt-controller;
57        #interrupt-cells = <1>;
58
59        interrupt-parent = <&cpu_intc>;
60        interrupts = <2>, <3>;
61};
62