1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/interrupt-controller/fsl,irqsteer.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Freescale IRQSTEER Interrupt Multiplexer
8
9maintainers:
10  - Lucas Stach <l.stach@pengutronix.de>
11
12properties:
13  compatible:
14    oneOf:
15      - const: fsl,imx-irqsteer
16      - items:
17          - const: fsl,imx8m-irqsteer
18          - const: fsl,imx-irqsteer
19
20  reg:
21    maxItems: 1
22
23  interrupts:
24    description: |
25      should contain the up to 8 parent interrupt lines used to multiplex
26      the input interrupts. They should be specified sequentially from
27      output 0 to 7.
28    items:
29      - description: output interrupt 0
30      - description: output interrupt 1
31      - description: output interrupt 2
32      - description: output interrupt 3
33      - description: output interrupt 4
34      - description: output interrupt 5
35      - description: output interrupt 6
36      - description: output interrupt 7
37    minItems: 1
38    maxItems: 8
39
40  clocks:
41    maxItems: 1
42
43  clock-names:
44    const: ipg
45
46  interrupt-controller: true
47
48  "#interrupt-cells":
49    const: 1
50
51  fsl,channel:
52    $ref: '/schemas/types.yaml#/definitions/uint32'
53    description: |
54      u32 value representing the output channel that all input IRQs should be
55      steered into.
56
57  fsl,num-irqs:
58    $ref: '/schemas/types.yaml#/definitions/uint32'
59    description: |
60      u32 value representing the number of input interrupts of this channel,
61      should be multiple of 32 input interrupts and up to 512 interrupts.
62
63required:
64  - compatible
65  - reg
66  - interrupts
67  - clocks
68  - clock-names
69  - interrupt-controller
70  - "#interrupt-cells"
71  - fsl,channel
72  - fsl,num-irqs
73
74additionalProperties: false
75
76examples:
77  - |
78    #include <dt-bindings/clock/imx8mq-clock.h>
79    #include <dt-bindings/interrupt-controller/arm-gic.h>
80
81    interrupt-controller@32e2d000 {
82        compatible = "fsl,imx-irqsteer";
83        reg = <0x32e2d000 0x1000>;
84        interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
85        clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>;
86        clock-names = "ipg";
87        fsl,channel = <0>;
88        fsl,num-irqs = <64>;
89        interrupt-controller;
90        #interrupt-cells = <1>;
91    };
92