1Binding for Qualcomm Atheros AR7xxx/AR9XXX CPU interrupt controller
2
3On most SoC the IRQ controller need to flush the DDR FIFO before running
4the interrupt handler of some devices. This is configured using the
5qca,ddr-wb-channels and qca,ddr-wb-channel-interrupts properties.
6
7Required Properties:
8
9- compatible: has to be "qca,<soctype>-cpu-intc", "qca,ar7100-cpu-intc"
10  as fallback
11- interrupt-controller : Identifies the node as an interrupt controller
12- #interrupt-cells : Specifies the number of cells needed to encode interrupt
13		     source, should be 1 for intc
14
15Please refer to interrupts.txt in this directory for details of the common
16Interrupt Controllers bindings used by client devices.
17
18Optional Properties:
19
20- qca,ddr-wb-channel-interrupts: List of the interrupts needing a write
21  buffer flush
22- qca,ddr-wb-channels: List of phandles to the write buffer channels for
23  each interrupt. If qca,ddr-wb-channel-interrupts is not present the interrupt
24  default to the entry's index.
25
26Example:
27
28	interrupt-controller {
29		compatible = "qca,ar9132-cpu-intc", "qca,ar7100-cpu-intc";
30
31		interrupt-controller;
32		#interrupt-cells = <1>;
33
34		qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>;
35		qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>,
36					<&ddr_ctrl 0>, <&ddr_ctrl 1>;
37	};
38
39	...
40
41	ddr_ctrl: memory-controller@18000000 {
42		...
43		#qca,ddr-wb-channel-cells = <1>;
44	};
45