1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/interrupt-controller/renesas,rzg2l-irqc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Renesas RZ/G2L (and alike SoC's) Interrupt Controller (IA55)
8
9maintainers:
10  - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
11  - Geert Uytterhoeven <geert+renesas@glider.be>
12
13description: |
14  IA55 performs various interrupt controls including synchronization for the external
15  interrupts of NMI, IRQ, and GPIOINT and the interrupts of the built-in peripheral
16  interrupts output by each IP. And it notifies the interrupt to the GIC
17    - IRQ sense select for 8 external interrupts, mapped to 8 GIC SPI interrupts
18    - GPIO pins used as external interrupt input pins, mapped to 32 GIC SPI interrupts
19    - NMI edge select (NMI is not treated as NMI exception and supports fall edge and
20      stand-up edge detection interrupts)
21
22allOf:
23  - $ref: /schemas/interrupt-controller.yaml#
24
25properties:
26  compatible:
27    items:
28      - enum:
29          - renesas,r9a07g044-irqc    # RZ/G2{L,LC}
30          - renesas,r9a07g054-irqc    # RZ/V2L
31      - const: renesas,rzg2l-irqc
32
33  '#interrupt-cells':
34    description: The first cell should contain external interrupt number (IRQ0-7) and the
35                 second cell is used to specify the flag.
36    const: 2
37
38  '#address-cells':
39    const: 0
40
41  interrupt-controller: true
42
43  reg:
44    maxItems: 1
45
46  interrupts:
47    maxItems: 41
48
49  clocks:
50    maxItems: 2
51
52  clock-names:
53    items:
54      - const: clk
55      - const: pclk
56
57  power-domains:
58    maxItems: 1
59
60  resets:
61    maxItems: 1
62
63required:
64  - compatible
65  - '#interrupt-cells'
66  - '#address-cells'
67  - interrupt-controller
68  - reg
69  - interrupts
70  - clocks
71  - clock-names
72  - power-domains
73  - resets
74
75unevaluatedProperties: false
76
77examples:
78  - |
79    #include <dt-bindings/interrupt-controller/arm-gic.h>
80    #include <dt-bindings/clock/r9a07g044-cpg.h>
81
82    irqc: interrupt-controller@110a0000 {
83            compatible = "renesas,r9a07g044-irqc", "renesas,rzg2l-irqc";
84            reg = <0x110a0000 0x10000>;
85            #interrupt-cells = <2>;
86            #address-cells = <0>;
87            interrupt-controller;
88            interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
89                         <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
90                         <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
91                         <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
92                         <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
93                         <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
94                         <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
95                         <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
96                         <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
97                         <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
98                         <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>,
99                         <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,
100                         <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
101                         <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
102                         <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
103                         <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
104                         <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
105                         <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
106                         <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>,
107                         <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>,
108                         <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
109                         <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
110                         <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
111                         <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
112                         <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
113                         <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
114                         <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>,
115                         <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
116                         <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
117                         <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
118                         <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
119                         <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
120                         <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
121                         <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
122                         <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
123                         <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
124                         <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
125                         <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
126                         <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
127                         <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
128                         <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>;
129            clocks = <&cpg CPG_MOD R9A07G044_IA55_CLK>,
130                     <&cpg CPG_MOD R9A07G044_IA55_PCLK>;
131            clock-names = "clk", "pclk";
132            power-domains = <&cpg>;
133            resets = <&cpg R9A07G044_IA55_RESETN>;
134    };
135