1*c66ec88fSEmmanuel VadotRISC-V Hart-Level Interrupt Controller (HLIC) 2*c66ec88fSEmmanuel Vadot--------------------------------------------- 3*c66ec88fSEmmanuel Vadot 4*c66ec88fSEmmanuel VadotRISC-V cores include Control Status Registers (CSRs) which are local to each 5*c66ec88fSEmmanuel VadotCPU core (HART in RISC-V terminology) and can be read or written by software. 6*c66ec88fSEmmanuel VadotSome of these CSRs are used to control local interrupts connected to the core. 7*c66ec88fSEmmanuel VadotEvery interrupt is ultimately routed through a hart's HLIC before it 8*c66ec88fSEmmanuel Vadotinterrupts that hart. 9*c66ec88fSEmmanuel Vadot 10*c66ec88fSEmmanuel VadotThe RISC-V supervisor ISA manual specifies three interrupt sources that are 11*c66ec88fSEmmanuel Vadotattached to every HLIC: software interrupts, the timer interrupt, and external 12*c66ec88fSEmmanuel Vadotinterrupts. Software interrupts are used to send IPIs between cores. The 13*c66ec88fSEmmanuel Vadottimer interrupt comes from an architecturally mandated real-time timer that is 14*c66ec88fSEmmanuel Vadotcontrolled via Supervisor Binary Interface (SBI) calls and CSR reads. External 15*c66ec88fSEmmanuel Vadotinterrupts connect all other device interrupts to the HLIC, which are routed 16*c66ec88fSEmmanuel Vadotvia the platform-level interrupt controller (PLIC). 17*c66ec88fSEmmanuel Vadot 18*c66ec88fSEmmanuel VadotAll RISC-V systems that conform to the supervisor ISA specification are 19*c66ec88fSEmmanuel Vadotrequired to have a HLIC with these three interrupt sources present. Since the 20*c66ec88fSEmmanuel Vadotinterrupt map is defined by the ISA it's not listed in the HLIC's device tree 21*c66ec88fSEmmanuel Vadotentry, though external interrupt controllers (like the PLIC, for example) will 22*c66ec88fSEmmanuel Vadotneed to define how their interrupts map to the relevant HLICs. This means 23*c66ec88fSEmmanuel Vadota PLIC interrupt property will typically list the HLICs for all present HARTs 24*c66ec88fSEmmanuel Vadotin the system. 25*c66ec88fSEmmanuel Vadot 26*c66ec88fSEmmanuel VadotRequired properties: 27*c66ec88fSEmmanuel Vadot- compatible : "riscv,cpu-intc" 28*c66ec88fSEmmanuel Vadot- #interrupt-cells : should be <1>. The interrupt sources are defined by the 29*c66ec88fSEmmanuel Vadot RISC-V supervisor ISA manual, with only the following three interrupts being 30*c66ec88fSEmmanuel Vadot defined for supervisor mode: 31*c66ec88fSEmmanuel Vadot - Source 1 is the supervisor software interrupt, which can be sent by an SBI 32*c66ec88fSEmmanuel Vadot call and is reserved for use by software. 33*c66ec88fSEmmanuel Vadot - Source 5 is the supervisor timer interrupt, which can be configured by 34*c66ec88fSEmmanuel Vadot SBI calls and implements a one-shot timer. 35*c66ec88fSEmmanuel Vadot - Source 9 is the supervisor external interrupt, which chains to all other 36*c66ec88fSEmmanuel Vadot device interrupts. 37*c66ec88fSEmmanuel Vadot- interrupt-controller : Identifies the node as an interrupt controller 38*c66ec88fSEmmanuel Vadot 39*c66ec88fSEmmanuel VadotFurthermore, this interrupt-controller MUST be embedded inside the cpu 40*c66ec88fSEmmanuel Vadotdefinition of the hart whose CSRs control these local interrupts. 41*c66ec88fSEmmanuel Vadot 42*c66ec88fSEmmanuel VadotAn example device tree entry for a HLIC is show below. 43*c66ec88fSEmmanuel Vadot 44*c66ec88fSEmmanuel Vadot cpu1: cpu@1 { 45*c66ec88fSEmmanuel Vadot compatible = "riscv"; 46*c66ec88fSEmmanuel Vadot ... 47*c66ec88fSEmmanuel Vadot cpu1-intc: interrupt-controller { 48*c66ec88fSEmmanuel Vadot #interrupt-cells = <1>; 49*c66ec88fSEmmanuel Vadot compatible = "sifive,fu540-c000-cpu-intc", "riscv,cpu-intc"; 50*c66ec88fSEmmanuel Vadot interrupt-controller; 51*c66ec88fSEmmanuel Vadot }; 52*c66ec88fSEmmanuel Vadot }; 53