16be33864SEmmanuel Vadot# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 26be33864SEmmanuel Vadot# Copyright (C) 2020 SiFive, Inc. 36be33864SEmmanuel Vadot%YAML 1.2 46be33864SEmmanuel Vadot--- 56be33864SEmmanuel Vadot$id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml# 66be33864SEmmanuel Vadot$schema: http://devicetree.org/meta-schemas/core.yaml# 76be33864SEmmanuel Vadot 86be33864SEmmanuel Vadottitle: SiFive Platform-Level Interrupt Controller (PLIC) 96be33864SEmmanuel Vadot 106be33864SEmmanuel Vadotdescription: 115def4c47SEmmanuel Vadot SiFive SoCs and other RISC-V SoCs include an implementation of the 125def4c47SEmmanuel Vadot Platform-Level Interrupt Controller (PLIC) high-level specification in 135def4c47SEmmanuel Vadot the RISC-V Privileged Architecture specification. The PLIC connects all 145def4c47SEmmanuel Vadot external interrupts in the system to all hart contexts in the system, via 155def4c47SEmmanuel Vadot the external interrupt source in each hart. 166be33864SEmmanuel Vadot 176be33864SEmmanuel Vadot A hart context is a privilege mode in a hardware execution thread. For example, 186be33864SEmmanuel Vadot in an 4 core system with 2-way SMT, you have 8 harts and probably at least two 196be33864SEmmanuel Vadot privilege modes per hart; machine mode and supervisor mode. 206be33864SEmmanuel Vadot 216be33864SEmmanuel Vadot Each interrupt can be enabled on per-context basis. Any context can claim 226be33864SEmmanuel Vadot a pending enabled interrupt and then release it once it has been handled. 236be33864SEmmanuel Vadot 246be33864SEmmanuel Vadot Each interrupt has a configurable priority. Higher priority interrupts are 256be33864SEmmanuel Vadot serviced first. Each context can specify a priority threshold. Interrupts 266be33864SEmmanuel Vadot with priority below this threshold will not cause the PLIC to raise its 276be33864SEmmanuel Vadot interrupt line leading to the context. 286be33864SEmmanuel Vadot 29b97ee269SEmmanuel Vadot The PLIC supports both edge-triggered and level-triggered interrupts. For 30b97ee269SEmmanuel Vadot edge-triggered interrupts, the RISC-V PLIC spec allows two responses to edges 31b97ee269SEmmanuel Vadot seen while an interrupt handler is active; the PLIC may either queue them or 32b97ee269SEmmanuel Vadot ignore them. In the first case, handlers are oblivious to the trigger type, so 33b97ee269SEmmanuel Vadot it is not included in the interrupt specifier. In the second case, software 34b97ee269SEmmanuel Vadot needs to know the trigger type, so it can reorder the interrupt flow to avoid 35b97ee269SEmmanuel Vadot missing interrupts. This special handling is needed by at least the Renesas 36b97ee269SEmmanuel Vadot RZ/Five SoC (AX45MP AndesCore with a NCEPLIC100) and the T-HEAD C900 PLIC. 376be33864SEmmanuel Vadot 386be33864SEmmanuel Vadot While the RISC-V ISA doesn't specify a memory layout for the PLIC, the 396be33864SEmmanuel Vadot "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that 406be33864SEmmanuel Vadot contains a specific memory layout, which is documented in chapter 8 of the 416be33864SEmmanuel Vadot SiFive U5 Coreplex Series Manual <https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf>. 426be33864SEmmanuel Vadot 43e67e8565SEmmanuel Vadot The thead,c900-plic is different from sifive,plic-1.0.0 in opensbi, the 44e67e8565SEmmanuel Vadot T-HEAD PLIC implementation requires setting a delegation bit to allow access 45e67e8565SEmmanuel Vadot from S-mode. So add thead,c900-plic to distinguish them. 46e67e8565SEmmanuel Vadot 476be33864SEmmanuel Vadotmaintainers: 486be33864SEmmanuel Vadot - Paul Walmsley <paul.walmsley@sifive.com> 496be33864SEmmanuel Vadot - Palmer Dabbelt <palmer@dabbelt.com> 506be33864SEmmanuel Vadot 516be33864SEmmanuel Vadotproperties: 526be33864SEmmanuel Vadot compatible: 53e67e8565SEmmanuel Vadot oneOf: 54e67e8565SEmmanuel Vadot - items: 555def4c47SEmmanuel Vadot - enum: 56b97ee269SEmmanuel Vadot - renesas,r9a07g043-plic 57b97ee269SEmmanuel Vadot - const: andestech,nceplic100 58b97ee269SEmmanuel Vadot - items: 59b97ee269SEmmanuel Vadot - enum: 60*f126890aSEmmanuel Vadot - canaan,k210-plic 615def4c47SEmmanuel Vadot - sifive,fu540-c000-plic 62e67e8565SEmmanuel Vadot - starfive,jh7100-plic 63fac71e4eSEmmanuel Vadot - starfive,jh7110-plic 646be33864SEmmanuel Vadot - const: sifive,plic-1.0.0 65e67e8565SEmmanuel Vadot - items: 66e67e8565SEmmanuel Vadot - enum: 67e67e8565SEmmanuel Vadot - allwinner,sun20i-d1-plic 68*f126890aSEmmanuel Vadot - thead,th1520-plic 69e67e8565SEmmanuel Vadot - const: thead,c900-plic 707ef62cebSEmmanuel Vadot - items: 717ef62cebSEmmanuel Vadot - const: sifive,plic-1.0.0 727ef62cebSEmmanuel Vadot - const: riscv,plic0 737ef62cebSEmmanuel Vadot deprecated: true 747ef62cebSEmmanuel Vadot description: For the QEMU virt machine only 756be33864SEmmanuel Vadot 766be33864SEmmanuel Vadot reg: 776be33864SEmmanuel Vadot maxItems: 1 786be33864SEmmanuel Vadot 796be33864SEmmanuel Vadot '#address-cells': 806be33864SEmmanuel Vadot const: 0 816be33864SEmmanuel Vadot 82b97ee269SEmmanuel Vadot '#interrupt-cells': true 836be33864SEmmanuel Vadot 846be33864SEmmanuel Vadot interrupt-controller: true 856be33864SEmmanuel Vadot 866be33864SEmmanuel Vadot interrupts-extended: 876be33864SEmmanuel Vadot minItems: 1 88e67e8565SEmmanuel Vadot maxItems: 15872 896be33864SEmmanuel Vadot description: 906be33864SEmmanuel Vadot Specifies which contexts are connected to the PLIC, with "-1" specifying 916be33864SEmmanuel Vadot that a context is not present. Each node pointed to should be a 926be33864SEmmanuel Vadot riscv,cpu-intc node, which has a riscv node as parent. 936be33864SEmmanuel Vadot 946be33864SEmmanuel Vadot riscv,ndev: 95fac71e4eSEmmanuel Vadot $ref: /schemas/types.yaml#/definitions/uint32 966be33864SEmmanuel Vadot description: 976be33864SEmmanuel Vadot Specifies how many external interrupts are supported by this controller. 986be33864SEmmanuel Vadot 99b97ee269SEmmanuel Vadot clocks: true 100b97ee269SEmmanuel Vadot 101b97ee269SEmmanuel Vadot power-domains: true 102b97ee269SEmmanuel Vadot 103b97ee269SEmmanuel Vadot resets: true 104b97ee269SEmmanuel Vadot 1056be33864SEmmanuel Vadotrequired: 1066be33864SEmmanuel Vadot - compatible 1076be33864SEmmanuel Vadot - '#address-cells' 1086be33864SEmmanuel Vadot - '#interrupt-cells' 1096be33864SEmmanuel Vadot - interrupt-controller 1106be33864SEmmanuel Vadot - reg 1116be33864SEmmanuel Vadot - interrupts-extended 1126be33864SEmmanuel Vadot - riscv,ndev 1136be33864SEmmanuel Vadot 114b97ee269SEmmanuel VadotallOf: 115b97ee269SEmmanuel Vadot - if: 116b97ee269SEmmanuel Vadot properties: 117b97ee269SEmmanuel Vadot compatible: 118b97ee269SEmmanuel Vadot contains: 119b97ee269SEmmanuel Vadot enum: 120b97ee269SEmmanuel Vadot - andestech,nceplic100 121b97ee269SEmmanuel Vadot - thead,c900-plic 122b97ee269SEmmanuel Vadot 123b97ee269SEmmanuel Vadot then: 124b97ee269SEmmanuel Vadot properties: 125b97ee269SEmmanuel Vadot '#interrupt-cells': 126b97ee269SEmmanuel Vadot const: 2 127b97ee269SEmmanuel Vadot 128b97ee269SEmmanuel Vadot else: 129b97ee269SEmmanuel Vadot properties: 130b97ee269SEmmanuel Vadot '#interrupt-cells': 131b97ee269SEmmanuel Vadot const: 1 132b97ee269SEmmanuel Vadot 133b97ee269SEmmanuel Vadot - if: 134b97ee269SEmmanuel Vadot properties: 135b97ee269SEmmanuel Vadot compatible: 136b97ee269SEmmanuel Vadot contains: 137b97ee269SEmmanuel Vadot const: renesas,r9a07g043-plic 138b97ee269SEmmanuel Vadot 139b97ee269SEmmanuel Vadot then: 140b97ee269SEmmanuel Vadot properties: 141b97ee269SEmmanuel Vadot clocks: 142b97ee269SEmmanuel Vadot maxItems: 1 143b97ee269SEmmanuel Vadot 144b97ee269SEmmanuel Vadot power-domains: 145b97ee269SEmmanuel Vadot maxItems: 1 146b97ee269SEmmanuel Vadot 147b97ee269SEmmanuel Vadot resets: 148b97ee269SEmmanuel Vadot maxItems: 1 149b97ee269SEmmanuel Vadot 150b97ee269SEmmanuel Vadot required: 151b97ee269SEmmanuel Vadot - clocks 152b97ee269SEmmanuel Vadot - power-domains 153b97ee269SEmmanuel Vadot - resets 154b97ee269SEmmanuel Vadot 1556be33864SEmmanuel VadotadditionalProperties: false 1566be33864SEmmanuel Vadot 1576be33864SEmmanuel Vadotexamples: 1586be33864SEmmanuel Vadot - | 1596be33864SEmmanuel Vadot plic: interrupt-controller@c000000 { 1606be33864SEmmanuel Vadot #address-cells = <0>; 1616be33864SEmmanuel Vadot #interrupt-cells = <1>; 1626be33864SEmmanuel Vadot compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0"; 1636be33864SEmmanuel Vadot interrupt-controller; 164e67e8565SEmmanuel Vadot interrupts-extended = <&cpu0_intc 11>, 165e67e8565SEmmanuel Vadot <&cpu1_intc 11>, <&cpu1_intc 9>, 166e67e8565SEmmanuel Vadot <&cpu2_intc 11>, <&cpu2_intc 9>, 167e67e8565SEmmanuel Vadot <&cpu3_intc 11>, <&cpu3_intc 9>, 168e67e8565SEmmanuel Vadot <&cpu4_intc 11>, <&cpu4_intc 9>; 1696be33864SEmmanuel Vadot reg = <0xc000000 0x4000000>; 1706be33864SEmmanuel Vadot riscv,ndev = <10>; 1716be33864SEmmanuel Vadot }; 172